JP6729523B2 - 炭化珪素半導体装置およびその製造方法 - Google Patents

炭化珪素半導体装置およびその製造方法 Download PDF

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JP6729523B2
JP6729523B2 JP2017166882A JP2017166882A JP6729523B2 JP 6729523 B2 JP6729523 B2 JP 6729523B2 JP 2017166882 A JP2017166882 A JP 2017166882A JP 2017166882 A JP2017166882 A JP 2017166882A JP 6729523 B2 JP6729523 B2 JP 6729523B2
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layer
current spreading
region
spreading layer
silicon carbide
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JP2019046908A (ja
JP2019046908A5 (enExample
Inventor
周平 箕谷
周平 箕谷
愛子 梶
愛子 梶
康裕 海老原
康裕 海老原
永岡 達司
達司 永岡
佐智子 青井
佐智子 青井
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Denso Corp
Toyota Motor Corp
Toyota Central R&D Labs Inc
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Denso Corp
Toyota Motor Corp
Toyota Central R&D Labs Inc
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Priority to JP2017166882A priority Critical patent/JP6729523B2/ja
Priority to PCT/JP2018/032004 priority patent/WO2019044921A1/ja
Priority to CN201880055698.3A priority patent/CN111066152B/zh
Publication of JP2019046908A publication Critical patent/JP2019046908A/ja
Publication of JP2019046908A5 publication Critical patent/JP2019046908A5/ja
Priority to US16/776,821 priority patent/US11063145B2/en
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/64Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66Vertical DMOS [VDMOS] FETs
    • H10D30/668Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/01Manufacture or treatment
    • H10D12/031Manufacture or treatment of IGBTs
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/01Manufacture or treatment
    • H10D12/031Manufacture or treatment of IGBTs
    • H10D12/032Manufacture or treatment of IGBTs of vertical IGBTs
    • H10D12/038Manufacture or treatment of IGBTs of vertical IGBTs having a recessed gate, e.g. trench-gate IGBTs
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/01Manufacture or treatment
    • H10D30/021Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0291Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
    • H10D30/0297Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs using recessing of the gate electrodes, e.g. to form trench gate electrodes
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/64Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66Vertical DMOS [VDMOS] FETs
    • H10D30/665Vertical DMOS [VDMOS] FETs having edge termination structures
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/01Manufacture or treatment
    • H10D62/051Forming charge compensation regions, e.g. superjunctions
    • H10D62/054Forming charge compensation regions, e.g. superjunctions by high energy implantations in bulk semiconductor bodies, e.g. forming pillars
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/109Reduced surface field [RESURF] PN junction structures
    • H10D62/111Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149Source or drain regions of field-effect devices
    • H10D62/151Source or drain regions of field-effect devices of IGFETs 
    • H10D62/156Drain regions of DMOS transistors
    • H10D62/157Impurity concentrations or distributions
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/393Body regions of DMOS transistors or IGBTs 
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/832Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
    • H10D62/8325Silicon carbide

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  • Electrodes Of Semiconductors (AREA)
JP2017166882A 2017-08-31 2017-08-31 炭化珪素半導体装置およびその製造方法 Active JP6729523B2 (ja)

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JP2017166882A JP6729523B2 (ja) 2017-08-31 2017-08-31 炭化珪素半導体装置およびその製造方法
PCT/JP2018/032004 WO2019044921A1 (ja) 2017-08-31 2018-08-29 炭化珪素半導体装置およびその製造方法
CN201880055698.3A CN111066152B (zh) 2017-08-31 2018-08-29 碳化硅半导体装置及其制造方法
US16/776,821 US11063145B2 (en) 2017-08-31 2020-01-30 Silicon carbide semiconductor device and method for manufacturing same

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JP2017166882A JP6729523B2 (ja) 2017-08-31 2017-08-31 炭化珪素半導体装置およびその製造方法

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JP2019046908A5 JP2019046908A5 (enExample) 2019-11-28
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WO (1) WO2019044921A1 (enExample)

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Publication number Priority date Publication date Assignee Title
JP7180402B2 (ja) 2019-01-21 2022-11-30 株式会社デンソー 半導体装置
JP7379880B2 (ja) * 2019-06-21 2023-11-15 富士電機株式会社 半導体装置
JP7425943B2 (ja) * 2019-12-12 2024-02-01 株式会社デンソー 炭化珪素半導体装置
JP7443924B2 (ja) 2020-05-14 2024-03-06 富士電機株式会社 半導体装置
JP7532921B2 (ja) 2020-06-09 2024-08-14 富士電機株式会社 半導体装置
JP7458257B2 (ja) 2020-07-09 2024-03-29 株式会社東芝 半導体装置、インバータ回路、駆動装置、車両、及び、昇降機
JP2022021181A (ja) 2020-07-21 2022-02-02 株式会社デンソー 半導体装置
KR102812224B1 (ko) * 2021-03-03 2025-05-22 주식회사 디비하이텍 에피택셜층의 유효 두께 차등 구조를 가지는 슈퍼정션 반도체 소자 및 제조방법
JP7476132B2 (ja) * 2021-03-23 2024-04-30 株式会社東芝 半導体装置、インバータ回路、駆動装置、車両、及び、昇降機
JP7521553B2 (ja) * 2021-03-24 2024-07-24 株式会社デンソー 炭化珪素半導体装置およびそれを用いたインバータ回路、炭化珪素半導体装置の製造方法
WO2022202936A1 (ja) * 2021-03-24 2022-09-29 株式会社デンソー 炭化珪素半導体装置およびそれを用いたインバータ回路、炭化珪素半導体装置の製造方法
JP7582061B2 (ja) * 2021-05-14 2024-11-13 株式会社デンソー 半導体装置
JP7593225B2 (ja) * 2021-05-14 2024-12-03 株式会社デンソー 炭化珪素半導体装置
JP7593235B2 (ja) * 2021-05-28 2024-12-03 株式会社デンソー 半導体装置
JP7619168B2 (ja) * 2021-06-01 2025-01-22 株式会社デンソー 半導体装置
JP7673513B2 (ja) * 2021-06-15 2025-05-09 株式会社デンソー 半導体装置
JP7651403B2 (ja) 2021-08-05 2025-03-26 株式会社デンソー 電界効果トランジスタとその製造方法
JP7687171B2 (ja) * 2021-09-28 2025-06-03 株式会社デンソー 半導体装置およびその製造方法
JP7704007B2 (ja) * 2021-11-09 2025-07-08 株式会社デンソー 半導体装置の製造方法
JP7683466B2 (ja) * 2021-11-17 2025-05-27 株式会社デンソー 半導体装置およびその製造方法
JP7717010B2 (ja) * 2022-03-08 2025-08-01 株式会社デンソー 半導体装置
JP7757235B2 (ja) * 2022-05-13 2025-10-21 株式会社デンソー 半導体装置とその製造方法
JP2024025440A (ja) * 2022-08-12 2024-02-26 株式会社デンソー 炭化珪素半導体装置
WO2025052689A1 (ja) * 2023-09-04 2025-03-13 株式会社 東芝 半導体装置
CN118800806B (zh) * 2024-09-11 2025-01-10 陕西半导体先导技术中心有限公司 一种带有突出p阱的umosfet器件及其制备方法

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5252813B2 (ja) * 2007-03-15 2013-07-31 株式会社豊田中央研究所 半導体装置の製造方法
CN100565879C (zh) * 2008-01-08 2009-12-02 苏州硅能半导体科技股份有限公司 一种深沟槽大功率mos器件及其制造方法
EP2091083A3 (en) 2008-02-13 2009-10-14 Denso Corporation Silicon carbide semiconductor device including a deep layer
JP2009302436A (ja) * 2008-06-17 2009-12-24 Denso Corp 炭化珪素半導体装置の製造方法
US8415671B2 (en) * 2010-04-16 2013-04-09 Cree, Inc. Wide band-gap MOSFETs having a heterojunction under gate trenches thereof and related methods of forming such devices
JP5531787B2 (ja) * 2010-05-31 2014-06-25 株式会社デンソー 炭化珪素半導体装置およびその製造方法
JP2012169384A (ja) * 2011-02-11 2012-09-06 Denso Corp 炭化珪素半導体装置およびその製造方法
JP5728992B2 (ja) 2011-02-11 2015-06-03 株式会社デンソー 炭化珪素半導体装置およびその製造方法
JP5812029B2 (ja) * 2012-06-13 2015-11-11 株式会社デンソー 炭化珪素半導体装置およびその製造方法
US8637922B1 (en) * 2012-07-19 2014-01-28 Infineon Technologies Ag Semiconductor device
CN107768427A (zh) * 2013-06-12 2018-03-06 三菱电机株式会社 半导体装置
JP2015072999A (ja) * 2013-10-02 2015-04-16 株式会社デンソー 炭化珪素半導体装置
JP6237408B2 (ja) 2014-03-28 2017-11-29 住友電気工業株式会社 炭化珪素半導体装置およびその製造方法

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JP2019046908A (ja) 2019-03-22
WO2019044921A1 (ja) 2019-03-07
CN111066152A (zh) 2020-04-24
US11063145B2 (en) 2021-07-13
US20200168732A1 (en) 2020-05-28
CN111066152B (zh) 2023-07-21

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