JP6657183B2 - 高ブレークダウンｎ型埋め込み層 - Google Patents

高ブレークダウンｎ型埋め込み層 Download PDF

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JP6657183B2
JP6657183B2 JP2017507937A JP2017507937A JP6657183B2 JP 6657183 B2 JP6657183 B2 JP 6657183B2 JP 2017507937 A JP2017507937 A JP 2017507937A JP 2017507937 A JP2017507937 A JP 2017507937A JP 6657183 B2 JP6657183 B2 JP 6657183B2
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semiconductor device
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semiconductor
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JP2017514319A5 (enExample
JP2017514319A (ja
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ピー ペンハルカル サミール
ピー ペンハルカル サミール
フー ビンホワ
フー ビンホワ
リッツマン エドワーズ ヘンリー
リッツマン エドワーズ ヘンリー
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日本テキサス・インスツルメンツ合同会社
テキサス インスツルメンツ インコーポレイテッド
テキサス インスツルメンツ インコーポレイテッド
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
    • H10D62/107—Buried supplementary regions, e.g. buried guard rings 
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2252—Diffusion into or out of group IV semiconductors using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase
    • H01L21/2253—Diffusion into or out of group IV semiconductors using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase by ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H01L21/2652—Through-implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/113—Isolations within a component, i.e. internal isolations
    • H10D62/114—PN junction isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/834—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge further characterised by the dopants
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/62—Electrodes ohmically coupled to a semiconductor

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Element Separation (AREA)
  • Bipolar Transistors (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
JP2017507937A 2014-04-25 2015-04-27 高ブレークダウンｎ型埋め込み層 Active JP6657183B2 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201461984205P 2014-04-25 2014-04-25
US61/984,205 2014-04-25
US14/555,330 US9385187B2 (en) 2014-04-25 2014-11-26 High breakdown N-type buried layer
US14/555,330 2014-11-26
PCT/US2015/027699 WO2015164853A1 (en) 2014-04-25 2015-04-27 High breakdown n-type buried layer

Publications (3)

Publication Number Publication Date
JP2017514319A JP2017514319A (ja) 2017-06-01
JP2017514319A5 JP2017514319A5 (enExample) 2018-06-07
JP6657183B2 true JP6657183B2 (ja) 2020-03-04

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US (2) US9385187B2 (enExample)
JP (1) JP6657183B2 (enExample)
CN (1) CN106233439B (enExample)
WO (1) WO2015164853A1 (enExample)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9385187B2 (en) * 2014-04-25 2016-07-05 Texas Instruments Incorporated High breakdown N-type buried layer
DE102017103782B4 (de) * 2017-02-23 2021-03-25 Infineon Technologies Ag Halbleitervorrichtung mit einer vergrabenen Schicht und Herstellungsverfahren hierfür
FR3089679A1 (fr) 2018-12-11 2020-06-12 Stmicroelectronics (Tours) Sas Dispositif de commutation et procédé de fabrication d'un tel dispositif
CN114695505B (zh) * 2020-12-29 2025-01-24 无锡华润上华科技有限公司 电子设备、半导体器件及其制备方法
CN118041270A (zh) * 2022-11-04 2024-05-14 广州乐仪投资有限公司 半导体结构的制备方法、半导体结构及电子设备

Family Cites Families (45)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4666556A (en) 1986-05-12 1987-05-19 International Business Machines Corporation Trench sidewall isolation by polysilicon oxidation
US4980747A (en) 1986-12-22 1990-12-25 Texas Instruments Inc. Deep trench isolation with surface contact to substrate
JPH0271526A (ja) * 1988-07-07 1990-03-12 Matsushita Electric Ind Co Ltd 半導体集積回路およびその製造方法
JPH0442959A (ja) * 1990-06-06 1992-02-13 Fujitsu Ltd 半導体集積回路装置
GB2248142A (en) * 1990-09-19 1992-03-25 Koninkl Philips Electronics Nv A method of manufacturing a semiconductor device
US5192708A (en) * 1991-04-29 1993-03-09 International Business Machines Corporation Sub-layer contact technique using in situ doped amorphous silicon and solid phase recrystallization
JPH0536823A (ja) * 1991-08-01 1993-02-12 Mitsubishi Electric Corp 半導体集積回路
US5994755A (en) * 1991-10-30 1999-11-30 Intersil Corporation Analog-to-digital converter and method of fabrication
JPH0799771B2 (ja) 1992-06-26 1995-10-25 インターナショナル・ビジネス・マシーンズ・コーポレイション 皮膜中の応力を制御する方法
JP3285435B2 (ja) * 1993-07-07 2002-05-27 三菱電機株式会社 半導体装置およびその製造方法
JPH08236614A (ja) * 1995-02-27 1996-09-13 Nippondenso Co Ltd 半導体装置の製造方法
JP3334027B2 (ja) * 1996-02-06 2002-10-15 富士電機株式会社 高耐圧横型半導体装置
US6218722B1 (en) 1997-02-14 2001-04-17 Gennum Corporation Antifuse based on silicided polysilicon bipolar transistor
JPH11251447A (ja) * 1998-02-27 1999-09-17 Nippon Foundry Inc 半導体装置及びその製造方法
US20010013610A1 (en) * 1999-08-02 2001-08-16 Min-Hwa Chi Vertical bipolar transistor based on gate induced drain leakage current
US6661042B2 (en) * 2002-03-11 2003-12-09 Monolithic System Technology, Inc. One-transistor floating-body DRAM cell in bulk CMOS process with electrically isolated charge storage region
US6943426B2 (en) 2002-08-14 2005-09-13 Advanced Analogic Technologies, Inc. Complementary analog bipolar transistors with trench-constrained isolation diffusion
US7041572B2 (en) 2002-10-25 2006-05-09 Vanguard International Semiconductor Corporation Fabrication method for a deep trench isolation structure of a high-voltage device
US7635621B2 (en) * 2002-11-22 2009-12-22 Micrel, Inc. Lateral double-diffused metal oxide semiconductor (LDMOS) device with an enhanced drift region that has an improved Ron area product
SE526366C3 (sv) * 2003-03-21 2005-10-26 Silex Microsystems Ab Elektriska anslutningar i substrat
US6815780B1 (en) 2003-04-15 2004-11-09 Motorola, Inc. Semiconductor component with substrate injection protection structure
JP4292964B2 (ja) * 2003-08-08 2009-07-08 三菱電機株式会社 縦型半導体装置
US7639713B2 (en) 2004-01-21 2009-12-29 Emc Corporation Database block network attached storage packet joining
JP4592340B2 (ja) 2004-06-29 2010-12-01 三洋電機株式会社 半導体装置の製造方法
KR100797896B1 (ko) * 2004-11-12 2008-01-24 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 다양한 동작 전압들을 갖는 집적 회로들을 절연시키기 위한반도체 구조
US7772100B2 (en) * 2005-03-24 2010-08-10 Nxp B.V. Method of manufacturing a semiconductor device having a buried doped region
CN1897282A (zh) * 2005-06-30 2007-01-17 St微电子克鲁勒斯图股份公司 包括具有隔离体的一个mos晶体管的存储单元
US7723204B2 (en) 2006-03-27 2010-05-25 Freescale Semiconductor, Inc. Semiconductor device with a multi-plate isolation structure
US7410862B2 (en) 2006-04-28 2008-08-12 International Business Machines Corporation Trench capacitor and method for fabricating the same
US8420483B2 (en) * 2007-01-09 2013-04-16 Maxpower Semiconductor, Inc. Method of manufacture for a semiconductor device
US8614151B2 (en) 2008-01-04 2013-12-24 Micron Technology, Inc. Method of etching a high aspect ratio contact
US7989875B2 (en) * 2008-11-24 2011-08-02 Nxp B.V. BiCMOS integration of multiple-times-programmable non-volatile memories
KR101610826B1 (ko) 2009-03-18 2016-04-11 삼성전자주식회사 커패시터를 갖는 반도체 장치의 형성방법
US8476530B2 (en) 2009-06-22 2013-07-02 International Business Machines Corporation Self-aligned nano-scale device with parallel plate electrodes
US20110062554A1 (en) 2009-09-17 2011-03-17 Hsing Michael R High voltage floating well in a silicon die
US8334190B2 (en) 2010-05-07 2012-12-18 Texas Instruments Incorporated Single step CMP for polishing three or more layer film stacks
US8399924B2 (en) 2010-06-17 2013-03-19 Texas Instruments Incorporated High voltage transistor using diluted drain
JP5743831B2 (ja) * 2011-09-29 2015-07-01 株式会社東芝 半導体装置
US8785971B2 (en) * 2011-11-23 2014-07-22 Amazing Microelectronic Corp. Transient voltage suppressor without leakage current
US8642423B2 (en) * 2011-11-30 2014-02-04 International Business Machines Corporation Polysilicon/metal contact resistance in deep trench
US9356133B2 (en) * 2012-02-01 2016-05-31 Texas Instruments Incorporated Medium voltage MOSFET device
US9293357B2 (en) 2012-07-02 2016-03-22 Texas Instruments Incorporated Sinker with a reduced width
US9082719B2 (en) 2012-10-19 2015-07-14 Infineon Technologies Ag Method for removing a dielectric layer from a bottom of a trench
US9136368B2 (en) * 2013-10-03 2015-09-15 Texas Instruments Incorporated Trench gate trench field plate semi-vertical semi-lateral MOSFET
US9385187B2 (en) * 2014-04-25 2016-07-05 Texas Instruments Incorporated High breakdown N-type buried layer

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Publication number Publication date
US9673273B2 (en) 2017-06-06
CN106233439B (zh) 2021-01-01
US20160315141A1 (en) 2016-10-27
US20150311281A1 (en) 2015-10-29
US9385187B2 (en) 2016-07-05
WO2015164853A1 (en) 2015-10-29
JP2017514319A (ja) 2017-06-01
CN106233439A (zh) 2016-12-14

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