US20110062554A1 - High voltage floating well in a silicon die - Google Patents

High voltage floating well in a silicon die Download PDF

Info

Publication number
US20110062554A1
US20110062554A1 US12562083 US56208309A US20110062554A1 US 20110062554 A1 US20110062554 A1 US 20110062554A1 US 12562083 US12562083 US 12562083 US 56208309 A US56208309 A US 56208309A US 20110062554 A1 US20110062554 A1 US 20110062554A1
Authority
US
Grant status
Application
Patent type
Prior art keywords
doped
region
fig
well
resistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US12562083
Inventor
Michael R. Hsing
James C. Moyer
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Monolithic Power Systems Inc
Original Assignee
Monolithic Power Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Images

Classifications

    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K17/00Electronic switching or gating, i.e. not by contact-making or -braking
    • H03K17/08Modifications for protecting switching circuit against overcurrent or overvoltage
    • H03K17/082Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output circuit to the control circuit
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/761PN junctions
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L28/00Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/20Resistors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/107Substrate region of field-effect devices
    • H01L29/1075Substrate region of field-effect devices of field-effect transistors
    • H01L29/1079Substrate region of field-effect devices of field-effect transistors with insulated gate
    • H01L29/1087Substrate region of field-effect devices of field-effect transistors with insulated gate characterised by the contact structure of the substrate region, e.g. for controlling or preventing bipolar effect
    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00Conversion of dc power input into dc power output
    • H02M3/02Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/158Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
    • H02M3/1588Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load comprising at least one synchronous rectifier element
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02BCLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion
    • Y02B70/14Reduction of losses in power supplies
    • Y02B70/1458Synchronous rectification
    • Y02B70/1466Synchronous rectification in non-galvanically isolated DC/DC converters

Abstract

In one embodiment, a graded n-doped region surrounding a well, and a spiral resistor connected to the well and to a p-doped region surrounding the graded n-doped region.

Description

    FIELD
  • [0001]
    The present invention relates to semiconductor electronics.
  • BACKGROUND
  • [0002]
    Many DC-to-DC power converters may be conceptualized by the circuit illustrated in FIG. 1, where electrical power from a source having a supply voltage VIN is provided to load 102 such that the load voltage is regulated to some voltage less than VIN. A feedback path is provided from node 103 to controller 104, where controller 104 controls the duty cycle of high-side switch 106 and low-side switch 108 to regulate the load voltage. A second-order low pass filter comprising inductor 110 and capacitor 112 couples load 102 to switch point 114 so as to smooth output ripples. In practice, switches 106 and 108 are power MOSFETs (Metal-Oxide-Semiconductor-Field-Effect-Transistor), where each power MOSFET is realized by a large number of individual MOSFETs connected in parallel. The operating principles for the circuit of FIG. 1 are well known to those skilled in the art of power converters, and need not be repeated here.
  • [0003]
    For some consumer applications, the supply voltage VIN may peak to several hundred volts, in which case the voltage drop across switch 106 or 108 may also peak to several hundred volts. Accordingly, for such applications, switches 106 and 108 should be designed to operate under such high voltage drops.
  • [0004]
    In practice, most or all of the circuit components in an embodiment, except for inductor 110, capacitor 112, load 102, and perhaps some discrete resistors and capacitors, are integrated on a single silicon die. Some circuit components within controller 104 may be connected to the supply voltage VIN. However, various circuit components within controller 104 may in practice be designed to operate over voltage drops not to exceed on the order of ten volts. For example, a circuit block within controller 104 may be connected to a high voltage pin, yet the circuit block may be designed for voltage drops not to exceed on the order of ten volts. Accordingly, it is desirable to electrically isolate such circuits from high voltage drops to avoid device breakdown.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • [0005]
    FIG. 1 illustrates a prior art DC-to-DC power converter.
  • [0006]
    FIG. 2 illustrates a cross-sectional plan view of an embodiment.
  • [0007]
    FIG. 3 illustrates a top plan view of an embodiment.
  • DESCRIPTION OF EMBODIMENTS
  • [0008]
    In the description that follows, the scope of the term “some embodiments” is not to be so limited as to mean more than one embodiment, but rather, the scope may include one embodiment, more than one embodiment, or perhaps all embodiments.
  • [0009]
    Although embodiments find application to DC-to-DC power converters, embodiments are not limited to such applications. In this Description of Embodiments, the region of the silicon die that is electrically isolated from high voltage drops may be termed a floating well.
  • [0010]
    FIG. 2 illustrates a cross-sectional plan view of a portion of a silicon die according to an embodiment. For ease of illustration, FIG. 2 is not drawn to scale, and various doped regions are idealized as rectangles. For reference, shown in FIG. 2 is a coordinate system with x-axis 202 and z-axis 204 lying in the plane of illustration, with y-axis 206 pointing into the plane of the illustration. With the coordinate system as shown, the cross-sectional view illustrated in FIG. 2 is taken as a slice of an embodiment, with the slice perpendicular to y-axis 206.
  • [0011]
    FIG. 3 illustrates a cross-sectional plan view of a portion of the silicon die according to an embodiment, but with a different view than that of FIG. 2. To provide relative orientations of the embodiment of FIG. 2 and the embodiment of FIG. 3, the coordinate system in FIG. 2 is also shown in FIG. 3, making clear that the cross-sectional view illustrated in FIG. 3 is a slice of an embodiment, with the slice taken perpendicular to z-axis 204. For ease of illustration, FIG. 3 is not drawn to scale.
  • [0012]
    Referring to FIG. 2, formed in p-doped substrate 208 is n-doped buried layer 210. Adjacent to n-doped buried layer 210 are several regions of the silicon die, where for simplicity only three such regions are illustrated in FIG. 2, and are labeled 212, 214, 216, and 218. Regions 212 and 216 are n-doped regions, and regions 214 and 218 are p-doped regions. Other embodiments may have more or less such regions adjacent to n-doped buried layer 210, but the outermost region adjacent to n-doped buried layer 210 is n-doped.
  • [0013]
    Region 212 in FIG. 2 appears noncontiguous only because of the way the slice is taken to provide the view of the illustration, but for the embodiments of FIGS. 2 and 3, region 212 is contiguous and surrounds n-doped buried layer 210. This is made clear by the view illustrated in FIG. 3, where dashed circle 302 in FIG. 3 corresponds to outer edge 302 of n-doped buried layer 210 in FIG. 2, and dashed circles 304 and 306 in FIG. 3 correspond, respectively, to junctions 304 and 306 in FIG. 2, where junction 304 is the junction between n-doped regions 212 and 220, and junction 306 is the junction between n-doped regions 220 and 222.
  • [0014]
    Region 212 lies between dashed circles 301 and 304 in FIG. 3, and is shown as an annulus. However, in practice n-doped region 212 may not be exactly circular in shape, and for some embodiments, n-doped region 212 may take on other geometric shapes, or it may be irregular.
  • [0015]
    In FIG. 2, labels 214 and 218 may refer to the same region. That is, p-doped regions 214 and 218 may be slices of the same annulus. However, different numeric labels are used because these numeric labels may represent noncontiguous regions.
  • [0016]
    Adjacent to n-doped region 212 is n-doped region 220 surrounding n-doped region 212, represented by the annulus between dashed circles 304 and 306 in FIG. 3. N-doped region 220 is doped less than n-doped region 212, as indicated by the symbol N- in FIG. 2. Adjacent to n-doped region 220 is n-doped region 222 surrounding n-doped region 220, represented by the annulus between dashed circles 306 and 308 in FIG. 3. N-doped region 222 is doped less than n-doped region 220, as indicated by the symbol N-- in FIG. 2. Adjacent to n-doped region 222 is p-doped region 224, represented by the annulus between dashed circles 308 and 310 in FIG. 3. P-doped region 224 may be part of p-substrate 208, but for ease of discussion is labeled as a distinct region. Regions 220, 222, and 224 may not be exactly circular in shape, and for some embodiments, may take on other geometric shapes, or they may be irregular.
  • [0017]
    n-doped buried layer 210 is represented by the region inside dashed circle 302 in FIG. 3. For the embodiment of FIG. 3, n-doped buried layer 210 is illustrated as having a disk shape, but other embodiments may utilize different shapes for region 210. For ease of illustration, regions 214, 216, and 218 (214 and 218 may label the same region, as discussed previously) are not shown in FIG. 3.
  • [0018]
    Referring to FIG. 2, label 226 denotes a dielectric layer, such as for example SiO2. For ease of illustration, FIG. 2 shows that the dielectric layer on some or all of regions 212, 214, 216, and 218 above n-doped buried layer 210 has been removed, but in practice a dielectric layer may be deposited over these regions.
  • [0019]
    Formed in oxide layer 226 is spiral resistor 228. Spiral resistor 228 may also be referred to as a spiral field plate. In FIG. 2, the cross-sectional view of spiral resistor 228 is indicated by hatched rectangles. Solid spiral line 228 in FIG. 3 represents spiral resistor 228, however, a simplification is made because the number of turns of spiral resistor 228 as shown in FIG. 3 is less than the number of turns represented in FIG. 2. Also, for simplicity all turns in FIG. 3 are shown equal in thickness (in the x-y plane), whereas this is not so for FIG. 2. Furthermore, for clarity of illustration, the scale of the various regions in FIG. 3 does not match that of FIG. 2. The slice in FIG. 3 is taken along spiral resistor 228 in the x-y plane, hence other structures in FIG. 3 are shown dashed because they are present below or above (along the z-axis dimension) the slice.
  • [0020]
    The inner ring of spiral resistor 228 is electrically connected to n-doped region 212. For example, in embodiments represented by the illustrations in FIGS. 2 and 3, the inner ring of spiral resistor 228 is connected to n-doped region 212 by way of highly doped n-region 234, and by a set of vias and an interconnect, collectively labeled by the numeral 230, and shown cross-hatched in the illustration of FIG. 2 and as a dashed rectangle in FIG. 3. Region 234 is a highly doped n-region to provide a good electrical contact between spiral resistor 228 and region 212, so that highly doped n-region 234 and set of vias and interconnect 230 serve as an ohmic contact.
  • [0021]
    The outer ring of spiral resistor 228 is electrically connected to p-doped region 224. For example, in embodiments represented by the illustrations in FIGS. 2 and 3, the outer ring of spiral resistor 228 is connected to p-doped region 224 by way of highly doped p-region 238, and by a set of vias and an interconnect, collectively labeled by the numeral 234, and shown cross-hatched in the illustration of FIG. 2 and as a dashed rectangle in FIG. 3. Region 238 is a highly doped p-region to provide a good electrical contact between spiral resistor 228 and region 224, so that highly doped p-region 238 and set of vias and interconnect 234 serve as an ohmic contact.
  • [0022]
    Spiral resistor 228 may not be exactly a spiral, and for some embodiments spiral resistor 228 may not have a spiral shape. For some embodiments, spiral resistor 228 may meander from above region 212 to above region 222. Some embodiments may have spiral resistor 228 comprising straight sections, so as to enclose a region somewhat rectangular in nature, but with curved corners. Accordingly, in general, the descriptive term “spiral resistor” is not meant to imply that the resistor coupling outer p-doped region 224 to n-doped region 212 is necessarily spiral in shape.
  • [0023]
    For some embodiments, spiral resistor 228 may comprise polysilicon. Well known design techniques may be used so that spiral resistor 228 has some desired resistance. For example, for some embodiments the sheet resistance of the polysilicon used for spiral resistor 228 may be from 1KΩ/square to 5KΩ/square, and a typical resistance for spiral resistor 228 may be in the neighborhood of 60MΩ. For some embodiments, the typical radii of curvature for the bends in spiral resistor 228 may be in the neighborhood of 100 μm to 200 μm. These numerical values are given merely to provide examples. Other embodiments may have numerical values not represented by these numerical ranges or values.
  • [0024]
    Regions 212, 220, and 222 provide a graded doping profile. For simplicity, only three such graduations or steps in doping are shown, but other embodiments may have a different number of such graduations or steps in doping level. As an example of doping levels, region 212 may have a doping level in the range of 1015 cm−3 to 1016 cm−3, where the doping profile is such that region 220 is doped at 1/10 the level of region 212, and region 222 is doped at 1/10 the level of region 220. These numerical values are given merely to provide examples. Other embodiments may have numerical values not represented by these numerical ranges or values.
  • [0025]
    In practice, during operation of the circuit fabricated in the silicon die, the interconnect represented by label 230 may be at a first voltage potential, and the interconnect represented by label 234 may be at a second voltage potential different from the first voltage potential. As a result, in operation the voltage potential of region 212 and n-doped buried layer 210 may be at the first voltage potential, and p-doped region 224 may be at the second voltage potential. The difference in these voltage potentials may be relatively high, for example several hundred volts, as may be the case for consumer power converters. As a particular example, in FIG. 2 the metal interconnect represented by label 230 is shown to be at the supply voltage VIN, and the metal interconnect represented by label 234 is shown to be at ground potential.
  • [0026]
    The voltage potential difference discussed above appears across spiral resistor 228, but if the resistance of spiral resistor 228 is sufficiently high, the resulting current may be set to a relatively low value to reduce wasted power and heat. Spiral resistor 228 sets the voltage potential at the surface of regions 212, 220, and 222, so as to mitigate high electric fields that may cause breakdown. The graded doping profile provided by regions 212, 220, and 222 profiles the depletion region between p-substrate 208 and n-doped regions 212, 220, 222 so that the depletion region has less depth towards p-doped region 224, thereby mitigating punch-through. Accordingly, spiral resistor 228 and the grading of the n-doping in the lateral dimension (x-y plane) help to electrically isolate regions 212, 214, 216, and 218, and n-doped buried layer 210, from parts of the silicon die that are physically placed outside of p-doped region 224. This is important for devices integrated in regions 212, 214, 216, and 218 that may be at or near the high voltage VIN, but where the voltage drops across such devices may be only on the order of ten volts.
  • [0027]
    The floating well may be considered to include the doped silicon inside circular junction 304, including n-doped buried layer 210. In general, the floating well (e.g., regions 210, 212, 214, 216, and 218) may float from a relatively high voltage, such as for example +700V above ground (or the p-substrate) to a much lower positive voltage, ground voltage, or a forward biased diode voltage drop below ground. Devices and circuits within such a floating well may operate at a high voltage with respect to ground, but at a low to medium voltage with respect to the floating well.
  • [0028]
    The particular value of the substrate voltage in a packaged integrated circuit depends upon the application, so for some applications the floating well may be held at 0V and the p-doped substrate voltage may move from 0V to −700V, for example. This may be done throughout the operating voltage range, for example, the floating well may be at −350V and the p-doped substrate at −350V, and so forth. For some embodiments, the volume resistivity of p-doped substrate 208 may be in the neighborhood of 80 ohm-cm, or greater, so that a breakdown voltage of about 700V may be obtained between n-doped buried layer 210 and p-doped substrate 208, whereas spiral resistor 228 and graded regions 212, 220, and 222 provide for a high breakdown voltage in the lateral dimension (x-y plane).
  • [0029]
    All devices within the floating well may be electrically isolated from the substrate, up to some breakdown voltage. P-well regions within the floating well, for example regions 214 and 218, may be electrically isolated from each other by the n-well regions within the floating well. For example, depending upon the device layout and the process technology used, devices within each p-well region may have an operating voltage, with respect to the p-doped substrate, ranging from the breakdown voltage to the breakdown voltage minus 20V to 60V, but because of the isolation, each such device experiences a relatively small voltage drop in the range of 20V to 60V. Examples of active devices using a p-well region inside the floating well may be an nMOSFET, an NPN transistor using the p-well region as a base and the n-doped buried layer as a collector, or a 20-60V pMOSFET using the p-well region as a drain extension. As a specific example, shown in FIG. 2 is an nMOSFET comprising n-doped source and drain regions 312 and 314, and gate 316 (underneath gate 316 is an oxide layer). These are merely a few examples, but in general any type of device and process for p-wells may be a candidate for p-wells within a floating well described by the embodiments.
  • [0030]
    N-well regions inside a floating well, e.g., regions 212 and 216 for the embodiment of FIG. 2, are all at the same voltage potential because they are electrically connected to each other by the n-doped buried layer. Devices fabricated in an n-well within a floating well may have the same operating voltage range as discussed previously with respect to p-wells within the floating well, depending on the device layout and the process. Devices fabricated in an n-well region within a floating well may be a pMOSFET, a lateral PNP device, or other types of devices, where any device that can be fabricated within an n-well may be a candidate for an n-well within a floating well described by the embodiments. As a specific example, shown in FIG. 2 is a pMOSFET comprising p-doped source and drain regions 318 and 320, and gate 322 (underneath gate 322 is an oxide layer).
  • [0031]
    Various modifications may be made to the described embodiments without departing from the scope of the invention as claimed below.
  • [0032]
    It is to be understood in these letters patent that the meaning of “A is connected to B”, where for example A or B may be, but are not limited to, a node, a device terminal, or a port, is that A and B are electrically connected to each other by a conductive structure so that for frequencies within the signal bandwidth of interest, the resistance, capacitance, and inductance introduced by the conductive structure may each be neglected. For example, a transmission line (e.g., microstrip), relatively short compared to the signal wavelength of interest, may be designed to introduce a relatively small impedance, so that two devices in electrical contact at each end of the transmission line may be considered to be connected to one another.
  • [0033]
    It is also to be understood in these letters patent that the meaning of “A is coupled to B” is that either A and B are connected to each other as described above, or that, although A and B may not be connected to each other as described above, there is nevertheless a device or circuit that is connected to both A and B so that a properly defined voltage or current at one of the two elements A or B has some effect on a properly defined voltage or current at the other of the two elements.

Claims (23)

  1. 1. An article of manufacture comprising:
    a semiconductor comprising:
    a substrate;
    an n-doped buried layer adjacent to the substrate;
    an n-doped region adjacent to the n-doped buried layer and the substrate, the n-doped region comprising a first n-doped region adjacent to the n-doped buried layer and having a first doping concentration, and a last n-doped region not adjacent to the n-doped buried layer and having a last doping concentration less than the first doping concentration; and
    a p-doped region adjacent to the last n-doped region and to the substrate; and
    a resistor electrically coupled to the first n-doped region and to the p-doped region.
  2. 2. The article of manufacture as set forth in claim 1, wherein the p-doped region is part of the substrate.
  3. 3. The article of manufacture as set forth in claim 1, further comprising:
    a dielectric layer formed on the n-doped region and the p-doped region, wherein the resistor is formed in the dielectric layer;
    a first ohmic contact to electrically couple the resistor to the first n-doped region; and
    a second ohmic contact to electrically couple the resistor to the p-doped region.
  4. 4. The article of manufacture as set forth in claim 3, wherein
    the first ohmic contact comprises a highly doped n-region in the first n-doped region, a first via in the dielectric layer connected to the highly doped n-region, an interconnect connected to the first via, and a second via in the dielectric layer connected to the interconnect and to the resistor; and
    the second ohmic contact comprises a highly doped p-region in the p-doped region, a first via in the dielectric layer connected to the highly doped p-region, an interconnect connected to the first via of the second ohmic contact, and a second via in the dielectric layer connected to the interconnect of the second ohmic contact and to the resistor.
  5. 5. The article of manufacture as set forth in claim 1, the n-doped region comprising a second n-doped region adjacent to the first n-doped region and the substrate, and having a second doping concentration less than the first doping concentration and greater than the last doping concentration.
  6. 6. The article of manufacture as set forth in claim 1, wherein a portion of the resistor surrounds the first n-doped region.
  7. 7. The article of manufacture as set forth in claim 6, wherein the resistor surrounds the first n-doped region.
  8. 8. The article of manufacture as set forth in claim 6, wherein the resistor has a spiral shape.
  9. 9. The article of manufacture as set forth in claim 1, wherein the last n-doped region surrounds the first n-doped region, and the p-doped region surrounds the last n-doped region.
  10. 10. The article of manufacture as set forth in claim 9, further comprising an isolated p-doped region adjacent to the first n-doped region and the n-doped buried layer, wherein the first n-doped region surrounds the isolated p-doped region.
  11. 11. The article of manufacture as set forth in claim 10, further comprising an active device integrated in the isolated p-doped region.
  12. 12. An article of manufacture comprising:
    a semiconductor comprising:
    a substrate;
    a well in contact with the substrate, the well comprising an n-doped buried layer in contact with the substrate, and an n-doped region in contact with the n-doped buried layer;
    a graded n-doped region having a graded doping concentration in contact with the substrate and the n-doped region of the well;
    a p-doped region in contact with the substrate and the graded n-doped region; and
    a resistor electrically coupled to the n-doped region of the well and to the p-doped region.
  13. 13. The article of manufacture as set forth in claim 12, wherein the graded n-doped region surrounds the well.
  14. 14. The article of manufacture as set forth in claim 13, wherein a portion of the resistor surrounds the well.
  15. 15. The article of manufacture as set forth in claim 14, wherein the resistor surrounds the well.
  16. 16. The article of manufacture as set forth in claim 12, wherein the graded n-doped region has a stepped doping profile.
  17. 17. The article of manufacture as set forth in claim 16, the n-doped region of the well having a doping concentration, wherein
    the graded n-doped region comprises
    a first n-doped region in contact with the n-doped region of the well, and having a first doping concentration less than the doping concentration of the n-doped region of the well; and
    a last n-doped region in contact with the p-doped region, and having a last doping concentration less than the first doping concentration.
  18. 18. The article of manufacture as set forth in claim 12, further comprising:
    a dielectric layer, wherein the resistor is formed in the dielectric layer;
    a first ohmic contact to electrically couple the resistor to the n-doped region of the well; and
    a second ohmic contact to electrically couple the resistor to the p-doped region.
  19. 19. The article of manufacture as set forth in claim 18, wherein
    the first ohmic contact comprises a highly doped n-region in the n-doped region of the well, a first via in the dielectric layer connected to the highly doped n-region, an interconnect connected to the first via, and a second via in the dielectric layer connected to the interconnect and to the resistor; and
    the second ohmic contact comprises a highly doped p-region in the p-doped region, a first via in the dielectric layer connected to the highly doped p-region, an interconnect connected to the first via of the second ohmic contact, and a second via in the dielectric layer connected to the interconnect of the second ohmic contact and to the resistor.
  20. 20. The article of manufacture as set forth in claim 12, the well further comprising a transistor formed in the n-doped region of the well.
  21. 21. The article of manufacture as set forth in claim 12, the well further comprising a p-doped region in contact with the n-doped buried layer, and a transistor formed in the p-doped region of the well.
  22. 22. The article of manufacture as set forth in claim 12, wherein the resistor has a spiral shape.
  23. 23. The article of manufacture as set forth in claim 12, the well further comprising a p-doped region in contact with the n-doped buried layer and surrounded by the n-doped region of the well, and an active device integrated in the p-doped region of the well.
US12562083 2009-09-17 2009-09-17 High voltage floating well in a silicon die Abandoned US20110062554A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US12562083 US20110062554A1 (en) 2009-09-17 2009-09-17 High voltage floating well in a silicon die

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US12562083 US20110062554A1 (en) 2009-09-17 2009-09-17 High voltage floating well in a silicon die
CN 201010263751 CN101937925B (en) 2009-09-17 2010-08-26 Semiconductor device
EP20100176546 EP2309537B1 (en) 2009-09-17 2010-09-14 High voltage floating well in a silicon die

Publications (1)

Publication Number Publication Date
US20110062554A1 true true US20110062554A1 (en) 2011-03-17

Family

ID=42985380

Family Applications (1)

Application Number Title Priority Date Filing Date
US12562083 Abandoned US20110062554A1 (en) 2009-09-17 2009-09-17 High voltage floating well in a silicon die

Country Status (3)

Country Link
US (1) US20110062554A1 (en)
EP (1) EP2309537B1 (en)
CN (1) CN101937925B (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120091529A1 (en) * 2010-10-15 2012-04-19 Taiwan Semiconductor Manufacturing Company, Ltd. High voltage resistor
US20120313692A1 (en) * 2011-06-08 2012-12-13 Sehat Sutardja Super-high-voltage resistor on silicon
US8686503B2 (en) 2011-08-17 2014-04-01 Monolithic Power Systems, Inc. Lateral high-voltage transistor and associated method for manufacturing
US8748980B2 (en) 2011-08-23 2014-06-10 Monolithic Power Systems, Inc. U-shape RESURF MOSFET devices and associated methods of manufacturing
US8759912B2 (en) 2011-08-01 2014-06-24 Monolithic Power Systems, Inc. High-voltage transistor device
US8928043B2 (en) * 2013-04-25 2015-01-06 Monolithic Power Systems, Inc. High voltage FET device with voltage sensing
US9231121B2 (en) 2013-01-17 2016-01-05 Monolithic Power Systems, Inc. High voltage circuit layout structure

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9385187B2 (en) * 2014-04-25 2016-07-05 Texas Instruments Incorporated High breakdown N-type buried layer

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4833509A (en) * 1983-10-31 1989-05-23 Burr-Brown Corporation Integrated circuit reference diode and fabrication method therefor
US5517046A (en) * 1993-11-19 1996-05-14 Micrel, Incorporated High voltage lateral DMOS device with enhanced drift region
US6680515B1 (en) * 2000-11-10 2004-01-20 Monolithic Power Systems, Inc. Lateral high voltage transistor having spiral field plate and graded concentration doping

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4862242A (en) * 1983-12-05 1989-08-29 General Electric Company Semiconductor wafer with an electrically-isolated semiconductor device
US5382826A (en) * 1993-12-21 1995-01-17 Xerox Corporation Stacked high voltage transistor unit
US7306999B2 (en) * 2005-01-25 2007-12-11 Semiconductor Components Industries, L.L.C. High voltage sensor device and method therefor
US20060220168A1 (en) * 2005-03-08 2006-10-05 Monolithic Power Systems, Inc. Shielding high voltage integrated circuits
US7843002B2 (en) * 2007-07-03 2010-11-30 Taiwan Semiconductor Manufacturing Company, Ltd. Fully isolated high-voltage MOS device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4833509A (en) * 1983-10-31 1989-05-23 Burr-Brown Corporation Integrated circuit reference diode and fabrication method therefor
US5517046A (en) * 1993-11-19 1996-05-14 Micrel, Incorporated High voltage lateral DMOS device with enhanced drift region
US6680515B1 (en) * 2000-11-10 2004-01-20 Monolithic Power Systems, Inc. Lateral high voltage transistor having spiral field plate and graded concentration doping

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120091529A1 (en) * 2010-10-15 2012-04-19 Taiwan Semiconductor Manufacturing Company, Ltd. High voltage resistor
KR101247696B1 (en) 2010-10-15 2013-03-26 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 High voltage resistor
US8587073B2 (en) * 2010-10-15 2013-11-19 Taiwan Semiconductor Manufacturing Company, Ltd. High voltage resistor
US20140057407A1 (en) * 2010-10-15 2014-02-27 Taiwan Semiconductor Manufacturing Company, Ltd. High Voltage Resistor
US9224827B2 (en) * 2010-10-15 2015-12-29 Taiwan Semiconductor Manufacturing Company, Ltd. High voltage resistor
US20120313692A1 (en) * 2011-06-08 2012-12-13 Sehat Sutardja Super-high-voltage resistor on silicon
US8759912B2 (en) 2011-08-01 2014-06-24 Monolithic Power Systems, Inc. High-voltage transistor device
US8686503B2 (en) 2011-08-17 2014-04-01 Monolithic Power Systems, Inc. Lateral high-voltage transistor and associated method for manufacturing
US8748980B2 (en) 2011-08-23 2014-06-10 Monolithic Power Systems, Inc. U-shape RESURF MOSFET devices and associated methods of manufacturing
US9231121B2 (en) 2013-01-17 2016-01-05 Monolithic Power Systems, Inc. High voltage circuit layout structure
US8928043B2 (en) * 2013-04-25 2015-01-06 Monolithic Power Systems, Inc. High voltage FET device with voltage sensing

Also Published As

Publication number Publication date Type
EP2309537A3 (en) 2011-08-03 application
EP2309537A2 (en) 2011-04-13 application
EP2309537B1 (en) 2016-06-08 grant
CN101937925A (en) 2011-01-05 application
CN101937925B (en) 2013-05-08 grant

Similar Documents

Publication Publication Date Title
US6909149B2 (en) Low voltage silicon controlled rectifier (SCR) for electrostatic discharge (ESD) protection of silicon-on-insulator technologies
US20140131711A1 (en) Structures and techniques for using semiconductor body to construct bipolar junction transistors
US20140133056A1 (en) Structures and techniques for using mesh-structure diodes for electro-static discharge (esd) protection
US20080044955A1 (en) Electrostatic discharge protection device for digital circuits and for applications with input/output bipolar voltage much higher than the core circuit power supply
US6236087B1 (en) SCR cell for electrical overstress protection of electronic circuits
US20020008299A1 (en) Integrated device with a trench isolation structure, and fabrication process therefor
US20050151160A1 (en) On-chip structure for electrostatic discharge (ESD) protection
US20120008242A1 (en) Apparatus and method for electronic circuit protection
US20120007207A1 (en) Apparatus and method for electronic circuit protection
US20070004160A1 (en) Tunable semiconductor diodes
US20050212051A1 (en) Low voltage silicon controlled rectifier (SCR) for electrostatic discharge (ESD) protection of silicon-on-insulator technologies
US20090045457A1 (en) Optimized configurations to integrate steering diodes in low capacitance transient voltage suppressor (TVS)
US20090115018A1 (en) Transient voltage suppressor manufactured in silicon on oxide (SOI) layer
US20100171149A1 (en) Symmetrical bi-directional semiconductor esd protection device
US8044457B2 (en) Transient over-voltage clamp
US6320232B1 (en) Integrated semiconductor circuit with protective structure for protection against electrostatic discharge
US20080203534A1 (en) Complementary zener triggered bipolar esd protection
US20130032882A1 (en) Bi-directional blocking voltage protection devices and methods of forming the same
US20070145411A1 (en) Trench polysilicon diode
US20070241421A1 (en) Semiconductor structure and method of manufacture
US20140138735A1 (en) Junction-isolated blocking voltage devices with integrated protection structures and methods of forming the same
US20030042498A1 (en) Method of forming a substrate-triggered SCR device in CMOS technology
US20040026728A1 (en) Semiconductor device and combined IC using the same
US20100327343A1 (en) Bond pad with integrated transient over-voltage protection
US20120199874A1 (en) Apparatus and method for transient electrical overstress protection

Legal Events

Date Code Title Description
AS Assignment

Owner name: MONOLITHIC POWER SYSTEMS, INC., CALIFORNIA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:HSING, MICHAEL R.;MOYER, JAMES C.;SIGNING DATES FROM 20091008 TO 20091013;REEL/FRAME:023641/0415