CN106233439B - 高击穿n型埋层 - Google Patents

高击穿n型埋层 Download PDF

Info

Publication number
CN106233439B
CN106233439B CN201580020171.3A CN201580020171A CN106233439B CN 106233439 B CN106233439 B CN 106233439B CN 201580020171 A CN201580020171 A CN 201580020171A CN 106233439 B CN106233439 B CN 106233439B
Authority
CN
China
Prior art keywords
layer
type
dopant
semiconductor device
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201580020171.3A
Other languages
English (en)
Chinese (zh)
Other versions
CN106233439A (zh
Inventor
S·P·彭哈卡
B·胡
H·L·爱德华兹
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Publication of CN106233439A publication Critical patent/CN106233439A/zh
Application granted granted Critical
Publication of CN106233439B publication Critical patent/CN106233439B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
    • H10D62/107Buried supplementary regions, e.g. buried guard rings 
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251Diffusion into or out of group IV semiconductors
    • H01L21/2252Diffusion into or out of group IV semiconductors using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase
    • H01L21/2253Diffusion into or out of group IV semiconductors using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase by ion implantation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/265Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/265Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H01L21/2652Through-implantation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/265Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/266Bombardment with radiation with high-energy radiation producing ion implantation using masks
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/113Isolations within a component, i.e. internal isolations
    • H10D62/114PN junction isolations
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/834Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge further characterised by the dopants
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/60Electrodes characterised by their materials
    • H10D64/62Electrodes ohmically coupled to a semiconductor

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Element Separation (AREA)
  • Bipolar Transistors (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
CN201580020171.3A 2014-04-25 2015-04-27 高击穿n型埋层 Active CN106233439B (zh)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201461984205P 2014-04-25 2014-04-25
US61/984,205 2014-04-25
US14/555,330 US9385187B2 (en) 2014-04-25 2014-11-26 High breakdown N-type buried layer
US14/555,330 2014-11-26
PCT/US2015/027699 WO2015164853A1 (en) 2014-04-25 2015-04-27 High breakdown n-type buried layer

Publications (2)

Publication Number Publication Date
CN106233439A CN106233439A (zh) 2016-12-14
CN106233439B true CN106233439B (zh) 2021-01-01

Family

ID=54333345

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201580020171.3A Active CN106233439B (zh) 2014-04-25 2015-04-27 高击穿n型埋层

Country Status (4)

Country Link
US (2) US9385187B2 (enExample)
JP (1) JP6657183B2 (enExample)
CN (1) CN106233439B (enExample)
WO (1) WO2015164853A1 (enExample)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9385187B2 (en) * 2014-04-25 2016-07-05 Texas Instruments Incorporated High breakdown N-type buried layer
DE102017103782B4 (de) * 2017-02-23 2021-03-25 Infineon Technologies Ag Halbleitervorrichtung mit einer vergrabenen Schicht und Herstellungsverfahren hierfür
FR3089679A1 (fr) 2018-12-11 2020-06-12 Stmicroelectronics (Tours) Sas Dispositif de commutation et procédé de fabrication d'un tel dispositif
CN114695505B (zh) * 2020-12-29 2025-01-24 无锡华润上华科技有限公司 电子设备、半导体器件及其制备方法
CN118041270A (zh) * 2022-11-04 2024-05-14 广州乐仪投资有限公司 半导体结构的制备方法、半导体结构及电子设备

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5192708A (en) * 1991-04-29 1993-03-09 International Business Machines Corporation Sub-layer contact technique using in situ doped amorphous silicon and solid phase recrystallization
JPH08236614A (ja) * 1995-02-27 1996-09-13 Nippondenso Co Ltd 半導体装置の製造方法
CN1581506A (zh) * 2003-08-08 2005-02-16 三菱电机株式会社 纵型半导体器件及其制造方法

Family Cites Families (42)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4666556A (en) 1986-05-12 1987-05-19 International Business Machines Corporation Trench sidewall isolation by polysilicon oxidation
US4980747A (en) 1986-12-22 1990-12-25 Texas Instruments Inc. Deep trench isolation with surface contact to substrate
JPH0271526A (ja) * 1988-07-07 1990-03-12 Matsushita Electric Ind Co Ltd 半導体集積回路およびその製造方法
JPH0442959A (ja) * 1990-06-06 1992-02-13 Fujitsu Ltd 半導体集積回路装置
GB2248142A (en) * 1990-09-19 1992-03-25 Koninkl Philips Electronics Nv A method of manufacturing a semiconductor device
JPH0536823A (ja) * 1991-08-01 1993-02-12 Mitsubishi Electric Corp 半導体集積回路
US5994755A (en) * 1991-10-30 1999-11-30 Intersil Corporation Analog-to-digital converter and method of fabrication
JPH0799771B2 (ja) 1992-06-26 1995-10-25 インターナショナル・ビジネス・マシーンズ・コーポレイション 皮膜中の応力を制御する方法
JP3285435B2 (ja) * 1993-07-07 2002-05-27 三菱電機株式会社 半導体装置およびその製造方法
JP3334027B2 (ja) * 1996-02-06 2002-10-15 富士電機株式会社 高耐圧横型半導体装置
US6218722B1 (en) 1997-02-14 2001-04-17 Gennum Corporation Antifuse based on silicided polysilicon bipolar transistor
JPH11251447A (ja) * 1998-02-27 1999-09-17 Nippon Foundry Inc 半導体装置及びその製造方法
US20010013610A1 (en) * 1999-08-02 2001-08-16 Min-Hwa Chi Vertical bipolar transistor based on gate induced drain leakage current
US6661042B2 (en) * 2002-03-11 2003-12-09 Monolithic System Technology, Inc. One-transistor floating-body DRAM cell in bulk CMOS process with electrically isolated charge storage region
US6943426B2 (en) 2002-08-14 2005-09-13 Advanced Analogic Technologies, Inc. Complementary analog bipolar transistors with trench-constrained isolation diffusion
US7041572B2 (en) 2002-10-25 2006-05-09 Vanguard International Semiconductor Corporation Fabrication method for a deep trench isolation structure of a high-voltage device
US7635621B2 (en) * 2002-11-22 2009-12-22 Micrel, Inc. Lateral double-diffused metal oxide semiconductor (LDMOS) device with an enhanced drift region that has an improved Ron area product
SE526366C3 (sv) * 2003-03-21 2005-10-26 Silex Microsystems Ab Elektriska anslutningar i substrat
US6815780B1 (en) 2003-04-15 2004-11-09 Motorola, Inc. Semiconductor component with substrate injection protection structure
US7639713B2 (en) 2004-01-21 2009-12-29 Emc Corporation Database block network attached storage packet joining
JP4592340B2 (ja) 2004-06-29 2010-12-01 三洋電機株式会社 半導体装置の製造方法
KR100797896B1 (ko) * 2004-11-12 2008-01-24 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 다양한 동작 전압들을 갖는 집적 회로들을 절연시키기 위한반도체 구조
US7772100B2 (en) * 2005-03-24 2010-08-10 Nxp B.V. Method of manufacturing a semiconductor device having a buried doped region
CN1897282A (zh) * 2005-06-30 2007-01-17 St微电子克鲁勒斯图股份公司 包括具有隔离体的一个mos晶体管的存储单元
US7723204B2 (en) 2006-03-27 2010-05-25 Freescale Semiconductor, Inc. Semiconductor device with a multi-plate isolation structure
US7410862B2 (en) 2006-04-28 2008-08-12 International Business Machines Corporation Trench capacitor and method for fabricating the same
US8420483B2 (en) * 2007-01-09 2013-04-16 Maxpower Semiconductor, Inc. Method of manufacture for a semiconductor device
US8614151B2 (en) 2008-01-04 2013-12-24 Micron Technology, Inc. Method of etching a high aspect ratio contact
US7989875B2 (en) * 2008-11-24 2011-08-02 Nxp B.V. BiCMOS integration of multiple-times-programmable non-volatile memories
KR101610826B1 (ko) 2009-03-18 2016-04-11 삼성전자주식회사 커패시터를 갖는 반도체 장치의 형성방법
US8476530B2 (en) 2009-06-22 2013-07-02 International Business Machines Corporation Self-aligned nano-scale device with parallel plate electrodes
US20110062554A1 (en) 2009-09-17 2011-03-17 Hsing Michael R High voltage floating well in a silicon die
US8334190B2 (en) 2010-05-07 2012-12-18 Texas Instruments Incorporated Single step CMP for polishing three or more layer film stacks
US8399924B2 (en) 2010-06-17 2013-03-19 Texas Instruments Incorporated High voltage transistor using diluted drain
JP5743831B2 (ja) * 2011-09-29 2015-07-01 株式会社東芝 半導体装置
US8785971B2 (en) * 2011-11-23 2014-07-22 Amazing Microelectronic Corp. Transient voltage suppressor without leakage current
US8642423B2 (en) * 2011-11-30 2014-02-04 International Business Machines Corporation Polysilicon/metal contact resistance in deep trench
US9356133B2 (en) * 2012-02-01 2016-05-31 Texas Instruments Incorporated Medium voltage MOSFET device
US9293357B2 (en) 2012-07-02 2016-03-22 Texas Instruments Incorporated Sinker with a reduced width
US9082719B2 (en) 2012-10-19 2015-07-14 Infineon Technologies Ag Method for removing a dielectric layer from a bottom of a trench
US9136368B2 (en) * 2013-10-03 2015-09-15 Texas Instruments Incorporated Trench gate trench field plate semi-vertical semi-lateral MOSFET
US9385187B2 (en) * 2014-04-25 2016-07-05 Texas Instruments Incorporated High breakdown N-type buried layer

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5192708A (en) * 1991-04-29 1993-03-09 International Business Machines Corporation Sub-layer contact technique using in situ doped amorphous silicon and solid phase recrystallization
JPH08236614A (ja) * 1995-02-27 1996-09-13 Nippondenso Co Ltd 半導体装置の製造方法
CN1581506A (zh) * 2003-08-08 2005-02-16 三菱电机株式会社 纵型半导体器件及其制造方法

Also Published As

Publication number Publication date
US9673273B2 (en) 2017-06-06
US20160315141A1 (en) 2016-10-27
US20150311281A1 (en) 2015-10-29
JP6657183B2 (ja) 2020-03-04
US9385187B2 (en) 2016-07-05
WO2015164853A1 (en) 2015-10-29
JP2017514319A (ja) 2017-06-01
CN106233439A (zh) 2016-12-14

Similar Documents

Publication Publication Date Title
JP7189403B2 (ja) ディープトレンチ充填のためのポリサンドイッチ
US7691734B2 (en) Deep trench based far subcollector reachthrough
US7915155B2 (en) Double trench for isolation of semiconductor devices
US8222114B2 (en) Manufacturing approach for collector and a buried layer of bipolar transistor
US9099321B2 (en) Method for fabricating power semiconductor device
CN106233439B (zh) 高击穿n型埋层
CN105633042B (zh) 超高纵横比接触件
CN113257921B (zh) 半导体结构
CN102386124A (zh) 直接接触的沟槽结构
CN108604606B (zh) 低动态电阻低电容二极管
CN101165921A (zh) 半导体结构
US9431286B1 (en) Deep trench with self-aligned sinker
KR20180104236A (ko) 전력 반도체 소자의 제조 방법
CN101151732A (zh) 包括功率二极管的集成电路
EP3176816A1 (en) Well implantation process for finfet device
CN115642180A (zh) 具有深耗尽沟道的半导体装置及其制造方法
JP5743246B2 (ja) 半導体装置及び関連する製造方法
JP7462732B2 (ja) 横方向拡散金属酸化物半導体デバイス及びその製造方法
US6806159B2 (en) Method for manufacturing a semiconductor device with sinker contact region
CN119856586A (zh) 埋藏式沟槽电容器
US20050037588A1 (en) Method for manufacturing and structure of semiconductor device with sinker contact region
KR101928253B1 (ko) 전력 반도체 소자의 제조 방법
CN119815929A (zh) 具有低电容的静电放电保护装置
KR960026931A (ko) 반도체장치 및 그 제조방법

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant