CN106233439A - 高击穿n型埋层 - Google Patents

高击穿n型埋层 Download PDF

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CN106233439A
CN106233439A CN201580020171.3A CN201580020171A CN106233439A CN 106233439 A CN106233439 A CN 106233439A CN 201580020171 A CN201580020171 A CN 201580020171A CN 106233439 A CN106233439 A CN 106233439A
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buried regions
epitaxial layer
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semiconductor device
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CN106233439B (zh
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S·P·彭哈卡
B·胡
H·L·爱德华兹
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Texas Instruments Inc
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Abstract

在所述示例中，半导体器件(100)具有通过以高剂量和低能量将锑和/或砷注入到p型第一外延层(104)中，并且以低剂量和高能量注入磷形成的n型埋层(108)。热驱动过程扩散和激活重掺杂剂和磷二者。锑和砷不显著扩散，保持用于埋层(108)的主层(114)的窄分布。磷扩散以提供在主层(114)下方的几微米厚的轻掺杂层(120)。外延p型层(106)在埋层(108)上方生长。

Description

高击穿n型埋层
技术领域
本发明一般涉及半导体器件，并且更具体地涉及在半导体器件中的埋层。
背景技术
示例半导体器件包含在p型衬底中的n型埋层。埋层偏置为80伏特以上的高电压，以为埋层上方的衬底中的部件提供高电压下的隔离操作。在埋层的底表面处，pn结显示出不期望的漏电流和低击穿。
发明内容
在所述示例中，半导体器件具有在p型第一外延层上方和p型第二外延层下方的n型埋层。埋层是通过以高剂量和低能量将重n型掺杂剂(锑和/或砷)注入到p型第一外延层中，并且以低剂量和高能量注入更轻的n型掺杂剂磷来形成的。热驱动过程扩散并激活重掺杂剂和磷二者。重掺杂剂不显著扩散，有利地保持用于埋层的主层的窄分布(narrowprofile)。磷扩散以有利地提供在主层下方的几微米厚的轻掺杂层。
附图说明
图1是一种包含高电压n型埋层的示例半导体器件的横截面。
图2A至2F是以制造的连续阶段示出的一种半导体器件的横截面，类似于图1的半导体器件。
图3A至3F是以制造的连续阶段描绘的包含高电压局部n型埋层的另一个示例半导体器件的横截面。
图4是包含高电压n型埋层的一种替代示例半导体器件的横截面。
具体实施方式
下面的共同未决专利申请通过引用被合并于此：申请号US 14/555,209；申请号US14/555,300；以及申请号US 14/555,359。
图1是一种包含高电压n型埋层的示例半导体器件的横截面。半导体器件100具有衬底102，其包括诸如单晶硅的半导体材料的第一外延层104。衬底102还包括在第一外延层104上布置的第二外延层106。第二外延层106包括可以具有与第一外延层104相同的组合物的半导体材料。n型埋层108布置在衬底102中的第一外延层104和第二外延层106之间的边界处，延伸到第一外延层104和第二外延层106。紧接n型埋层108下方的第一外延层104被称为下层110。下层110是p型，并且具有5欧姆厘米(ohm-cm)至10ohm-cm的电阻率。在n型埋层108上方的第二外延层106被称为上层112。上层112是p型，并且具有5ohm-cm至10ohm-cm的电阻率。
n型埋层108包括主层114，其跨越第一外延层104和第二外延层106之间的边界，延伸到第一外延层104中至少一微米，并且延伸到第二外延层106中至少一微米。主层114具有大于5×1018cm-3的平均掺杂密度。在主层114中至少50百分比的n型掺杂剂是砷和/或锑。主层114的顶表面116在衬底102的顶表面118下方至少5微米。主层114的顶表面116可以在衬底102的顶表面118下方8微米到12微米。
n型埋层108包括在主层114下方延伸至少2微米的轻掺杂层120。轻掺杂层120布置在下层110上方的第一外延层104中。轻掺杂层120具有1×1016cm-3至1×1017cm-3的平均掺杂密度。在轻掺杂层120中至少90百分比的n型掺杂剂是磷。n型埋层108可以如图1所示基本上横跨半导体器件100延伸。
在半导体器件100的操作期间，n型埋层108可以偏置到高于下层110的80伏特至110伏特。具有轻掺杂层120的n型埋层108的结构可有利地防止在n型埋层108和下层110之间的pn结的击穿，并且可有利地提供期望的低水平的漏电流。此外，具有主层114的n型埋层108的结构有利地提供低薄层电阻以对在n型埋层108上方的上层112中的部件保持均匀偏压。
半导体器件100可以包括深沟槽结构122，其延伸通过上层112，通过n型埋层108，并进入下层110。深沟槽结构122包括介电内衬(liner)124，包括接触衬底102的半导体材料的二氧化硅。深沟槽结构122还可以包括导电的填充材料126，诸如在介电内衬124上的多晶的硅(被称为多晶硅)。具有轻掺杂层120的n型埋层108的结构特别有利地防止在介电内衬124处n型埋层108和下层110之间的pn结的击穿。深沟槽结构122可具有如在图1中描绘的闭环配置，以使得上层112的一部分128通过深沟槽结构122与剩余上层112电隔离，并且通过n型埋层108与下层110电隔离。上层112的部分128中的部件可相对于在深沟槽结构122外侧的剩余上层112中的部件以85伏特至110伏特而有利地操作。
图2A至2F是以制造的连续阶段示出的一种半导体器件的横截面，类似于图1的半导体器件。参照图2A，半导体器件100的制造以第一外延层104开始。例如，第一外延层104可以是在重掺杂单晶硅晶片上外延层堆叠的顶部部分。第一外延层104是具有5ohm-cm至10ohm-cm的电阻率的p型。衬垫氧化物层130诸如通过热氧化形成在第一外延层104上方。
N型掺杂剂132被注入到第一外延层104中，以形成第一注入层134。n型掺杂剂包括至少50百分比的砷和/或锑。在本示例的一个版本中，n型掺杂剂132可以基本上全部是锑，如图2A所示。n型掺杂剂132以大于5×1014cm-2(诸如1×1015cm-2至5×1015cm-2)的剂量被注入。n型掺杂剂132中的锑可以在小于50keV的能量下被注入。n型掺杂剂132中的砷可以在小于40keV的能量下被注入。
参照图2B，磷136注入到第一外延层104中以在第一注入层134下方形成第二注入层138。磷136以1×1013cm-2至1×1014cm-2的剂量并且以高于100keV的能量注入。
参照图2C，第一热驱动过程140加热第一外延层104至1150℃到1225℃的温度至少30分钟。第一热驱动过程140可在具有氧化环境的炉中执行，这增加了衬垫氧化物层130的厚度。第一热驱动过程140导致在第一注入层134中注入的n型掺杂剂和第二注入层138中注入的磷更深地扩散进入第一外延层104中。在第二注入层138中的磷比在第一注入层134中的砷和锑更远地扩散到第一外延层104中。随后，衬垫氧化物层130诸如通过使用缓冲的氢氟酸的稀释水溶液的湿刻蚀来去除。
参照图2D，外延过程在第一外延层104上生长第二外延层106。外延过程可使用硅烷、二氯硅烷，或其它含硅试剂。在外延过程期间，在图2C的第一注入层134中的n型掺杂剂扩散进入第二外延层106中，以形成n型埋层108的主层114。主层114跨越在第一外延层104和第二外延层106之间的边界。图2C的第二注入层138中的磷形成n型埋层108的轻掺杂层120。外延过程可使用含硼试剂(诸如二硼烷)，以提供在第二外延层106中的p型掺杂。可替代地，在完成外延过程之后，p型掺杂剂(诸如硼)可以注入到第二外延层106中。第一外延层104和第二外延层106提供衬底102的顶部部分。
参照图2E，第二热驱动过程142加热衬底102至1125℃到1200℃的温度至少120分钟。第二热驱动过程142可在具有轻微氧化环境的炉中执行。当完成第二热驱动时，n型埋层108的主层114延伸到第一外延层104中至少一微米，并且延伸到第二外延层106中至少一微米，并且轻掺杂层120延伸到主层114下方至少2微米。在主层114中的平均掺杂大于5×1018cm-3。在轻掺杂层120中的平均掺杂为1×1016cm-3至1×1017cm-3。
参照图2F，深沟槽结构122可在图2E的第二热驱动过程142之后通过在衬底102中蚀刻的深沟槽来形成。介电内衬124可以通过热氧化、接着通过由次常压化学气相淀积(SACVD)过程沉积二氧化硅形成。导电填充材料126可通过沉积多晶硅共形层并随后从衬底的顶表面上方去除多晶硅形成，诸如通过化学机械抛光(CMP)过程。通过在深沟槽被部分蚀刻之后将n型掺杂剂注入到第二外延层106中，可选的n型自对准散热片(sinker)144可以形成在邻接深沟槽结构的第二外延层106中。n型自对准散热片144提供电连接到n型埋层108。
图3A至3F是以制造的连续阶段描绘的包含高电压局部n型埋层的另一个示例半导体器件的横截面。局部n型埋层延伸横跨半导体器件的仅一部分。参照图3A，半导体器件300形成在包含半导体材料(诸如单晶硅)的第一外延层304上。第一外延层304是具有5ohm-cm至10ohm-cm的电阻率的p型。衬垫氧化物层330形成在第一外延层304上方。在该示例中，注入掩模346形成在衬垫氧化物层330上方，以曝露用于局部n型埋层308的区域。注入掩模346可以包括通过光刻过程形成的光致抗蚀剂，或者可包括硬掩模材料，诸如通过热氧化或等离子体增强化学气相(PECVD)过程形成的二氧化硅。在注入掩模346中的硬掩模材料可在以高能量注入磷之后有利地促进注入掩模346的随后去除。
N型掺杂剂332通过由注入掩模346曝露的区域被注入到第一外延层304中，以形成第一注入层334。n型掺杂剂包括至少50百分比的砷和/或锑。n型掺杂剂332以大于5×1014cm-2(诸如1×1015cm-2至5×1015cm-2)的剂量注入。
参照图3B，磷336通过由注入掩模346曝露的区域被注入到第一外延层304中，以形成在第一注入层334下方的第二注入层338。磷336以1×1013cm-2至1×1014cm-2的剂量并且以高于100keV的能量被注入。注入掩模346中的有机材料(诸如光致抗蚀剂)在随后的第一热驱动过程之前被去除。
参照图3C，第一热驱动过程340加热第一外延层304至1150℃到1225℃的温度至少30分钟，诸如参考图2所述。第一热驱动过程340导致在第一注入层334中注入的n型掺杂剂和在第二注入层338中注入的磷更深地扩散到第一外延层304中。在第二注入层338中的磷比第一注入层334中的砷和锑更远地扩散到第一外延层304中。注入掩模346(如果有的话)和衬垫氧化物层330随后被去除。
参照图3D，外延过程在第一外延层304上生长第二外延层306，以提供半导体器件300的衬底302。在外延过程期间，在图3C的第一注入层334中的n型掺杂剂扩散进入第二外延层306，以形成局部n型埋层308的主层314。主层314跨越在第一外延层304和第二外延层306之间的边界。在图3C的第二注入层338中的磷在主层314下方形成局部n型埋层308的轻掺杂层320。第二外延层306是具有5ohm-cm至10ohm-cm的电阻率的p型。紧接在n型埋层308下方的第一外延层304被称为下层310。类似地，在n型埋层308上方的第二外延层306被称为上层312。
参照图3E，第二热驱动过程342加热衬底302至1125℃到1200℃的温度至少120分钟。当第二热驱动完成时，局部n型埋层308的主层314延伸到第一外延层304中至少一微米，并且延伸到第二外延层306中至少一微米，并且轻掺杂层320在主层314下方延伸至少2微米。主层314的顶表面316是在衬底302的顶表面318下方至少5微米。主层314的顶表面316可以是在衬底302的顶表面318下方8微米至12微米。在主层314中的平均掺杂大于5×1018cm-3。在主层314中的至少50百分比的n型掺杂剂是砷和/或锑。
轻掺杂层320在主层314下方延伸至少2微米。在轻掺杂层320中的平均掺杂是1×1016cm-3至1×1017cm-3。在轻掺杂层320中的至少90百分比的n型掺杂剂是磷。
参照图3F，n型散热片348形成在第二外延层306中，向下延伸至局部n型埋层308。n型散热片348可具有闭环配置以将上层312的部分328与剩余的上层312隔离。局部n型埋层308将上层312的部分328与下层310隔离。具有主层314和轻掺杂层320的局部n型埋层308的结构可有利地提供在局部n型埋层308中的低薄层电阻，同时减少漏电流并且防止在局部n型埋层308和下层310之间的pn结的击穿。
图4是包含高电压n型埋层的一种替代示例半导体器件的横截面。半导体器件400具有衬底402，其包括p型半导体材料(诸如单晶硅)的第一外延层404。衬底402还包括布置在第一外延层404上的第二外延层406。第二外延层406包括p型半导体材料，其可以具有与第一外延层404相同的组合物。n型埋层408布置在衬底402中的第一外延层404和第二外延层406之间边界处，延伸到第一外延层404和第二外延层406中。紧接n型埋层408下方的第一外延层404被称为下层410。下层410是p型，并且具有5ohm-cm至10ohm-cm的电阻率。n型埋层408上方的第二外延层406被称为上层412。上层412是p型，并且具有5ohm-cm至10ohm-cm的电阻率。
n型埋层408包括主层414，其跨越第一外延层404和第二外延层406之间的边界，延伸到第一外延层404中至少一微米，并且延伸到第二外延层406中至少一微米。主层414具有大于5×1018cm-3的平均掺杂密度。主层414的顶面416是在衬底402的顶表面418下方至少5微米。主层414的顶表面416可以是在衬底402的顶表面418下方8微米至12微米。n型埋层408包括在主层414下方延伸至少2微米的轻掺杂层420。轻掺杂层420布置在下层410上方的第一外延层404中。轻掺杂层420具有1×1016cm-3至1×1017cm-3的平均掺杂密度。n型埋层408可以如在此的任何示例中所述的来形成。
一个或更多个深沟槽结构422布置在衬底402中，在埋层408下方延伸到下层410中。深沟槽结构422包括接触衬底402的介电内衬424。深沟槽结构422包括在介电内衬424上的导电沟槽填充材料426。在该示例中，介电内衬424在深沟槽结构422的底部450处被去除，并且沟槽填充材料426延伸到衬底402，通过p型接触区域452与衬底402进行电连接。接触区域452和去除在每个深沟槽结构422的底部450处的介电内衬424的方法可如在申请号US14/555,359中所描述的进行，其通过引用被合并于此。
在该示例中，沟槽填充材料426包括布置在介电内衬424上的多晶硅的第一层454，延伸到深沟槽结构422的底部450。多晶硅的第二层456布置在多晶硅的第一层454上。掺杂剂以至少1×1018cm-3的平均掺杂密度分布在多晶硅的第一层454和多晶硅的第二层456中。沟槽填充材料426可如在申请号US 14/555,300中所描述的形成，其通过引用被合并于此。
N型自对准散热片444布置在邻接深沟槽结构422并且延伸到埋层408的上层412中。自对准散热片444提供到埋层408的电连接。自对准散热片444可如在申请号US 14/555,209中所描述的形成，其通过引用被合并于此。
附图不是按比例绘制的。
在权利要求的范围之内，在所描述的实施例中修改是可能的，并且其它实施例是可能的。

Claims (19)

1.一种半导体器件，包括：
衬底，其包括p型半导体材料；以及
n型埋层，其布置在所述衬底中；
所述n型埋层包括：具有大于5×1018cm-3平均掺杂密度的2微米至10微米厚的主层，其中在所述主层中的至少50百分比的n型掺杂剂选自由锑和砷组成的组，以及其中所述主层的顶表面在所述衬底的顶表面下方至少5微米；以及轻掺杂层在所述主层下方延伸至少2微米，所述轻掺杂层具有1×1016cm-3至1×1017cm-3的平均掺杂密度，其中在轻掺杂层中的至少90百分比的n型掺杂剂是磷。
2.根据权利要求1所述的半导体器件，其中所述p型半导体材料具有5ohm-cm至10ohm-cm的电阻率。
3.根据权利要求1所述的半导体，其中在所述主层中的至少50百分比的n型掺杂剂是锑。
4.根据权利要求1所述的半导体器件，其中所述n型埋层基本上横跨所述半导体器件延伸。
5.根据权利要求1所述的半导体器件，其中所述n型埋层是横跨所述半导体器件的仅一部分而延伸的局部n型埋层。
6.根据权利要求1所述的半导体器件，包括延伸通过所述n型埋层的布置在所述衬底中的深沟槽结构，所述深沟槽结构包括具有接触所述衬底的二氧化硅的介电内衬。
7.根据权利要求6所述的半导体器件，其中所述深沟槽结构具有闭环配置。
8.根据权利要求6所述的半导体器件，包括在所述衬底中布置的邻接所述深沟槽结构并且向下延伸到所述n型埋层的n型自对准散热片。
9.根据权利要求1所述的半导体器件，包括在所述衬底中布置的延伸到所述n型埋层的n型散热片，所述n型散热片具有闭环配置。
10.一种形成半导体器件的方法，包括：
提供包括p型半导体材料的衬底的第一外延层；
以大于5×1014cm-2的剂量将n型掺杂剂注入到所述第一外延层中，所述n型掺杂剂选自由砷和磷组成的组；
以1×1013cm-2至1×1014cm-2的剂量并且以高于100keV的能量将磷注入到所述第一外延层中；
在加热所述第一外延层至1150℃到1225℃的温度至少30分钟的第一热驱动过程中加热所述第一外延层；以及
在所述第一外延层上形成所述衬底的p型外延层；
其中注入的n型掺杂剂形成n型埋层的主层，所述主层为2微米至10微米厚，其中在所述主层中的至少50百分比的n型掺杂剂选自由锑和砷组成的组，以及其中所述主层的顶表面在所述衬底的顶表面下方至少5微米，以及注入的磷形成所述n型埋层的轻掺杂层，所述轻掺杂层在所述主层下方延伸至少2微米，其中所述轻掺杂层具有1×1016cm-3至1×1017cm-3的平均掺杂密度，以及在所述轻掺杂层中的至少90百分比的n型掺杂剂是磷。
11.根据权利要求10所述的方法，其中在所述第一外延层中的所述p型半导体材料具有5ohm-cm至10ohm-cm的电阻率。
12.根据权利要求10所述的方法，其中以大于5×1014cm-2的剂量注入到所述第一外延层中的n型掺杂剂是锑。
13.根据权利要求10所述的方法，其中所述n型掺杂剂和所述磷被注入到横跨所述半导体器件的所述第一外延层中。
14.根据权利要求10所述的方法，其中所述n型掺杂剂和所述磷通过由注入掩模曝露的区域被注入到所述第一外延层中，以使得所述n型埋层是局部n型埋层。
15.根据权利要求10所述的方法，包括在形成所述外延层之后，在将所述衬底加热至1125℃到1200℃的温度至少120分钟的第二热驱动过程中加热所述衬底。
16.根据权利要求10所述的方法，包括在所述衬底中形成延伸通过所述n型埋层的深沟槽，以及在所述深沟槽中形成具有接触所述衬底的二氧化硅的介电内衬。
17.根据权利要求16所述的方法，其中所述深沟槽具有闭环配置。
18.根据权利要求16所述的方法，包括在所述深沟槽形成之后将n型掺杂剂注入到与所述深沟槽相邻的所述衬底中，以在所述衬底中形成向下延伸到所述n型埋层的n型自对准散热片。
19.根据权利要求10所述的方法，包括在所述衬底中形成延伸到所述n型埋层的n型散热片，所述n型散热片具有闭环配置。
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US9385187B2 (en) * 2014-04-25 2016-07-05 Texas Instruments Incorporated High breakdown N-type buried layer
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Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5192708A (en) * 1991-04-29 1993-03-09 International Business Machines Corporation Sub-layer contact technique using in situ doped amorphous silicon and solid phase recrystallization
JPH08236614A (ja) * 1995-02-27 1996-09-13 Nippondenso Co Ltd 半導体装置の製造方法
US5624858A (en) * 1993-07-07 1997-04-29 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing a semiconductor device with increased breakdown voltage
US20010013610A1 (en) * 1999-08-02 2001-08-16 Min-Hwa Chi Vertical bipolar transistor based on gate induced drain leakage current
US20030168677A1 (en) * 2002-03-11 2003-09-11 Fu-Chieh Hsu One-transistor floating-body DRAM cell in bulk CMOS process with electrically isolated charge storage region
CN1581506A (zh) * 2003-08-08 2005-02-16 三菱电机株式会社 纵型半导体器件及其制造方法
CN101641763A (zh) * 2007-01-09 2010-02-03 威力半导体有限公司 半导体器件及其制造方法
US20100127318A1 (en) * 2008-11-24 2010-05-27 Nxp B.V. Bicmos integration of multiple-times-programmable non-volatile memories
US20130127007A1 (en) * 2011-11-23 2013-05-23 Che-Hao Chuang Transient voltage suppressor without leakage current

Family Cites Families (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4666556A (en) 1986-05-12 1987-05-19 International Business Machines Corporation Trench sidewall isolation by polysilicon oxidation
US4980747A (en) 1986-12-22 1990-12-25 Texas Instruments Inc. Deep trench isolation with surface contact to substrate
US5994755A (en) * 1991-10-30 1999-11-30 Intersil Corporation Analog-to-digital converter and method of fabrication
JPH0799771B2 (ja) 1992-06-26 1995-10-25 インターナショナル・ビジネス・マシーンズ・コーポレイション 皮膜中の応力を制御する方法
US6218722B1 (en) 1997-02-14 2001-04-17 Gennum Corporation Antifuse based on silicided polysilicon bipolar transistor
US6943426B2 (en) 2002-08-14 2005-09-13 Advanced Analogic Technologies, Inc. Complementary analog bipolar transistors with trench-constrained isolation diffusion
US7041572B2 (en) 2002-10-25 2006-05-09 Vanguard International Semiconductor Corporation Fabrication method for a deep trench isolation structure of a high-voltage device
US7635621B2 (en) * 2002-11-22 2009-12-22 Micrel, Inc. Lateral double-diffused metal oxide semiconductor (LDMOS) device with an enhanced drift region that has an improved Ron area product
SE526366C3 (sv) * 2003-03-21 2005-10-26 Silex Microsystems Ab Elektriska anslutningar i substrat
US6815780B1 (en) 2003-04-15 2004-11-09 Motorola, Inc. Semiconductor component with substrate injection protection structure
US7639713B2 (en) 2004-01-21 2009-12-29 Emc Corporation Database block network attached storage packet joining
JP4592340B2 (ja) 2004-06-29 2010-12-01 三洋電機株式会社 半導体装置の製造方法
CN101147251B (zh) * 2005-03-24 2010-12-08 Nxp股份有限公司 制备具有掩埋掺杂区的半导体器件的方法
US7723204B2 (en) 2006-03-27 2010-05-25 Freescale Semiconductor, Inc. Semiconductor device with a multi-plate isolation structure
US7410862B2 (en) 2006-04-28 2008-08-12 International Business Machines Corporation Trench capacitor and method for fabricating the same
US8614151B2 (en) 2008-01-04 2013-12-24 Micron Technology, Inc. Method of etching a high aspect ratio contact
KR101610826B1 (ko) 2009-03-18 2016-04-11 삼성전자주식회사 커패시터를 갖는 반도체 장치의 형성방법
US8476530B2 (en) 2009-06-22 2013-07-02 International Business Machines Corporation Self-aligned nano-scale device with parallel plate electrodes
US20110062554A1 (en) 2009-09-17 2011-03-17 Hsing Michael R High voltage floating well in a silicon die
US8334190B2 (en) 2010-05-07 2012-12-18 Texas Instruments Incorporated Single step CMP for polishing three or more layer film stacks
US8399924B2 (en) 2010-06-17 2013-03-19 Texas Instruments Incorporated High voltage transistor using diluted drain
US8642423B2 (en) * 2011-11-30 2014-02-04 International Business Machines Corporation Polysilicon/metal contact resistance in deep trench
US9356133B2 (en) * 2012-02-01 2016-05-31 Texas Instruments Incorporated Medium voltage MOSFET device
US9293357B2 (en) 2012-07-02 2016-03-22 Texas Instruments Incorporated Sinker with a reduced width
US9082719B2 (en) 2012-10-19 2015-07-14 Infineon Technologies Ag Method for removing a dielectric layer from a bottom of a trench
US9136368B2 (en) * 2013-10-03 2015-09-15 Texas Instruments Incorporated Trench gate trench field plate semi-vertical semi-lateral MOSFET
US9385187B2 (en) * 2014-04-25 2016-07-05 Texas Instruments Incorporated High breakdown N-type buried layer

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5192708A (en) * 1991-04-29 1993-03-09 International Business Machines Corporation Sub-layer contact technique using in situ doped amorphous silicon and solid phase recrystallization
US5624858A (en) * 1993-07-07 1997-04-29 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing a semiconductor device with increased breakdown voltage
JPH08236614A (ja) * 1995-02-27 1996-09-13 Nippondenso Co Ltd 半導体装置の製造方法
US20010013610A1 (en) * 1999-08-02 2001-08-16 Min-Hwa Chi Vertical bipolar transistor based on gate induced drain leakage current
US20030168677A1 (en) * 2002-03-11 2003-09-11 Fu-Chieh Hsu One-transistor floating-body DRAM cell in bulk CMOS process with electrically isolated charge storage region
CN1581506A (zh) * 2003-08-08 2005-02-16 三菱电机株式会社 纵型半导体器件及其制造方法
CN101641763A (zh) * 2007-01-09 2010-02-03 威力半导体有限公司 半导体器件及其制造方法
US20100127318A1 (en) * 2008-11-24 2010-05-27 Nxp B.V. Bicmos integration of multiple-times-programmable non-volatile memories
US20130127007A1 (en) * 2011-11-23 2013-05-23 Che-Hao Chuang Transient voltage suppressor without leakage current

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