JP6618375B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP6618375B2 JP6618375B2 JP2016017350A JP2016017350A JP6618375B2 JP 6618375 B2 JP6618375 B2 JP 6618375B2 JP 2016017350 A JP2016017350 A JP 2016017350A JP 2016017350 A JP2016017350 A JP 2016017350A JP 6618375 B2 JP6618375 B2 JP 6618375B2
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- 239000004065 semiconductor Substances 0.000 title claims description 63
- 230000001681 protective effect Effects 0.000 claims description 59
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 7
- 229920005591 polysilicon Polymers 0.000 claims description 7
- 239000005380 borophosphosilicate glass Substances 0.000 claims description 6
- 239000000758 substrate Substances 0.000 claims description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- 239000010941 cobalt Substances 0.000 claims description 2
- 229910017052 cobalt Inorganic materials 0.000 claims description 2
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 2
- 239000003870 refractory metal Substances 0.000 claims description 2
- 229910021332 silicide Inorganic materials 0.000 claims description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 2
- 229910021341 titanium silicide Inorganic materials 0.000 claims description 2
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 claims description 2
- 229910021342 tungsten silicide Inorganic materials 0.000 claims description 2
- 239000004020 conductor Substances 0.000 description 22
- 238000004880 explosion Methods 0.000 description 10
- 238000010586 diagram Methods 0.000 description 7
- 238000003892 spreading Methods 0.000 description 6
- 238000007664 blowing Methods 0.000 description 4
- 238000000034 method Methods 0.000 description 3
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000005452 bending Methods 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000000155 melt Substances 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000002360 explosive Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 230000008719 thickening Effects 0.000 description 1
- 238000009966 trimming Methods 0.000 description 1
- 230000008016 vaporization Effects 0.000 description 1
- 238000009834 vaporization Methods 0.000 description 1
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- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
- H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
- H01L23/5258—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive the change of state resulting from the use of an external beam, e.g. laser beam or ion beam
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
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- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
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- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
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- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
- H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
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- H01L23/62—Protection against overvoltage, e.g. fuses, shunts
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- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
図7に、従来の小型化された半導体装置400の構成を示す。図7(a)は、半導体装置400において複数のヒューズ素子が形成された領域の平面図であり、図7(b)は、図7(a)におけるB−B線に沿った断面図である。
図8は、図示された3つのヒューズ素子43のうち、左側と中央のヒューズ素子43a及び43bを切断した状態を示している。
半導体装置400では、外部から浸入する水分によってヒューズ素子43や配線(図示せず)等が腐食することを防ぐために、絶縁膜45として耐湿性の高いBPSG膜またはPSG膜を用いている。しかしながら、BPSG膜及びPSG膜は、いずれも耐湿性においては優れているものの、機械的強度が低い。
図9は、図示された3つのヒューズ素子43のうち、中央のヒューズ素子43bを切断した状態を示している。
図8及び図9に示すような問題は、隣接するヒューズ素子の間隔が5μm以下と狭くなってくると特に発生しやすくなる。
[第1の実施形態]
図1は、第1の実施形態による半導体装置100の構造を説明するための図であり、図1(a)は、半導体装置100において複数のヒューズ素子が形成された領域の平面図、図1(b)は、図1(a)におけるB−B線に沿った断面図である。
そこで、以下に、第2の実施形態として、ヒューズ素子13の側面をより強固に支持する構成につき説明する。
図3は、第2の実施形態による半導体装置200の構造を説明するための図であり、図3(a)は、半導体装置200において複数のヒューズ素子が形成された領域の平面図、図3(b)は、図3(a)におけるB−B線に沿った断面図である。
その他の構成については、図1の半導体装置100と同一であるため、同一の構成要素には同一の符号を付し、重複する説明は適宜省略する。
保護絶縁膜24は、絶縁膜12上にヒューズ素子13を形成した後、例えば、プラズマCVD法により、ヒューズ素子13の上面及び側面を含む全面に保護絶縁膜24を構成するシリコン窒化膜等の絶縁膜を形成した後、ヒューズ素子13の上面が露出するまでエッチバックを行い、ヒューズ素子13の側面に絶縁膜を残すことにより形成される。
図5は、第3の実施形態による半導体装置300の構造を説明するための図であり、図5(a)は、半導体装置300において複数のヒューズ素子が形成された領域の平面図、図5(b)は、図5(a)におけるB−B線に沿った断面図である。
その他の構成については、図1の半導体装置100と同一であるため、同一の構成要素には同一の符号を付し、重複する説明は適宜省略する。
保護絶縁膜34は、ヒューズ素子13の側面に設けられた第1の部分34sと、ヒューズ素子13の上面に設けられた第2の部分34tとを含んで構成されている。
また、保護絶縁膜34の第1の部分34sの膜厚は、上記第2の実施形態にて説明したとおり、厚ければ厚いほど良く、隣り合う第1の部分34s同士が接する厚さとするのが最も好ましい。
例えば、ヒューズ素子13を構成する導電体として、上記各実施形態においては、ポリシリコン膜を用いる例を示したが、これに限らず、高融点金属膜や、ポリシリコン膜上にチタンシリサイド膜、タングステンシリサイド膜、及びコバルトシリサイド膜のいずれかが積層された膜等を用いることも可能である。
12,15,42,45 絶縁膜
13,43 ヒューズ素子
14,24,34 保護絶縁膜
16,46 ヒューズ開口部
17,47 ヒューズブロー痕
48 再付着層
Claims (5)
- 半導体基板上に設けられた第1の絶縁膜と、
前記第1の絶縁膜上に互いに隣接して設けられた複数のヒューズ素子と、
前記ヒューズ素子の少なくとも側面を覆う保護絶縁膜と、
前記ヒューズ素子及び前記保護絶縁膜を覆うBPSG膜またはPSG膜からなる第2の絶縁膜とを備え、
前記保護絶縁膜の機械的強度が前記第2の絶縁膜より高く、
前記保護絶縁膜が前記ヒューズ素子の前記側面を覆う第1の部分と、前記ヒューズ素子の上面を覆う第2の部分とを有することを特徴とする半導体装置。 - 前記保護絶縁膜の前記第1の部分の厚さが前記第2の部分の厚さよりも厚いことを特徴とする請求項1に記載の半導体装置。
- 前記保護絶縁膜の前記第2の部分の厚さが100nm以下であることを特徴とする請求項1または2に記載の半導体装置。
- 前記保護絶縁膜がシリコン窒化膜またはシリコン酸窒化膜であることを特徴とする請求項1乃至3のいずれか一項に記載の半導体装置。
- 前記ヒューズ素子がポリシリコン膜、高融点金属膜、またはポリシリコン膜上にチタンシリサイド膜、タングステンシリサイド膜、及びコバルトシリサイド膜のいずれかが積層された膜で構成されていることを特徴とする請求項1乃至4のいずれか一項に記載の半導体装置。
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
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JP2016017350A JP6618375B2 (ja) | 2016-02-01 | 2016-02-01 | 半導体装置 |
TW106102521A TWI714713B (zh) | 2016-02-01 | 2017-01-24 | 半導體裝置 |
CN201710056947.8A CN107026145B (zh) | 2016-02-01 | 2017-01-26 | 半导体装置 |
US15/420,744 US9984966B2 (en) | 2016-02-01 | 2017-01-31 | Semiconductor device having fuse elements |
KR1020170014436A KR20170091532A (ko) | 2016-02-01 | 2017-02-01 | 반도체 장치 |
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JP2016017350A JP6618375B2 (ja) | 2016-02-01 | 2016-02-01 | 半導体装置 |
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JP2017139264A JP2017139264A (ja) | 2017-08-10 |
JP6618375B2 true JP6618375B2 (ja) | 2019-12-11 |
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JP2016017350A Expired - Fee Related JP6618375B2 (ja) | 2016-02-01 | 2016-02-01 | 半導体装置 |
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US (1) | US9984966B2 (ja) |
JP (1) | JP6618375B2 (ja) |
KR (1) | KR20170091532A (ja) |
CN (1) | CN107026145B (ja) |
TW (1) | TWI714713B (ja) |
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CN106057823B (zh) * | 2016-07-29 | 2019-05-10 | 京东方科技集团股份有限公司 | 一种阵列基板及其制作方法、显示装置 |
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5847596Y2 (ja) * | 1979-09-05 | 1983-10-29 | 富士通株式会社 | 半導体装置 |
US5521116A (en) * | 1995-04-24 | 1996-05-28 | Texas Instruments Incorporated | Sidewall formation process for a top lead fuse |
JPH09172087A (ja) * | 1995-12-19 | 1997-06-30 | Toshiba Corp | 半導体装置 |
US6096566A (en) * | 1998-04-22 | 2000-08-01 | Clear Logic, Inc. | Inter-conductive layer fuse for integrated circuits |
KR100268438B1 (ko) | 1998-07-03 | 2000-10-16 | 윤종용 | 복수의 퓨즈들을 갖는 반도체 메모리 장치 |
US6235557B1 (en) * | 1999-04-28 | 2001-05-22 | Philips Semiconductors, Inc. | Programmable fuse and method therefor |
US6249038B1 (en) * | 1999-06-04 | 2001-06-19 | International Business Machines Corporation | Method and structure for a semiconductor fuse |
TW410416B (en) * | 1999-06-15 | 2000-11-01 | Vanguard Int Semiconduct Corp | Method for forming fuse in DRAM |
US6869750B2 (en) * | 1999-10-28 | 2005-03-22 | Fujitsu Limited | Structure and method for forming a multilayered structure |
KR100476694B1 (ko) * | 2002-11-07 | 2005-03-17 | 삼성전자주식회사 | 반도체 장치의 퓨즈 구조물 및 그 제조 방법 |
US7148089B2 (en) * | 2004-03-01 | 2006-12-12 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for forming copper fuse links |
US7556989B2 (en) * | 2005-03-22 | 2009-07-07 | Samsung Electronics Co., Ltd. | Semiconductor device having fuse pattern and methods of fabricating the same |
KR101129772B1 (ko) * | 2009-07-29 | 2012-04-13 | 주식회사 하이닉스반도체 | 반도체 소자의 퓨즈 및 그 형성 방법 |
KR101674057B1 (ko) * | 2010-04-01 | 2016-11-08 | 삼성전자 주식회사 | 강화된 복합 절연막을 포함하는 반도체 칩 구조 및 그 제조 방법 |
JPWO2014162987A1 (ja) * | 2013-04-04 | 2017-02-16 | ローム株式会社 | 複合チップ部品、回路アセンブリおよび電子機器 |
US9773588B2 (en) * | 2014-05-16 | 2017-09-26 | Rohm Co., Ltd. | Chip parts |
-
2016
- 2016-02-01 JP JP2016017350A patent/JP6618375B2/ja not_active Expired - Fee Related
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2017
- 2017-01-24 TW TW106102521A patent/TWI714713B/zh not_active IP Right Cessation
- 2017-01-26 CN CN201710056947.8A patent/CN107026145B/zh active Active
- 2017-01-31 US US15/420,744 patent/US9984966B2/en not_active Expired - Fee Related
- 2017-02-01 KR KR1020170014436A patent/KR20170091532A/ko not_active Application Discontinuation
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CN107026145B (zh) | 2023-05-23 |
JP2017139264A (ja) | 2017-08-10 |
TWI714713B (zh) | 2021-01-01 |
US9984966B2 (en) | 2018-05-29 |
TW201801250A (zh) | 2018-01-01 |
KR20170091532A (ko) | 2017-08-09 |
CN107026145A (zh) | 2017-08-08 |
US20170221824A1 (en) | 2017-08-03 |
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