CN107026145B - 半导体装置 - Google Patents
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- CN107026145B CN107026145B CN201710056947.8A CN201710056947A CN107026145B CN 107026145 B CN107026145 B CN 107026145B CN 201710056947 A CN201710056947 A CN 201710056947A CN 107026145 B CN107026145 B CN 107026145B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 74
- 230000001681 protective effect Effects 0.000 claims abstract description 74
- 239000005380 borophosphosilicate glass Substances 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 7
- 229920005591 polysilicon Polymers 0.000 claims description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 4
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- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 claims description 2
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Abstract
课题在于:提供一种半导体装置,该半导体装置即便在维持熔丝元件的耐湿性并且邻接的熔丝元件的间隔狭窄的情况下,利用激光照射切断熔丝元件时,也能防止构成熔丝元件的导体的再附着、或熔丝元件的断线等。解决方案如下,即具备:设在半导体衬底上的第1绝缘膜;彼此邻接地设在第1绝缘膜上的多个熔丝元件;覆盖熔丝元件的至少侧面的保护绝缘膜;以及覆盖熔丝元件及保护绝缘膜的由BPSG膜或PSG膜构成的第2绝缘膜,保护绝缘膜的机械强度高于第2绝缘膜。
Description
技术领域
本发明涉及半导体装置,特别涉及具有利用激光照射来烧断(blow)的熔丝元件的半导体装置。
背景技术
一般,在半导体装置的电阻值的调整或冗长电路的设定中广泛使用熔丝元件。通过切断熔丝元件,从导通状态变化到非导通状态,向修调(trimming)电路存储期望的信息。熔丝元件的切断,可采用利用激光照射来烧断熔丝元件的方法、或流动大电流而熔断熔丝元件的方法等。在此,所谓烧断是指熔丝因热而破裂,构成物散落的情形。
利用激光照射来烧断的熔丝元件,由多晶硅等的导体构成,在被氧化硅膜等的绝缘膜覆盖的状态下,隔着该绝缘膜照射激光从而被切断(例如,参照专利文献1)。
【现有技术文献】
【专利文献】
【专利文献1】日本特开2000-40388号公报。
发明内容
【发明要解决的课题】
近年,随着半导体装置的小型化,熔丝元件也被要求小型化,特别是在并排配置多个熔丝元件的情况下,产生使邻接的熔丝元件的间隔狭窄的需要。
图7示出现有的小型化的半导体装置400的结构。图7(a)是在半导体装置400中形成多个熔丝元件的区域的俯视图,图7(b)是沿着图7(a)中的B-B线的截面图。
如图7所示那样,现有的半导体装置400在形成在半导体衬底41上的绝缘膜42上,具备靠近配置的多个由多晶硅等的导体构成的熔丝元件43(43a、43b、43c)。进而,设有覆盖多个熔丝元件43的绝缘膜45,在绝缘膜45形成有用于激光照射的熔丝开口部46。
图8是用于说明在图7的半导体装置400中在切断熔丝元件43的情况下产生的问题的一个例子的图,图8(a)是与图7(a)对应的俯视图,图8(b)是沿着图8(a)中的B-B线的截面图,图8(c)是沿着图8(a)中的C-C线的截面图。
图8示出切断图示的三个熔丝元件43之中左侧和中央的熔丝元件43a及43b的状态。
如图8所示那样,若向靠近配置的熔丝元件43a及43b的每一个照射激光,则熔丝元件43a及43b的被激光照射的部分的导体熔化、汽化而蒸汽压力上升,连同包覆的绝缘膜45爆炸而熔丝元件43a及43b分别成为非导通状态。
然而,由于邻接的熔丝元件43的间隔狭窄,所以因激光照射而形成的熔丝烧断痕47会成为相邻的熔丝烧断痕47彼此相连的状态。
此时,存在熔化、汽化的导体没有吹飞到远处,如图8(a)及(c)所示那样,再附着到熔丝烧断痕47的内侧面,形成再附着层48的情况。即,产生因汽化的导体的再附着而切断的邻接的熔丝元件43彼此会电短路这一问题。
这基于以下的理由。
半导体装置400中,为了防止熔丝元件43或布线(未图示)等因从外部渗入的水分而腐蚀的情况,作为绝缘膜45使用耐湿性高的BPSG膜或PSG膜。然而,BPSG膜及PSG膜均是在耐湿性上优异,但是机械强度低。
若绝缘膜45的机械强度低,则在激光照射时的导体的蒸汽压力未充分上升的状态下引起爆炸,因此导体没有吹飞到远处,容易引起熔化、汽化的导体向熔丝烧断痕47内的再附着。如上述,因小型化而邻接的熔丝元件43的间隔变狭窄,因此是相邻的熔丝烧断痕47彼此相连状态,从而如图8(a)所示那样,再附着层48会以连接切断的熔丝元件43a和43b的方式形成,其结果,成为熔丝元件43a和43b会短路。
图9是用于说明在图7的半导体装置400中,切断熔丝元件43的情况下产生的问题的其他例的图,图9(a)是与图7(a)对应的俯视图,图9(b)是沿着图9(a)中的B-B线的截面图。
图9示出切断图示的三个熔丝元件43之中中央的熔丝元件43b的状态。
如图9所示那样,存在若向熔丝元件43b照射激光而使熔丝元件43b烧断,则会在熔丝烧断痕47内露出邻接的熔丝元件43(在本例中熔丝元件43c)的一部分的情况。
即,如上述,由于绝缘膜45的机械强度低,熔丝烧断痕47会扩展到与熔丝元件43b邻接的熔丝元件43c上,在熔丝元件43c形成露出部EXP。如此若露出熔丝元件43c,则会牵涉到熔丝元件43c因水分而腐蚀,或者从露出部EXP进行氧化而熔丝元件43c断线等的问题。
关于如图8及图9所示的问题,若邻接的熔丝元件的间隔狭窄到5μm以下则变得特别容易发生。
本发明是为解决如上述的问题而成的发明,其目的在于提供一种半导体装置,该半导体装置即便在维持熔丝元件的耐湿性并且邻接的熔丝元件的间隔狭窄的情况下,在利用激光照射来切断熔丝元件时,也能防止构成熔丝元件的导体的再附着、或熔丝元件的断线等。
【用于解决课题的方案】
本发明的半导体装置,其特征如下,即具备:设在半导体衬底上的第1绝缘膜;彼此邻接地设在所述第1绝缘膜上的多个熔丝元件;覆盖所述熔丝元件的至少侧面的保护绝缘膜;以及覆盖所述熔丝元件及所述保护绝缘膜的由BPSG膜或PSG膜构成的第2绝缘膜,所述保护绝缘膜的机械强度高于所述第2绝缘膜。
【发明效果】
依据本发明,机械强度比第2绝缘膜还高的保护绝缘膜覆盖熔丝元件的至少侧面,因此激光照射时在熔丝元件的被激光照射的部分的导体的蒸汽压力变高的状态下引起爆炸。因而,以比现有的半导体装置400还大的力引起爆炸,因此取得熔化、汽化的导体吹飞到远处,变得难以引起爆炸而形成的向烧断痕内的再附着的效果。
另外,因为覆盖熔丝元件侧面的保护绝缘膜的存在,该爆炸的力难以在水平方向扩展,因此抑制熔丝烧断痕扩展到与激光照射的熔丝元件邻接的熔丝元件上的情况,因而,能够防止邻接的熔丝元件露出。
附图说明
【图1】是用于说明依据第1实施方式的半导体装置100的构造的图,图1(a)是半导体装置100中形成多个熔丝元件的区域的俯视图,图1(b)是沿着图1(a)中的B-B线的截面图。
【图2】是用于说明图1的半导体装置100中的熔丝元件烧断后的状态的图,图2(a)是与图1(a)对应的俯视图,图2(b)是沿着图2(a)中的B-B线的截面图。
【图3】是用于说明依据第2实施方式的半导体装置200的构造的图,图3(a)是半导体装置200中形成多个熔丝元件的区域的俯视图,图3(b)是沿着图3(a)中的B-B线的截面图。
【图4】是用于说明图3的半导体装置200中的熔丝元件烧断后的状态的图,图4(a)是与图3(a)对应的俯视图,图4(b)是沿着图4(a)中的B-B线的截面图。
【图5】是用于说明依据第3实施方式的半导体装置300的构造的图,图5(a)是半导体装置300中形成多个熔丝元件的区域的俯视图,图5(b)是沿着图5(a)中的B-B线的截面图。
【图6】是用于说明图5的半导体装置300中的熔丝元件烧断后的状态的图,图6(a)是与图5(a)对应的俯视图,图6(b)是沿着图6(a)中的B-B线的截面图。
【图7】是用于说明现有的半导体装置400的构造的图,图7(a)是半导体装置400中形成多个熔丝元件的区域的俯视图,图7(b)是沿着图7(a)中的B-B线的截面图。
【图8】是用于说明现有的半导体装置400中的熔丝元件烧断后的问题的图,图8(a)是与图7(a)对应的俯视图,图8(b)是沿着图8(a)中的B-B线的截面图,图8(c)是沿着图8(a)中的C-C线的截面图。
【图9】是用于说明现有的半导体装置400中的熔丝元件烧断后的其他问题的图,图9(a)是与图7(a)对应的俯视图,图9(b)是沿着图9(a)中的B-B线的截面图。
具体实施方式
以下,参照附图,对本发明的实施方式进行说明。
[第1实施方式]
图1是用于说明依据第1实施方式的半导体装置100的构造的图,图1(a)是半导体装置100中形成多个熔丝元件的区域的俯视图,图1(b)是沿着图1(a)中的B-B线的截面图。
如图1所示那样,在依据本实施方式的半导体装置100中,在半导体衬底11上设有绝缘膜12,在其上彼此邻接地配置有由多晶硅膜等的导体构成的多个熔丝元件13(13a、13b、13c)。进而,设有覆盖多个熔丝元件13的侧面、上表面及绝缘膜12的上表面的保护绝缘膜14。在保护绝缘膜14上设有绝缘膜15,在绝缘膜15形成有激光照射用的熔丝开口部16。
绝缘膜15为了防止熔丝元件13或形成在未图示的区域的布线等因从外部渗入的水分而腐蚀(氧化等)的情况,由难以通过水分的、即耐湿性高的膜即BPSG膜或PSG膜构成。
保护绝缘膜14由机械强度比绝缘膜15还高的绝缘膜构成,例如,能够使用氮化硅膜或氮氧化硅膜。任一种膜都能够容易地导入到通常的半导体制造方法中。
表示机械强度的指标有许多,例如包含BPSG膜或PSG膜的石英(SiO2)的弯曲强度为约150MPa,与之相对包含氮化硅膜的氮化硅为600~1000MPa,氮化硅的弯曲强度比SiO2高。
在如上述那样构成的半导体装置100中,若对图1所示的三个熔丝元件13之中靠近配置的熔丝元件13a及13b的每一个照射激光,则熔丝元件13a及13b的被激光照射的部分的导体熔化、汽化而蒸汽压力上升。此时,由于熔丝元件13的侧面及上表面被机械强度比绝缘膜15还高的保护绝缘膜14覆盖,即便导体熔化、汽化,也不会立即爆炸。即,激光照射部的蒸汽压力充分地变高到能够破坏保护绝缘膜14的程度之后才会连同保护绝缘膜14和其上的绝缘膜15爆炸,熔丝元件13a及13b分别成为非导通状态。
在图2中示出如此处理而切断熔丝元件13a及13b的状态。图2(a)是与图1(a)对应的俯视图,图2(b)是沿着图2(a)中的B-B线的截面图。
如图2所示那样,在熔丝元件13a及13b的切断部的周围,分别形成有熔丝烧断痕17,但是在熔丝烧断痕17内不会形成再附着层。因而,能防止如图8所示的现有的半导体装置400那样切断的熔丝元件13a和13b短路的情况。这是因为:如上述由于熔丝元件13的侧面及上表面被保护绝缘膜14覆盖,因此在被激光照射的导体的蒸汽压力充分提高之后引起爆炸,从而能够使熔化、汽化的导体散落到远处。
另外,由于熔丝元件13的侧面被机械强度高的保护绝缘膜14支撑,所以爆炸的力难以在水平方向扩展,能抑制烧断痕扩展到与激光照射的熔丝元件邻接的熔丝元件上。由此,邻接的熔丝元件(例如,熔丝元件13c)露出,能够防止受到损伤。
在本实施方式中,熔丝元件13的上表面中的保护绝缘膜14的膜厚,若过厚则以通常的激光照射条件烧断变得困难,因此优选为100nm以下。下限可以设为10nm以上,以能稳定形成保护绝缘膜14。
在绝缘膜12上形成熔丝元件13后,保护绝缘膜14作为一体的膜例如通过等离子体CVD法,在熔丝元件13的上表面、侧面及绝缘膜12的上表面形成。因而,在本实施方式中,熔丝元件的侧面的保护绝缘膜14的膜厚被限制成与熔丝元件13的上表面的保护绝缘膜14的膜厚相等的厚度。
因此,以下,作为第2实施方式,对更加牢固地支撑熔丝元件13的侧面的结构进行说明。
[第2实施方式]
图3是用于说明依据第2实施方式的半导体装置200的构造的图,图3(a)是半导体装置200中形成多个熔丝元件的区域的俯视图,图3(b)是沿着图3(a)中的B-B线的截面图。
本实施方式的半导体装置200中,取代图1所示的第1实施方式的半导体装置100中的保护绝缘膜14,在各熔丝元件13的两侧面分别形成有保护绝缘膜24。保护绝缘膜24与保护绝缘膜14同样,由机械强度比绝缘膜15还高的绝缘膜构成,例如,能够使用氮化硅膜或氮氧化硅膜。
关于其他的结构,由于与图1的半导体装置100相同,对于相同结构要素标注相同标号,适当省略重复的说明。
保护绝缘膜24与第1实施方式的保护绝缘膜14不同,不在熔丝元件13的上表面和绝缘膜12的上表面形成。保护绝缘膜24形成为比半导体装置100中的保护绝缘膜14还厚。由此,与半导体装置100中的保护绝缘膜14相比,熔丝元件13的侧面还更加牢固地被支撑。
图4中示出在半导体装置200中,因激光照射而熔丝元件13a及13b被切断的状态。图4(a)是与图3(a)对应的俯视图,图4(b)是沿着图4(a)中的B-B线的截面图。
如上述,在本实施方式中,由于保护绝缘膜24形成为较厚,如图4所示那样,熔丝烧断痕27水平方向的扩展变得比图2所示的熔丝烧断痕17还狭窄。即,激光的照射造成的爆炸的力在水平方向扩展,能够比第1实施方式还更加可靠地抑制烧断痕扩展到邻接的熔丝元件上。
由于保护绝缘膜24的厚度越厚预期的效果变得越高,所以最优选设为相邻的保护绝缘膜24彼此相接的厚度。
保护绝缘膜24通过如下方法形成,即在绝缘膜12上形成熔丝元件13后,例如,通过等离子体CVD法在包括熔丝元件13的上表面及侧面的整个面形成构成保护绝缘膜24的氮化硅膜等的绝缘膜后,进行深腐蚀(each back)到熔丝元件13的上表面露出,使绝缘膜残留在熔丝元件13的侧面。
因而,与在半导体装置100形成保护绝缘膜14相比,还产生追加深腐蚀的工序的需要。然而,保护绝缘膜24较厚,从而与第1实施方式的半导体装置100相比还能提高对邻接熔丝元件的损伤防止效果。
另外,由于在熔丝元件13的上表面不设保护绝缘膜,所以成为在激光照射部的蒸汽压力比半导体装置100稍低的状态下爆炸,但是在熔丝元件13的侧面上设有保护绝缘膜24,从而与现有的半导体装置400相比,能够在提高激光照射部的蒸汽压力的状态下爆炸,因而,也能够抑制熔化、汽化的导体再附着到熔丝烧断痕27内。
[第3实施方式]
图5是用于说明依据第3实施方式的半导体装置300的构造的图,图5(a)是半导体装置300中形成多个熔丝元件的区域的俯视图,图5(b)是沿着图5(a)中的B-B线的截面图。
本实施方式的半导体装置300中,取代图1所示的第1实施方式的半导体装置100中的保护绝缘膜14,形成有保护绝缘膜34。保护绝缘膜34与保护绝缘膜14同样,由机械强度比绝缘膜15还高的绝缘膜构成,例如,能够使用氮化硅膜或氮氧化硅膜。
关于其他的结构,由于与图1的半导体装置100相同,对于相同结构要素标注相同标号,适当省略重复的说明。
如图5所示那样,保护绝缘膜34覆盖多个熔丝元件13的侧面、上表面及绝缘膜12上表面而形成。
保护绝缘膜34构成为包括设在熔丝元件13的侧面的第1部分34s和设在熔丝元件13的上表面的第2部分34t。
而且,保护绝缘膜的第1部分34s的厚度形成为比第2部分34t的厚度还厚。
另外,保护绝缘膜34的第1部分34s的膜厚,如在上述第2实施方式中说明的那样,越厚越好,最优选设为相邻的第1部分34s彼此相接的厚度。
保护绝缘膜34的第2部分34t的膜厚,如在上述第1实施方式中说明的那样,若过厚则利用通常的激光照射条件烧断变得困难,因此优选为100nm以下。
保护绝缘膜34通过如下方法形成,即首先与形成第2实施方式中的保护绝缘膜24同样,除掉构成保护绝缘膜34的氮化硅膜等的绝缘膜,以使熔丝元件13的上表面露出,且在熔丝元件13的侧面残留绝缘膜,其后,利用等离子体CVD法,在整个面形成保护绝缘膜34的第2部分34t所需要的厚度的绝缘膜。
在图6示出如上述那样构成的半导体装置300中,熔丝元件13a及13b因激光照射而被切断的状态。图6(a)是与图5(a)对应的俯视图,图6(b)是沿着图6(a)中的B-B线的截面图。
如图6所示那样,在熔丝元件13a及13b的切断部的周围,分别形成有熔丝烧断痕37,而在熔丝烧断痕37内不会形成再附着层。因而,防止切断的熔丝元件13a和13b短路。这是因为:与第1实施方式的半导体装置100同样,通过熔丝元件13的侧面及上表面被保护绝缘膜34覆盖,被激光照射的导体的蒸汽压力充分地提高之后引起爆炸,从而能够使熔化、汽化的导体散落到远处。
进而,熔丝烧断痕37水平方向的扩展与图2所示的熔丝烧断痕17相比还狭窄。即,因激光的照射而爆炸的力在水平方向扩展,能够比第1实施方式还可靠地抑制烧断痕扩展到邻接的熔丝元件上。
如此,依据本实施方式,通过使保护绝缘膜34的第1部分34s较厚,能够比第1实施方式还牢固地支撑熔丝元件13的侧面,抑制熔丝烧断痕37的水平方向的扩展。另外,通过在熔丝元件13的上表面设有能够由激光照射烧断的厚度的保护绝缘膜34的第2部分34t,与第1实施方式同样,在激光照射时,能够在熔化、汽化的导体的蒸汽压力充分地提高之后爆炸。
如以上说明的那样,依据本发明,防止因导体的再附着而造成的邻接熔丝元件间的短路,另外能够防止与烧断的熔丝元件邻接的熔丝元件的损坏或断线,因而,能够提高半导体装置的成品率或可靠性。
以上,对本发明的实施方式进行了说明,但本发明并不限于上述实施方式,在不脱离本发明的宗旨的范围内可进行各种各样的变更这一点无需赘述。
例如,作为构成熔丝元件13的导体,在上述各实施方式中,示出了使用多晶硅膜的例子,但不限于此,也可以使用高熔点金属膜、或在多晶硅膜上层叠钛硅化物膜、钨硅化物膜、及钴硅化物膜的任一种的膜等。
【标号说明】
11 半导体衬底;12、15、42、45 绝缘膜;13、43 熔丝元件;14、24、34 保护绝缘膜;16、46 熔丝开口部;17、47 熔丝烧断痕;48 再附着层。
Claims (7)
1.一种半导体装置,其特征在于具备:
设在半导体衬底上的第1绝缘膜;
多个熔丝元件,其与所述第1绝缘膜接触且在所述第1绝缘膜上彼此邻接地设置;
覆盖所述熔丝元件的至少侧面的保护绝缘膜;以及
覆盖所述熔丝元件及所述保护绝缘膜的由BPSG膜或PSG膜构成的第2绝缘膜,
所述保护绝缘膜的机械强度高于所述第2绝缘膜,
所述保护绝缘膜具有在相邻设置的所述熔丝元件彼此之间覆盖所述熔丝元件的所述侧面的第1部分、和覆盖所述熔丝元件的上表面的第2部分,并且所述保护绝缘膜的所述第1部分的厚度比所述第2部分的厚度还厚。
2.如权利要求1所述的半导体装置,其特征在于,所述保护绝缘膜的所述第1部分的厚度,设为相邻的第1部分彼此相接的厚度。
3.如权利要求1所述的半导体装置,其特征在于,所述保护绝缘膜的所述第2部分的厚度为100nm以下。
4.一种半导体装置,其特征在于具备:
设在半导体衬底上的第1绝缘膜;
多个熔丝元件,其与所述第1绝缘膜接触且在所述第1绝缘膜上彼此邻接地设置;
覆盖所述熔丝元件的侧面的保护绝缘膜;以及
覆盖所述熔丝元件及所述保护绝缘膜的由BPSG膜或PSG膜构成的第2绝缘膜,
所述保护绝缘膜的机械强度高于所述第2绝缘膜,
在相邻设置的所述熔丝元件彼此之间,所述保护绝缘膜的厚度设为相邻的保护绝缘膜彼此相接的厚度。
5.一种半导体装置,其特征在于具备:
设在半导体衬底上的第1绝缘膜;
多个熔丝元件,其与所述第1绝缘膜接触且在所述第1绝缘膜上彼此邻接地设置;
覆盖所述熔丝元件的至少侧面的保护绝缘膜;以及
覆盖所述熔丝元件及所述保护绝缘膜的由BPSG膜或PSG膜构成的第2绝缘膜,
所述保护绝缘膜的机械强度高于所述第2绝缘膜,
所述保护绝缘膜具有在相邻设置的所述熔丝元件彼此之间覆盖所述熔丝元件的所述侧面的第1部分、和覆盖所述熔丝元件的上表面的第2部分,并且所述保护绝缘膜的所述第1部分的膜厚与所述第2部分的膜厚相等。
6.如权利要求1至5的任一项所述的半导体装置,其特征在于,所述保护绝缘膜为氮化硅膜或氮氧化硅膜。
7.如权利要求1至5的任一项所述的半导体装置,其特征在于,所述熔丝元件由多晶硅膜、高熔点金属膜、或在多晶硅膜上层叠钛硅化物膜、钨硅化物膜、及钴硅化物膜的任一种的膜构成。
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JPH09172087A (ja) * | 1995-12-19 | 1997-06-30 | Toshiba Corp | 半導体装置 |
WO2014162987A1 (ja) * | 2013-04-04 | 2014-10-09 | ローム株式会社 | 複合チップ部品、回路アセンブリおよび電子機器 |
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JPS5847596Y2 (ja) * | 1979-09-05 | 1983-10-29 | 富士通株式会社 | 半導体装置 |
US5521116A (en) * | 1995-04-24 | 1996-05-28 | Texas Instruments Incorporated | Sidewall formation process for a top lead fuse |
US6096566A (en) * | 1998-04-22 | 2000-08-01 | Clear Logic, Inc. | Inter-conductive layer fuse for integrated circuits |
KR100268438B1 (ko) | 1998-07-03 | 2000-10-16 | 윤종용 | 복수의 퓨즈들을 갖는 반도체 메모리 장치 |
US6235557B1 (en) * | 1999-04-28 | 2001-05-22 | Philips Semiconductors, Inc. | Programmable fuse and method therefor |
US6249038B1 (en) * | 1999-06-04 | 2001-06-19 | International Business Machines Corporation | Method and structure for a semiconductor fuse |
TW410416B (en) * | 1999-06-15 | 2000-11-01 | Vanguard Int Semiconduct Corp | Method for forming fuse in DRAM |
US6869750B2 (en) * | 1999-10-28 | 2005-03-22 | Fujitsu Limited | Structure and method for forming a multilayered structure |
KR100476694B1 (ko) * | 2002-11-07 | 2005-03-17 | 삼성전자주식회사 | 반도체 장치의 퓨즈 구조물 및 그 제조 방법 |
US7148089B2 (en) * | 2004-03-01 | 2006-12-12 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for forming copper fuse links |
US7556989B2 (en) * | 2005-03-22 | 2009-07-07 | Samsung Electronics Co., Ltd. | Semiconductor device having fuse pattern and methods of fabricating the same |
KR101129772B1 (ko) * | 2009-07-29 | 2012-04-13 | 주식회사 하이닉스반도체 | 반도체 소자의 퓨즈 및 그 형성 방법 |
KR101674057B1 (ko) * | 2010-04-01 | 2016-11-08 | 삼성전자 주식회사 | 강화된 복합 절연막을 포함하는 반도체 칩 구조 및 그 제조 방법 |
US9773588B2 (en) * | 2014-05-16 | 2017-09-26 | Rohm Co., Ltd. | Chip parts |
-
2016
- 2016-02-01 JP JP2016017350A patent/JP6618375B2/ja not_active Expired - Fee Related
-
2017
- 2017-01-24 TW TW106102521A patent/TWI714713B/zh not_active IP Right Cessation
- 2017-01-26 CN CN201710056947.8A patent/CN107026145B/zh active Active
- 2017-01-31 US US15/420,744 patent/US9984966B2/en not_active Expired - Fee Related
- 2017-02-01 KR KR1020170014436A patent/KR20170091532A/ko not_active Application Discontinuation
Patent Citations (2)
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JPH09172087A (ja) * | 1995-12-19 | 1997-06-30 | Toshiba Corp | 半導体装置 |
WO2014162987A1 (ja) * | 2013-04-04 | 2014-10-09 | ローム株式会社 | 複合チップ部品、回路アセンブリおよび電子機器 |
Also Published As
Publication number | Publication date |
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JP6618375B2 (ja) | 2019-12-11 |
TW201801250A (zh) | 2018-01-01 |
US9984966B2 (en) | 2018-05-29 |
JP2017139264A (ja) | 2017-08-10 |
KR20170091532A (ko) | 2017-08-09 |
CN107026145A (zh) | 2017-08-08 |
TWI714713B (zh) | 2021-01-01 |
US20170221824A1 (en) | 2017-08-03 |
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