JP6603657B2 - 撮像装置 - Google Patents
撮像装置 Download PDFInfo
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- JP6603657B2 JP6603657B2 JP2016526750A JP2016526750A JP6603657B2 JP 6603657 B2 JP6603657 B2 JP 6603657B2 JP 2016526750 A JP2016526750 A JP 2016526750A JP 2016526750 A JP2016526750 A JP 2016526750A JP 6603657 B2 JP6603657 B2 JP 6603657B2
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- transistor
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- semiconductor
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Description
本実施の形態では、本発明の一態様の撮像装置について、図面を参照して説明する。
図1(A)は、本発明の一態様の撮像装置100の構成例を示す平面図である。撮像装置100は、画素部110と、第1の回路260、第2の回路270、第3の回路280、及び第4の回路290を有する。画素部110は、p行q列(p及びqは2以上の自然数)のマトリクス状に配置された複数の画素111(撮像素子)を有する。第1の回路260乃至第4の回路290は、複数の画素111に接続し、複数の画素111を駆動するための信号を供給する機能を有する。なお、本明細書等において、第1の回路260乃至第4の回路290などを「周辺回路」もしくは「駆動回路」と呼ぶ場合がある。例えば、第1の回路260は周辺回路の一部と言える。
画素111の構成例について、図3乃至図5を用いて説明する。画素111は、トランジスタ131、トランジスタ132、トランジスタ133、トランジスタ134、容量素子135、及び光電変換素子136などの機能素子を有する。また、画素111を構成する機能素子のうち、光電変換素子136以外の機能素子で構成した回路を画素駆動回路112と呼ぶ。なお、画素駆動回路112は光電変換素子136と電気的に接続される。画素駆動回路112は、光電変換素子136の受光量に応じたアナログ信号を生成する機能を有する。
撮像装置100が有する画素111を副画素として用いて、複数の画素111それぞれに異なる波長域の光を透過するフィルタ(カラーフィルタ)を設けることで、カラー画像表示を実現するための情報を取得することができる。
本実施の形態では、上記実施の形態に示した撮像装置100を固体撮像素子の一種であるCMOSイメージセンサで構成する場合の一例について、図11乃至図15を用いて説明する。図11に示す画素領域251は、撮像装置100が有する画素111の一部の断面図である。図11に示す周辺回路領域252は、撮像装置100が有する周辺回路の一部の断面図である。また、図11に示すトランジスタ134の拡大図を図12(A)に示す。また、図11に示す容量素子135の拡大図を図12(B)に示す。また、図11に示すトランジスタ281の拡大図を図14(A)に示す。また、図11に示すトランジスタ282の拡大図を図14(B)に示す。
ここで、半導体層242a、半導体層242b、および半導体層242cの積層により構成される半導体層242の機能およびその効果について、図13示すエネルギーバンド構造図を用いて説明する。図13は、図12(A)にC1−C2の一点鎖線で示す部位のエネルギーバンド構造図である。図13は、トランジスタ134のチャネル形成領域のエネルギーバンド構造を示している。
ここで、半導体層242に適用可能な酸化物半導体膜について詳細に説明しておく。
周辺回路及び画素回路に、OR回路、AND回路、NAND回路、及びNOR回路などの論理回路や、インバータ回路、バッファ回路、シフトレジスタ回路、フリップフロップ回路、エンコーダ回路、デコーダ回路、増幅回路、アナログスイッチ回路、積分回路、微分回路、及びメモリ素子などを適宜設けることができる。
本実施の形態では、上記実施の形態に示したトランジスタと置き換えて使用することができるトランジスタの構成例について、図18乃至図22を用いて説明する。
図18(A1)に例示するトランジスタ410は、ボトムゲート型のトランジスタの一種であるチャネル保護型のトランジスタである。トランジスタ410は、絶縁層109上にゲート電極として機能できる電極246を有する。また、電極246上に絶縁層117を介して半導体層242を有する。電極246は配線121と同様の材料及び方法で形成することができる。
図19(A1)に例示するトランジスタ430は、トップゲート型のトランジスタの一種である。トランジスタ430は、絶縁層109の上に半導体層242を有し、半導体層242および絶縁層109上に、半導体層242の一部に接する電極244および半導体層242の一部に接する電極249を有し、半導体層242、電極244、および電極249上に絶縁層117を有し、絶縁層117上に電極246を有する。
図20に例示するトランジスタ450は、半導体層242bの上面及び側面が半導体層242cに覆われた構造を有する。図20(A)はトランジスタ450の上面図である。図20(B)は、図20(A)中のX1−X2の一点鎖線で示した部位の断面図(チャネル長方向の断面図)である。図20(C)は、図20(A)中のY1−Y2の一点鎖線で示した部位の断面図(チャネル幅方向の断面図)である。
本実施の形態では、本発明の一態様に係る撮像装置を用いた電子機器の一例について説明する。
101 基板
102 絶縁層
103 絶縁層
104 絶縁層
105 絶縁層
106 コンタクトプラグ
107 絶縁層
108 絶縁層
109 絶縁層
110 画素部
111 画素
112 画素駆動回路
113 画素
115 絶縁層
116 絶縁層
117 絶縁層
118 絶縁層
119 絶縁層
121 配線
122 配線
123 配線
124 配線
125 配線
126 配線
127 配線
128 配線
129 配線
131 トランジスタ
132 トランジスタ
133 トランジスタ
134 トランジスタ
135 容量素子
136 光電変換素子
137 配線
141 配線
142 配線
143 配線
144 配線
145 配線
151 ノード
152 ノード
177 絶縁層
205 絶縁層
209 絶縁層
212 電極
213 電極
214 層
217 絶縁層
221 p型半導体
222 i型半導体
223 n型半導体
224 開口
225 開口
241 トランジスタ
242 半導体層
243 電極
244 電極
245 電極
246 電極
249 電極
251 画素領域
252 周辺回路領域
254 ノード
255 不純物元素
256 ノード
257 容量素子
260 回路
261 信号処理回路
262 列駆動回路
263 出力回路
264 回路
266 配線
267 配線
268 配線
269 配線
270 回路
273 電極
277 絶縁層
280 回路
281 トランジスタ
282 トランジスタ
283 i型半導体
284 低濃度p型不純物領域
285 p型半導体
286 絶縁層
287 電極
288 側壁
289 トランジスタ
290 回路
291 フォトダイオード
292 トランジスタ
293 トランジスタ
294 低濃度n型不純物領域
295 n型半導体
382 Ec
386 Ec
390 トラップ準位
410 トランジスタ
411 トランジスタ
420 トランジスタ
421 トランジスタ
430 トランジスタ
431 トランジスタ
440 トランジスタ
441 トランジスタ
450 トランジスタ
451 トランジスタ
452 トランジスタ
600 レンズ
602 フィルタ
604 配線層
660 光
901 筐体
902 筐体
903 表示部
904 表示部
905 マイク
906 スピーカー
907 操作キー
908 スタイラス
909 カメラ
911 筐体
912 表示部
919 カメラ
921 筐体
922 シャッターボタン
923 マイク
925 レンズ
927 発光部
931 筐体
932 表示部
933 リストバンド
939 カメラ
941 筐体
942 筐体
943 表示部
944 操作キー
945 レンズ
946 接続部
951 筐体
952 表示部
954 スピーカー
955 ボタン
956 入出力端子
957 マイク
959 カメラ
1800 シフトレジスタ回路
1810 シフトレジスタ回路
1900 バッファ回路
1910 バッファ回路
2100 アナログスイッチ回路
2110 垂直出力線
2200 出力線
108c 半導体層
111B 画素
111G 画素
111R 画素
242a 半導体層
242b 半導体層
242c 半導体層
243a 電極
243b 電極
264a コンパレータ
264b カウンタ回路
272c 半導体層
383a Ec
383b Ec
383c Ec
602B フィルタ
602G フィルタ
602R フィルタ
Claims (5)
- 光電変換素子と、第1乃至第4のトランジスタと、容量素子と、第1乃至第7の配線と、を有し、
前記光電変換素子は、n型半導体と、i型半導体と、p型半導体と、を有し、
前記p型半導体は、平面視において櫛歯型の形状を有し、
前記n型半導体は、平面視において櫛歯型の形状を有し、
前記n型半導体と前記p型半導体は、前記i型半導体を挟んで噛み合うように配置され、
前記第1の配線は、前記n型半導体または前記p型半導体の一方と電気的に接続され、
前記n型半導体または前記p型半導体の他方は、前記第1のトランジスタのソースまたはドレインの一方と電気的に接続され、
前記第1のトランジスタのゲートは前記第2の配線と電気的に接続され、
前記第1のトランジスタのソースまたはドレインの他方は第1のノードと電気的に接続され、
前記第2のトランジスタのソースまたはドレインの一方は前記第3の配線と電気的に接続され、
前記第2のトランジスタのソースまたはドレインの他方は前記第1のノードと電気的に接続され、
前記第2のトランジスタのゲートは前記第4の配線と電気的に接続され、
前記容量素子の一方の電極は前記第1のノードと電気的に接続され、
前記容量素子の他方の電極は前記第1の配線と電気的に接続され、
前記第3のトランジスタのゲートは前記第1のノードと電気的に接続され、
前記第3のトランジスタのソースまたはドレインの一方は前記第5の配線と電気的に接続され、
前記第3のトランジスタのソースまたはドレインの他方は、前記第4のトランジスタのソースまたはドレインの一方と電気的に接続され、
前記第4のトランジスタのソースまたはドレインの他方は、前記第6の配線と電気的に接続され、
前記第4のトランジスタのゲートは前記第7の配線と電気的に接続され、
前記n型半導体、前記p型半導体、及び、前記i型半導体は絶縁層の上面に接し、
前記n型半導体と前記p型半導体は、それぞれ第1凸部と第2凸部を有し、
前記n型半導体と前記p型半導体は、前記n型半導体の前記第1凸部が前記p型半導体の前記第1凸部と前記第2凸部の間に位置し、かつ、前記p型半導体の前記第2凸部が前記n型半導体の前記第1凸部と前記第2凸部の間に位置するように、噛み合うように配置され、
前記第2の配線、前記第4の配線、及び、前記第7の配線のうち一の配線は、前記n型半導体の前記第1凸部及び前記p型半導体の前記第2凸部のうち一の凸部が延びている方向に沿って、かつ、前記一の凸部と重なるように延びている撮像装置。 - 請求項1において、
前記一の配線の幅は、前記一の凸部の幅より大きくない撮像装置。 - 請求項1または請求項2において、
前記n型半導体及び前記p型半導体の一方は前記i型半導体に囲まれていて、前記i型半導体は前記n型半導体及び前記p型半導体の他方に囲まれている撮像装置。 - 光電変換素子と、第1乃至第4のトランジスタと、容量素子と、第1乃至第7の配線と、を有し、
前記光電変換素子は、n型半導体と、i型半導体と、p型半導体と、を有し、
前記p型半導体は、平面視において櫛歯型の形状を有し、
前記n型半導体は、平面視において櫛歯型の形状を有し、
前記n型半導体と前記p型半導体は、前記i型半導体を挟んで噛み合うように配置され、
前記第1の配線は、前記n型半導体または前記p型半導体の一方と電気的に接続され、
前記n型半導体または前記p型半導体の他方は、前記第1のトランジスタのソースまたはドレインの一方と電気的に接続され、
前記第1のトランジスタのゲートは前記第2の配線と電気的に接続され、
前記第1のトランジスタのソースまたはドレインの他方は第1のノードと電気的に接続され、
前記第2のトランジスタのソースまたはドレインの一方は前記第3の配線と電気的に接続され、
前記第2のトランジスタのソースまたはドレインの他方は前記第1のノードと電気的に接続され、
前記第2のトランジスタのゲートは前記第4の配線と電気的に接続され、
前記容量素子の一方の電極は前記第1のノードと電気的に接続され、
前記容量素子の他方の電極は前記第1の配線と電気的に接続され、
前記第3のトランジスタのゲートは前記第1のノードと電気的に接続され、
前記第3のトランジスタのソースまたはドレインの一方は前記第5の配線と電気的に接続され、
前記第3のトランジスタのソースまたはドレインの他方は、前記第4のトランジスタのソースまたはドレインの一方と電気的に接続され、
前記第4のトランジスタのソースまたはドレインの他方は、前記第6の配線と電気的に接続され、
前記第4のトランジスタのゲートは前記第7の配線と電気的に接続され、
前記n型半導体及び前記p型半導体の一方は前記i型半導体に囲まれていて、前記i型半導体は前記n型半導体及び前記p型半導体の他方に囲まれている撮像装置。 - 請求項1乃至4のいずれか一において、
前記第1乃至前記第4のトランジスタのチャネル形成領域が有する半導体は、
前記i型半導体と異なる禁制帯幅を有する撮像装置。
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US20220077205A1 (en) | 2022-03-10 |
KR102359180B1 (ko) | 2022-02-08 |
KR20220100106A (ko) | 2022-07-14 |
US11908876B2 (en) | 2024-02-20 |
US20170092670A1 (en) | 2017-03-30 |
KR102419715B1 (ko) | 2022-07-13 |
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JP2020021955A (ja) | 2020-02-06 |
WO2015189732A1 (ja) | 2015-12-17 |
JP7274543B2 (ja) | 2023-05-16 |
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