JP6599556B2 - セラミックノーリード表面実装電子デバイス用の応力抑制インターポーザ - Google Patents
セラミックノーリード表面実装電子デバイス用の応力抑制インターポーザ Download PDFInfo
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- 230000001629 suppression Effects 0.000 title claims description 22
- 239000000919 ceramic Substances 0.000 title description 3
- 229910000679 solder Inorganic materials 0.000 claims description 139
- 239000000463 material Substances 0.000 claims description 104
- 230000005496 eutectics Effects 0.000 claims description 10
- 230000008018 melting Effects 0.000 claims description 10
- 238000002844 melting Methods 0.000 claims description 10
- 238000004891 communication Methods 0.000 claims description 6
- 230000002093 peripheral effect Effects 0.000 claims description 6
- 229910010293 ceramic material Inorganic materials 0.000 claims description 4
- 239000002184 metal Substances 0.000 claims description 4
- 229910052751 metal Inorganic materials 0.000 claims description 4
- 238000007747 plating Methods 0.000 claims description 4
- 238000000034 method Methods 0.000 description 6
- 238000005476 soldering Methods 0.000 description 5
- 230000008569 process Effects 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 238000003491 array Methods 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 230000007246 mechanism Effects 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- WUUZKBJEUBFVMV-UHFFFAOYSA-N copper molybdenum Chemical compound [Cu].[Mo] WUUZKBJEUBFVMV-UHFFFAOYSA-N 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910016525 CuMo Inorganic materials 0.000 description 1
- 230000000712 assembly Effects 0.000 description 1
- 238000000429 assembly Methods 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000008602 contraction Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000005382 thermal cycling Methods 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
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Description
Claims (20)
- 第1及び第2の電子デバイスそれぞれの第1及び第2のはんだ材料間に配置可能な応力抑制インターポーザであって、
中心部と該中心部を取り囲む周辺部とを有するプレート素子であり、面積上限を持つ第1のキャビティを前記周辺部に画成し、且つ前記面積上限よりも高い面積下限を持つ第2のキャビティを前記中心部に画成するように形成されているプレート素子と、
前記第1及び第2のはんだ材料と電気的に連通するように、それぞれ、前記第2のキャビティ内及び前記第1のキャビティ内に配置可能な第3及び第4のはんだ材料と
を有し、
前記第3のはんだ材料は、少なくとも前記第2及び第4のはんだ材料よりも柔軟であり且つ高い融点を持つ、
応力抑制インターポーザ。 - 前記プレート素子は、セラミック材料と、前記第1及び第2のキャビティの側壁上に形成された金属めっきとを有する、請求項1に記載の応力抑制インターポーザ。
- 前記プレート素子は、前記第1の電子デバイスのフットプリントと同等又はそれより僅かに大きいサイズのフットプリントを有する、請求項1に記載の応力抑制インターポーザ。
- 前記第1のはんだ材料は、共晶はんだ及び高鉛含有はんだのうちの一方を有し、前記第2及び第4のはんだ材料は共晶はんだを有し、前記第3のはんだ材料は高鉛含有はんだを有する、請求項1に記載の応力抑制インターポーザ。
- 前記第1のはんだ材料は、63Sn/37Pbはんだ及び90Pb/10Snはんだのうちの一方を有し、前記第2及び第4のはんだ材料は63Sn/37Pbはんだを有し、前記第3のはんだ材料は90Pb/10Snはんだを有する、請求項1に記載の応力抑制インターポーザ。
- 第1及び第2の電子デバイス間に配置可能な応力抑制インターポーザアセンブリであって、
前記第1及び第2の電子デバイスの各々の第1の端子パッド及び第2の端子パッドに近接して配置可能な第1及び第2のはんだ材料と、
前記第1及び第2の電子デバイスの各々の前記第1の端子パッドにそれぞれ対応するように、面積上限を持つ第1のキャビティを周辺部に画成し、且つ、前記第1及び第2の電子デバイスの各々の前記第2の端子パッドにそれぞれ対応するように、前記面積上限よりも高い面積下限を持つ第2のキャビティを中心部に画成するように形成されているプレート素子と、
前記第1及び第2のはんだ材料と電気的に連通するように、それぞれ、前記第2のキャビティ内及び前記第1のキャビティ内に配置可能な第3及び第4のはんだ材料と
を有し、
前記第3のはんだ材料は、少なくとも前記第2及び第4のはんだ材料よりも柔軟であり且つ高い融点を持つ、
応力抑制インターポーザアセンブリ。 - 前記プレート素子は、セラミック材料と、前記第1及び第2のキャビティの側壁上に形成された金属めっきとを有する、請求項6に記載の応力抑制インターポーザアセンブリ。
- 前記プレート素子は、前記第1の電子デバイスのフットプリントと同等又はそれより僅かに大きいサイズのフットプリントを有する、請求項6に記載の応力抑制インターポーザアセンブリ。
- 前記第1及び第2の電子デバイスの各々の少なくとも前記第1の端子パッドは、それぞれ異なるサイズの端子パッドを有する、請求項8に記載の応力抑制インターポーザアセンブリ。
- 前記第1のはんだ材料は、共晶はんだ及び高鉛含有はんだのうちの一方を有し、前記第2及び第4のはんだ材料は共晶はんだを有し、前記第3のはんだ材料は高鉛含有はんだを有する、請求項6に記載の応力抑制インターポーザアセンブリ。
- 前記第1のはんだ材料は、63Sn/37Pbはんだ及び90Pb/10Snはんだのうちの一方を有し、前記第2及び第4のはんだ材料は63Sn/37Pbはんだを有し、前記第3のはんだ材料は90Pb/10Snはんだを有する、請求項6に記載の応力抑制インターポーザアセンブリ。
- 第1の端子パッド及び第2の端子パッドを有する第1の電子デバイスと、
第1の端子パッド及び第2の端子パッドを有する第2の電子デバイスと、
前記第1及び第2の電子デバイスの各々の前記第1の端子パッド及び前記第2の端子パッドに近接して配置可能な第1及び第2のはんだ材料と、
前記第1及び第2の電子デバイスの各々の前記第1の端子パッドにそれぞれ対応するように、面積上限を持つ第1のキャビティを周辺部に画成し、且つ、前記第1及び第2の電子デバイスの各々の前記第2の端子パッドにそれぞれ対応するように、前記面積上限よりも高い面積下限を持つ第2のキャビティを中心部に画成するように形成されているプレート素子と、
前記第1及び第2のはんだ材料と電気的に連通するように、それぞれ、前記第2のキャビティ内及び前記第1のキャビティ内に配置可能な第3及び第4のはんだ材料と
を有し、
前記第3のはんだ材料は、少なくとも前記第2及び第4のはんだ材料よりも柔軟であり且つ高い融点を持つ、
電子機器。 - 前記プレート素子は、セラミック材料と、前記第1及び第2のキャビティの側壁上に形成された金属めっきとを有する、請求項12に記載の電子機器。
- 前記第1の電子デバイスは、クワッドフラットパックノーリード(CQFN)の表面実装デバイス(SMD)を有し、前記第2の電子デバイスはプリント配線板(PWB)を有する、請求項12に記載の電子機器。
- 前記プレート素子は、前記PWB上に前記CQFNのSMDのフットプリントと同等又はそれより僅かに大きいサイズのフットプリントを有する、請求項14に記載の電子機器。
- 前記第1及び第2の電子デバイスの各々の前記第1の端子パッドは、それぞれ異なるサイズの端子パッドを有し、前記第1のキャビティは、対応する異なるサイズのキャビティを有する、請求項12に記載の電子機器。
- 前記第1及び第2の電子デバイスの各々の前記第2の端子パッドは、それぞれ単一の大きい端子パッドを有し、前記第2のキャビティは、単一の対応する大きいキャビティを有する、請求項12に記載の電子機器。
- 前記第1のキャビティは、複数列のアレイにて配列され、前記第2のキャビティは、前記複数列のアレイの中に包囲された1つ以上の大きいキャビティを有する、請求項12に記載の電子機器。
- 前記第1のはんだ材料は、共晶はんだ及び高鉛含有はんだのうちの一方を有し、前記第2及び第4のはんだ材料は共晶はんだを有し、前記第3のはんだ材料は高鉛含有はんだを有する、請求項12に記載の電子機器。
- 前記第1のはんだ材料は、63Sn/37Pbはんだ及び90Pb/10Snはんだのうちの一方を有し、前記第2及び第4のはんだ材料は63Sn/37Pbはんだを有し、前記第3のはんだ材料は90Pb/10Snはんだを有する、請求項12に記載の電子機器。
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US14/947,574 US9648729B1 (en) | 2015-11-20 | 2015-11-20 | Stress reduction interposer for ceramic no-lead surface mount electronic device |
US14/947,574 | 2015-11-20 | ||
PCT/US2016/062700 WO2017087762A1 (en) | 2015-11-20 | 2016-11-18 | Stress reduction interposer for ceramic no-lead surface mount electronic device |
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JP6599556B2 true JP6599556B2 (ja) | 2019-10-30 |
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US (1) | US9648729B1 (ja) |
EP (1) | EP3378290A1 (ja) |
JP (1) | JP6599556B2 (ja) |
KR (1) | KR20180089407A (ja) |
CA (1) | CA3005349A1 (ja) |
IL (1) | IL258859B (ja) |
MX (1) | MX2018005616A (ja) |
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US11508669B2 (en) | 2019-08-30 | 2022-11-22 | Nxp B.V. | Method and apparatus for improved circuit structure thermal reliability on printed circuit board materials |
US11532593B2 (en) | 2020-09-30 | 2022-12-20 | Taiwan Semiconductor Manufacturing Co., Ltd. | Embedded stress absorber in package |
CN116779584B (zh) * | 2023-08-21 | 2023-11-03 | 湖南大学 | 一种低芯片温度梯度的功率半导体模块封装结构及方法 |
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MY112145A (en) | 1994-07-11 | 2001-04-30 | Ibm | Direct attachment of heat sink attached directly to flip chip using flexible epoxy |
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JPH11163225A (ja) * | 1997-11-25 | 1999-06-18 | Ngk Spark Plug Co Ltd | 中継基板、ic実装基板と中継基板との接続体、ic実装基板と中継基板と取付基板とからなる構造体 |
USD423532S (en) | 1998-10-21 | 2000-04-25 | Ngk Spark Plug Co., Ltd. | Solder column interposer |
JP3792445B2 (ja) | 1999-03-30 | 2006-07-05 | 日本特殊陶業株式会社 | コンデンサ付属配線基板 |
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TWI245402B (en) | 2002-01-07 | 2005-12-11 | Megic Corp | Rod soldering structure and manufacturing process thereof |
US7245022B2 (en) | 2003-11-25 | 2007-07-17 | International Business Machines Corporation | Semiconductor module with improved interposer structure and method for forming the same |
EP1677349A4 (en) | 2004-02-24 | 2010-12-01 | Ibiden Co Ltd | SUBSTRATE FOR MOUNTING A SEMICONDUCTOR |
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WO2007080863A1 (ja) | 2006-01-16 | 2007-07-19 | Nec Corporation | 半導体装置、該半導体装置を実装するプリント配線基板、及びそれらの接続構造 |
DE602006021193D1 (de) | 2006-10-27 | 2011-05-19 | Agie Charmilles S A | Leiterplatteneinheit und Verfahren zur Herstellung dazu |
JP2008283043A (ja) * | 2007-05-11 | 2008-11-20 | Toppan Printing Co Ltd | 多層配線板およびその製造方法 |
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US9648729B1 (en) | 2017-05-09 |
TW201729374A (zh) | 2017-08-16 |
WO2017087762A1 (en) | 2017-05-26 |
KR20180089407A (ko) | 2018-08-08 |
JP2018535551A (ja) | 2018-11-29 |
TWI705542B (zh) | 2020-09-21 |
IL258859A (en) | 2018-06-28 |
EP3378290A1 (en) | 2018-09-26 |
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US20170150596A1 (en) | 2017-05-25 |
MX2018005616A (es) | 2018-08-15 |
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