JP6536814B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP6536814B2 JP6536814B2 JP2015185934A JP2015185934A JP6536814B2 JP 6536814 B2 JP6536814 B2 JP 6536814B2 JP 2015185934 A JP2015185934 A JP 2015185934A JP 2015185934 A JP2015185934 A JP 2015185934A JP 6536814 B2 JP6536814 B2 JP 6536814B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- electrode
- silicon glass
- semiconductor substrate
- electrodes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 title claims description 55
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 38
- 229910052710 silicon Inorganic materials 0.000 claims description 38
- 239000010703 silicon Substances 0.000 claims description 38
- 239000011521 glass Substances 0.000 claims description 37
- 239000000758 substrate Substances 0.000 claims description 31
- 239000011229 interlayer Substances 0.000 claims description 30
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 18
- 229910052698 phosphorus Inorganic materials 0.000 claims description 18
- 239000011574 phosphorus Substances 0.000 claims description 18
- 239000010410 layer Substances 0.000 description 20
- 239000005380 borophosphosilicate glass Substances 0.000 description 17
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 11
- 229910052796 boron Inorganic materials 0.000 description 11
- 230000007797 corrosion Effects 0.000 description 3
- 238000005260 corrosion Methods 0.000 description 3
- 239000012535 impurity Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000008595 infiltration Effects 0.000 description 1
- 238000001764 infiltration Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Description
本発明の半導体装置は、
半導体基体と
前記半導体基体上の層間膜と、
前記層間膜上の一部の領域上の電極と、を備え、
前記層間膜は、
ノンドープのシリコンガラス膜と、
前記ノンドープのシリコンガラス膜上にリンを含むシリコンガラス膜と、
前記リンを含むシリコンガラス膜上にノンドープのシリコンガラス膜と、を含み、
活性領域を囲むエッジ領域上であって互いに離間した複数の電極を含み、
前記活性領域側の前記電極のうちの1つは、前記半導体基体の表面にある前記活性領域の第1の主電極と電気的に接続し、
前記半導体基体の端部側の前記電極の他の1つは、前記半導体基体の裏面にある第2の主電極と電気的に接続し、
前記層間膜は前記電極のうちの1つと前記電極の他の1つの上にあることを特徴とする。
エッジトレンチ102の外側には第1のリサーフ領域41と第1のリサーフ領域41から半導体基体の端部側へと延伸し、且つ第1のリサーフ領域41よりも深くまで延伸する第2のリサーフ領域42が形成されている。第2のリサーフ領域42の不純物濃度は1×1015〜1×1017[/cm3]であり、第1のリサーフ領域41よりも不純物濃度が低い。半導体基体2上には絶縁膜55を介して電極51、52、53、54が設けられており、電極51、52、53、54の内で最も半導体基体の端部側の電極51、52、53、54がコレクタ電極11と電気的に接続し、電極51、52、53、54の内で最も活性領域側の電極51、52、53、54がエミッタ電極10と電気的に接続されている。従って、コレクタ電極11とエミッタ電極10に電圧を印加すると、隣合う電極51、52、53、54間に容量が生じ、容量性のフィールドプレートとして機能する。電極51、52、53、54上には層間膜9が設けられている。ここで、半導体基体2の上面にリサーフ領域42が形成されている半導体基体2の領域上の少なくとも一部、さらにリサーフ領域42より外側の半導体基体2の領域上において、層間膜9はその上に電極10が形成されておらず、層間膜9の上面が露出している。
ボロンとリンを含むシリコンガラス(BPSG)膜の下にノンドープのシリコンガラス(NSG)膜が形成されている。この膜の厚みは0.4μm〜0.6μmであって、NSG膜は半導体装置の外部から侵入した水分がその下側の基板側へと侵入することを抑制する効果がある。
ボロンとリンを含むシリコンガラス(BPSG)膜の上にノンドープのシリコンガラス(NSG)膜が形成されている。この膜の厚みは0.4μm〜0.6μmである。
2 半導体基体
3 n−層
4 p―層
5 n+層
6 ゲート電極
7 P層
8 酸化膜
9 層間膜
10 エミッタ電極
11 コレクタ電極
12 補助電極
13 保護膜
Claims (2)
- 半導体基体と、
前記半導体基体上の層間膜と、
前記層間膜上の一部の領域上の電極と、を備え、
前記層間膜は、 ノンドープのシリコンガラス膜と、
前記ノンドープのシリコンガラス膜上にリンを含むシリコンガラス膜と、
前記リンを含むシリコンガラス膜上にノンドープのシリコンガラス膜と、 を含み、
活性領域を囲むエッジ領域上であって互いに離間した複数の電極を含み、
前記活性領域側の前記電極のうちの1つは、前記半導体基体の表面にある前記活性領域の第1の主電極と電気的に接続し、
前記半導体基体の端部側の前記電極の他の1つは、前記半導体基体の裏面にある第2の主電極と電気的に接続し、
前記層間膜は前記電極のうちの1つと前記電極の他の1つの上にあることを特徴とする半導体装置。 - 前記電極はAlを含む事を特徴とする請求項1の半導体装置。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2015185934A JP6536814B2 (ja) | 2015-09-18 | 2015-09-18 | 半導体装置 |
CN201510761493.5A CN106548922B (zh) | 2015-09-18 | 2015-11-10 | 半导体装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2015185934A JP6536814B2 (ja) | 2015-09-18 | 2015-09-18 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2017059785A JP2017059785A (ja) | 2017-03-23 |
JP6536814B2 true JP6536814B2 (ja) | 2019-07-03 |
Family
ID=58364843
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2015185934A Active JP6536814B2 (ja) | 2015-09-18 | 2015-09-18 | 半導体装置 |
Country Status (2)
Country | Link |
---|---|
JP (1) | JP6536814B2 (ja) |
CN (1) | CN106548922B (ja) |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS634646A (ja) * | 1986-06-24 | 1988-01-09 | Matsushita Electric Works Ltd | 半導体装置の製法 |
US5424570A (en) * | 1992-01-31 | 1995-06-13 | Sgs-Thomson Microelectronics, Inc. | Contact structure for improving photoresist adhesion on a dielectric layer |
EP0660393B1 (en) * | 1993-12-23 | 2000-05-10 | STMicroelectronics, Inc. | Method and dielectric structure for facilitating overetching of metal without damage to inter-level dielectric |
JPH09293717A (ja) * | 1996-03-01 | 1997-11-11 | Nippon Telegr & Teleph Corp <Ntt> | 半導体装置およびその作製方法 |
JPH11238799A (ja) * | 1998-02-24 | 1999-08-31 | Nec Corp | 半導体装置およびその製造方法 |
JP2002222859A (ja) * | 2001-01-26 | 2002-08-09 | Sanken Electric Co Ltd | 半導体素子のコンタクト電極形成方法 |
JP2007180365A (ja) * | 2005-12-28 | 2007-07-12 | Nec Electronics Corp | 半導体装置及びその製造方法 |
CN101452909B (zh) * | 2007-11-30 | 2010-08-11 | 上海华虹Nec电子有限公司 | 接触孔层间膜上刻蚀接触孔的方法 |
-
2015
- 2015-09-18 JP JP2015185934A patent/JP6536814B2/ja active Active
- 2015-11-10 CN CN201510761493.5A patent/CN106548922B/zh active Active
Also Published As
Publication number | Publication date |
---|---|
CN106548922B (zh) | 2020-01-14 |
CN106548922A (zh) | 2017-03-29 |
JP2017059785A (ja) | 2017-03-23 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5612256B2 (ja) | 半導体装置 | |
JP5315638B2 (ja) | 半導体装置 | |
JP6805620B2 (ja) | 半導体装置 | |
TW201611275A (zh) | 半導體裝置 | |
US9825158B2 (en) | Insulated gate bipolar transistor | |
JP2013115225A (ja) | 電力用半導体装置およびその製造方法 | |
JP5537359B2 (ja) | 半導体装置 | |
JP2013201237A (ja) | 半導体装置 | |
JP6283468B2 (ja) | 逆導通igbt | |
JP2013069866A (ja) | 半導体装置 | |
JP6573107B2 (ja) | 半導体装置 | |
JP6624370B2 (ja) | 半導体装置 | |
JP6918736B2 (ja) | 半導体装置 | |
JP2022108230A (ja) | 半導体装置 | |
JP6758592B2 (ja) | 半導体装置 | |
JP6536814B2 (ja) | 半導体装置 | |
JP2018082207A5 (ja) | ||
JP5465837B2 (ja) | 半導体装置 | |
JP6458994B2 (ja) | 半導体装置 | |
JP6760134B2 (ja) | 半導体装置 | |
JP7201004B2 (ja) | 半導体装置 | |
KR101721181B1 (ko) | 전력 반도체 소자 | |
JP6513932B2 (ja) | 半導体装置 | |
JP7201005B2 (ja) | 半導体装置 | |
KR20160038692A (ko) | 반도체 장치 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20180629 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20190215 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20190220 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20190326 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20190508 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20190521 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 6536814 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |