JP6505521B2 - 配線基板、半導体装置及び配線基板の製造方法 - Google Patents

配線基板、半導体装置及び配線基板の製造方法 Download PDF

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Publication number
JP6505521B2
JP6505521B2 JP2015128756A JP2015128756A JP6505521B2 JP 6505521 B2 JP6505521 B2 JP 6505521B2 JP 2015128756 A JP2015128756 A JP 2015128756A JP 2015128756 A JP2015128756 A JP 2015128756A JP 6505521 B2 JP6505521 B2 JP 6505521B2
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Japan
Prior art keywords
reinforcing
insulating layer
pattern
wiring
reinforcement
Prior art date
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Application number
JP2015128756A
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English (en)
Japanese (ja)
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JP2017017048A5 (enExample
JP2017017048A (ja
Inventor
幸太郎 小谷
幸太郎 小谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
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Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2015128756A priority Critical patent/JP6505521B2/ja
Priority to US15/183,273 priority patent/US9818702B2/en
Publication of JP2017017048A publication Critical patent/JP2017017048A/ja
Publication of JP2017017048A5 publication Critical patent/JP2017017048A5/ja
Application granted granted Critical
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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices
    • H10W42/121—Arrangements for protection of devices protecting against mechanical damage
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H10W70/635—Through-vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/0198—Manufacture or treatment batch processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Structure Of Printed Boards (AREA)
JP2015128756A 2015-06-26 2015-06-26 配線基板、半導体装置及び配線基板の製造方法 Active JP6505521B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2015128756A JP6505521B2 (ja) 2015-06-26 2015-06-26 配線基板、半導体装置及び配線基板の製造方法
US15/183,273 US9818702B2 (en) 2015-06-26 2016-06-15 Wiring substrate and semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2015128756A JP6505521B2 (ja) 2015-06-26 2015-06-26 配線基板、半導体装置及び配線基板の製造方法

Publications (3)

Publication Number Publication Date
JP2017017048A JP2017017048A (ja) 2017-01-19
JP2017017048A5 JP2017017048A5 (enExample) 2018-01-25
JP6505521B2 true JP6505521B2 (ja) 2019-04-24

Family

ID=57601309

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2015128756A Active JP6505521B2 (ja) 2015-06-26 2015-06-26 配線基板、半導体装置及び配線基板の製造方法

Country Status (2)

Country Link
US (1) US9818702B2 (enExample)
JP (1) JP6505521B2 (enExample)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6332330B2 (ja) * 2016-05-20 2018-05-30 日亜化学工業株式会社 配線基体の製造方法及びそれを用いた発光装置の製造方法並びに配線基体及びそれを用いた発光装置。
US11545455B2 (en) 2019-05-28 2023-01-03 Apple Inc. Semiconductor packaging substrate fine pitch metal bump and reinforcement structures
DE102019215471B4 (de) * 2019-10-09 2022-05-25 Vitesco Technologies GmbH Elektronisches Bauteil mit einer Kontaktieranordnung und Verfahren zur Herstellung eines elektronischen Bauteils
US12394720B2 (en) * 2022-08-16 2025-08-19 Taiwan Semiconductor Manufacturing Company Limited Semiconductor package including reinforcement structure and methods of forming the same

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002076634A (ja) * 2000-08-25 2002-03-15 Kyocera Corp 配線基板およびこれを用いた電子部品モジュール
KR20090057820A (ko) * 2007-12-03 2009-06-08 삼성전기주식회사 인쇄회로기판 및 그 제조방법
JP4993739B2 (ja) * 2007-12-06 2012-08-08 新光電気工業株式会社 配線基板、その製造方法及び電子部品装置
KR101051551B1 (ko) * 2009-10-30 2011-07-22 삼성전기주식회사 요철 패턴을 갖는 비아 패드를 포함하는 인쇄회로기판 및 그 제조방법
JP2014075515A (ja) * 2012-10-05 2014-04-24 Shinko Electric Ind Co Ltd 配線基板及び配線基板の製造方法

Also Published As

Publication number Publication date
US20160379938A1 (en) 2016-12-29
US9818702B2 (en) 2017-11-14
JP2017017048A (ja) 2017-01-19

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