JP6498787B2 - 半導体装置 - Google Patents
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- JP6498787B2 JP6498787B2 JP2017558873A JP2017558873A JP6498787B2 JP 6498787 B2 JP6498787 B2 JP 6498787B2 JP 2017558873 A JP2017558873 A JP 2017558873A JP 2017558873 A JP2017558873 A JP 2017558873A JP 6498787 B2 JP6498787 B2 JP 6498787B2
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Description
図1は、半導体装置の基本構造(発明の理解に必要となる最小限の構成要素のみ)を模式的に示す縦断面図である。本図の半導体装置10は、出力端子OUTに接続されたn型半導体基板11と、n型半導体基板11に形成されたp型ウェル12と、p型ウェル12に形成されて制御端子INに接続されたn型半導体領域13と、p型ウェル12と接地端子GNDとの間に接続された電位分離部14と、を有する。
図2は、ローサイドスイッチICへの適用例を示すアプリケーション図である。本図に例示した電子機器1は、半導体装置100と、これに外付けされるマイコンM1、負荷Z1、及び、抵抗R1を有する。
図8は、車両Xの一構成例を示す外観図である。本構成例の車両Xは、不図示のバッテリと、バッテリから電力の供給を受けて動作する種々の電子機器X11〜X18と、を搭載している。なお、本図における電子機器X11〜X18の搭載位置については、図示の便宜上、実際とは異なる場合がある。
なお、本明細書中に開示されている種々の技術的特徴は、上記実施形態のほか、その技術的創作の主旨を逸脱しない範囲で種々の変更を加えることが可能である。すなわち、上記実施形態は、全ての点で例示であって制限的なものではないと考えられるべきであり、本発明の技術的範囲は、上記実施形態の説明ではなく、特許請求の範囲によって示されるものであり、特許請求の範囲と均等の意味及び範囲内に属する全ての変更が含まれると理解されるべきである。
10 半導体装置
11 n型半導体基板
12 p型ウェル
13 n型半導体領域
14 電位分離部
14a p型ウェル
14b n型半導体領域
14c 抵抗
100 半導体装置
101 n型半導体基板
101a n型基板層
101b n型エピタキシャル成長層
101c 基板電極
110 出力トランジスタ
111 p型ウェル
112 トレンチゲート
113 高濃度n型半導体領域
114 高濃度p型半導体領域
120 制御部
121 p型ウェル
122 低濃度n型半導体領域
123 低濃度p型半導体領域
124、127 高濃度p型半導体領域
125、126 高濃度n型半導体領域
130 電位分離部
131 p型ウェル
132 低濃度n型半導体領域
133 高濃度p型半導体領域
134 高濃度n型半導体領域
135 抵抗
136 ダミーPMOSFET
136S 高濃度p型半導体領域(ソース)
136D 高濃度p型半導体領域(ドレイン)
136G ゲート電極(ゲート)
210 PMOSFET
210S 高濃度p型半導体領域(ソース)
210D 高濃度p型半導体領域(ドレイン)
210G ゲート電極(ゲート)
220 NMOSFET
220S 高濃度n型半導体領域(ソース)
220D 高濃度n型半導体領域(ドレイン)
220G ゲート電極(ゲート)
230 コンパレータ
240、250 抵抗
IN 制御端子
OUT 出力端子(負荷接続端子)
GND 接地端子
EX 抵抗接続端子
Q1、Q2、Q11、Q12 寄生トランジスタ
M1 マイコン
R1 抵抗
Z1 負荷
X 車両
X11〜X18 電子機器
Claims (11)
- 出力端子に接続されたn型半導体基板と、
前記n型半導体基板に形成された第1p型ウェルと、
前記第1p型ウェルに形成されて制御端子に接続された第1n型半導体領域と、
前記第1p型ウェルと接地端子との間に接続された電位分離部と、
を有し、
前記電位分離部は、前記出力端子が前記接地端子よりも高電位であるときには前記第1p型ウェルと前記接地端子を同電位とし、前記出力端子が前記接地端子よりも低電位であるときには前記第1p型ウェルと前記出力端子を同電位とする、
半導体装置であって、
前記電位分離部は、
前記n型半導体基板に形成されて前記接地端子に接続された第2p型ウェルと、
前記第2p型ウェルに形成された第2n型半導体領域と、
を有し、
前記第1p型ウェルと前記第2n型半導体領域は、共通の抵抗を介して前記接地端子に接続されている、
ことを特徴とする半導体装置。 - 出力端子に接続されたn型半導体基板と、
前記n型半導体基板に形成された第1p型ウェルと、
前記第1p型ウェルに形成されて制御端子に接続された第1n型半導体領域と、
前記第1p型ウェルと接地端子との間に接続された電位分離部と、
を有し、
前記電位分離部は、
前記n型半導体基板に形成されて前記接地端子に接続された第2p型ウェルと、
前記第2p型ウェルに形成された第2n型半導体領域と、
を有し、
前記第1p型ウェルと前記第2n型半導体領域は、共通の抵抗を介して前記接地端子に接続されている、
ことを特徴とする半導体装置。 - 前記抵抗を外付けするための外部端子をさらに有することを特徴とする請求項1または請求項2に記載の半導体装置。
- 前記第2n型半導体領域は、前記第2p型ウェルに形成されたダミーPMOSFETのバックゲートに相当することを特徴とする請求項1〜請求項3のいずれか一項に記載の半導体装置。
- 前記出力端子と前記接地端子との間に接続されており前記制御端子から入力される制御電圧に応じてオン/オフされる縦型構造の出力トランジスタと、
前記制御電圧を電源として動作する制御部と、
をさらに有し、
前記第1p型ウェルと前記第1n型半導体領域は、いずれも前記制御部の構成要素であることを特徴とする請求項1〜請求項4のいずれか一項に記載の半導体装置。 - 前記制御部は、
前記制御端子と前記出力トランジスタのゲートとの間に接続されたPMOSFETと、
前記出力トランジスタのゲートと前記接地端子との間に接続されたNMOSFETと、
を含み、
前記第1p型ウェルは、前記NMOSFETのバックゲートに相当し、
前記第1n型半導体領域は、前記PMOSFETのバックゲートに相当する、
ことを特徴とする請求項5に記載の半導体装置。 - 出力端子に接続されたn型半導体基板と、
前記n型半導体基板に形成された第1p型ウェルと、
前記第1p型ウェルに形成されて制御端子に接続された第1n型半導体領域と、
前記第1p型ウェルと接地端子との間に接続された電位分離部と、
を有し、
前記電位分離部は、前記出力端子が前記接地端子よりも高電位であるときには前記第1p型ウェルと前記接地端子を同電位とし、前記出力端子が前記接地端子よりも低電位であるときには前記第1p型ウェルと前記出力端子を同電位とする、
半導体装置であって、
前記出力端子と前記接地端子との間に接続されており前記制御端子から入力される制御電圧に応じてオン/オフされる縦型構造の出力トランジスタと、
前記制御電圧を電源として動作する制御部と、
をさらに有し、
前記第1p型ウェルと前記第1n型半導体領域は、いずれも前記制御部の構成要素であって、
前記制御部は、
前記制御端子と前記出力トランジスタのゲートとの間に接続されたPMOSFETと、
前記出力トランジスタのゲートと前記接地端子との間に接続されたNMOSFETと、
を含み、
前記第1p型ウェルは、前記NMOSFETのバックゲートに相当し、
前記第1n型半導体領域は、前記PMOSFETのバックゲートに相当する、
ことを特徴とする半導体装置。 - 請求項1〜請求項7のいずれか一項に記載の半導体装置と、
前記半導体装置の制御端子に制御電圧を供給するマイコンと、
前記半導体装置の出力端子に外付けされる負荷と、
を有することを特徴とする電子機器。 - 前記負荷は、誘導性負荷であることを特徴とする請求項8に記載の電子機器。
- 前記半導体装置は、ローサイドスイッチIC、スイッチング電源IC、または、モータドライバICであることを特徴とする請求項9に記載の電子機器。
- 請求項10に記載の電子機器と、
前記電子機器に電力を供給するバッテリと、
を有することを特徴とする車両。
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