JP6489660B2 - 印刷回路基板製造方法 - Google Patents
印刷回路基板製造方法 Download PDFInfo
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- JP6489660B2 JP6489660B2 JP2017046029A JP2017046029A JP6489660B2 JP 6489660 B2 JP6489660 B2 JP 6489660B2 JP 2017046029 A JP2017046029 A JP 2017046029A JP 2017046029 A JP2017046029 A JP 2017046029A JP 6489660 B2 JP6489660 B2 JP 6489660B2
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- 238000004519 manufacturing process Methods 0.000 title claims description 42
- 238000000034 method Methods 0.000 claims description 24
- 229910000679 solder Inorganic materials 0.000 claims description 20
- 239000000758 substrate Substances 0.000 claims description 8
- 239000011521 glass Substances 0.000 claims description 3
- 230000008878 coupling Effects 0.000 claims 4
- 238000010168 coupling process Methods 0.000 claims 4
- 238000005859 coupling reaction Methods 0.000 claims 4
- 239000010410 layer Substances 0.000 description 178
- 238000010586 diagram Methods 0.000 description 23
- 239000012790 adhesive layer Substances 0.000 description 8
- 238000007689 inspection Methods 0.000 description 8
- 230000003014 reinforcing effect Effects 0.000 description 7
- 239000002390 adhesive tape Substances 0.000 description 5
- 230000002159 abnormal effect Effects 0.000 description 4
- 239000000654 additive Substances 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 230000001681 protective effect Effects 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000005856 abnormality Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4623—Manufacturing multilayer circuits by laminating two or more circuit boards the circuit boards having internal via connections between two or more circuit layers before lamination, e.g. double-sided circuit boards
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/007—Manufacture or processing of a substrate for a printed circuit board supported by a temporary or sacrificial carrier
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/429—Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81192—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15192—Resurf arrangement of the internal vias
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15313—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a land array, e.g. LGA
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Ceramic Engineering (AREA)
- Inorganic Chemistry (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Description
図1は本発明の一実施例に係る印刷回路基板を示した図面である。図1を参照すれば、本発明の一実施例に係る印刷回路基板は高密度のブリッジ回路層100、低密度回路層150およびソルダーバンプ180/ビア280を含む。
図3〜図14は本発明の一実施例に係る印刷回路基板の製造方法を示した図面である。本発明の一実施例に係る印刷回路基板の製造方法は、補強部材152を具備した低密度回路層150に高密度のブリッジ回路層100をソルダーバンプ180を利用して結合し、内蔵させる方法を例示する。
5 第1キャリア
6 第2キャリア
7 第3キャリア
100、200 ブリッジ回路層
110、210 ブリッジ回路
130 検査回路パターン
150、250 低密度回路層
160、260 低密度回路
170、270 外層回路
180 ソルダーバンプ
280 ビア
Claims (10)
- 低粗度の第1キャリアに高密度のブリッジ(bridge)回路を具備したブリッジ回路層を形成する段階;
前記ブリッジ回路層に仮接合される第2キャリアを接合し、前記第1キャリアを分離する段階;および
低密度回路を具備した低密度回路層に前記ブリッジ回路層を結合し埋め立てる段階を含む、印刷回路基板製造方法。 - 前記第1キャリアはガラス基板を含む、請求項1に記載の印刷回路基板製造方法。
- 前記ブリッジ回路層を結合し埋め立てる段階は、
前記低密度回路を具備した低密度回路層を形成する段階;
前記低密度回路層に前記ブリッジ回路層を結合させて電気的に連結する段階;
前記第2キャリアを分離させる段階;および
前記ブリッジ回路層を埋め立てる段階を含む、請求項1または請求項2に記載の印刷回路基板製造方法。 - 前記低密度回路層と前記ブリッジ回路層はソルダーバンプを通じて連結される、請求項3に記載の印刷回路基板製造方法。
- 前記ブリッジ回路と連結された外層回路を形成する段階をさらに含む、請求項3または請求項4に記載の印刷回路基板製造方法。
- 前記ブリッジ回路層を結合し埋め立てる段階は、
第3キャリアに前記ブリッジ回路層を装着させる段階;
前記第2キャリアを分離させる段階;
前記第3キャリアに前記ブリッジ回路層を埋め立てる前記低密度回路層をビルドアップ(build−up)する段階;および
前記第3キャリアを分離する段階を含む、請求項1〜請求項5のいずれか一項に記載の印刷回路基板製造方法。 - 前記ビルドアップする段階は、
前記ブリッジ回路層と低密度回路層をビアで連結する段階を含む、請求項6に記載の印刷回路基板製造方法。 - 前記ブリッジ回路と連結された外層回路を形成する段階をさらに含む、請求項6または請求項7に記載の印刷回路基板製造方法。
- 前記ブリッジ回路層を結合し埋め立てる段階は、
前記低密度回路層を具備した低密度回路層を形成する段階;
前記低密度回路層に前記ブリッジ回路層を結合させて電気的に連結する段階;および
前記第2キャリアが結合された前記ブリッジ回路層を埋め立てる段階を含む、請求項1に記載の印刷回路基板製造方法。 - 前記ブリッジ回路層を結合し埋め立てる段階は、
第3キャリアに前記ブリッジ回路層を装着させる段階;
前記第3キャリアに、前記第2キャリアが結合された前記ブリッジ回路層を埋め立てる前記低密度回路層をビルドアップ(build−up)する段階;および
前記第3キャリアを分離する段階を含む、請求項1に記載の印刷回路基板製造方法。
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KR10-2016-0037600 | 2016-03-29 | ||
KR1020160037600A KR101966328B1 (ko) | 2016-03-29 | 2016-03-29 | 인쇄회로기판 및 그 제조방법 |
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US10867954B2 (en) | 2017-11-15 | 2020-12-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interconnect chips |
KR102101712B1 (ko) * | 2018-03-21 | 2020-04-21 | (주)심텍 | 브릿지 기판을 포함하는 인쇄회로기판 |
KR102648090B1 (ko) * | 2019-05-17 | 2024-03-18 | 삼성전자주식회사 | 배선기판 및 이를 포함하는 반도체 패키지 |
JP2021093516A (ja) | 2019-12-11 | 2021-06-17 | インテル・コーポレーション | 集積回路パッケージのためのコンポジットブリッジダイツーダイ相互接続 |
KR20220015573A (ko) | 2020-07-31 | 2022-02-08 | 삼성전기주식회사 | 인쇄회로기판 및 그 제조방법 |
KR20220065550A (ko) | 2020-11-13 | 2022-05-20 | 삼성전기주식회사 | 연결구조체 내장기판 |
CN113035827B (zh) * | 2021-02-25 | 2022-07-05 | 日月光半导体制造股份有限公司 | 半导体封装装置及其制造方法 |
KR20230075176A (ko) | 2021-11-22 | 2023-05-31 | 삼성전기주식회사 | 인쇄회로기판 |
KR20240045007A (ko) * | 2022-09-29 | 2024-04-05 | 엘지이노텍 주식회사 | 반도체 패키지 |
KR20240044946A (ko) * | 2022-09-29 | 2024-04-05 | 엘지이노텍 주식회사 | 반도체 패키지 |
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2016
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KR101966328B1 (ko) | 2019-04-05 |
JP2017183714A (ja) | 2017-10-05 |
KR20170111677A (ko) | 2017-10-12 |
JP6787550B2 (ja) | 2020-11-18 |
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