JP6366412B2 - パターン形成方法 - Google Patents
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- 238000000034 method Methods 0.000 title claims description 62
- 230000007261 regionalization Effects 0.000 title description 7
- 239000000758 substrate Substances 0.000 claims description 36
- 238000002955 isolation Methods 0.000 claims description 10
- 238000000926 separation method Methods 0.000 claims description 8
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 239000011295 pitch Substances 0.000 description 18
- 238000005530 etching Methods 0.000 description 8
- 238000011161 development Methods 0.000 description 4
- 230000018109 developmental process Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 230000010354 integration Effects 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
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Description
まず、図4(a)に示すように、シリコン基板10上にゲート酸化膜11、ゲート材料12、およびハードマスク13を形成し、ハードマスク13の上にL/S=20/60nmのレジストパターンを形成する。L/S=20/60nmのレジストパターンは、例えば、L/S=40/40nmのマスクパターンを露光装置を用いてレジストに露光した後、酸素プラズマなどによってレジストを等方的にエッチングすることによって作製されうる。
L&Sパターンを部分的に除去するために用いられるパターンはカットパターンと呼ばれる。カットパターンにおける複数の要素(カット要素9)は、例えば、L&Sパターン上において、L&Sパターンのピッチと同じピッチの碁盤の目状のグリッド(Evenグリッド)の各交点に配置されうる。つまり、L&SパターンのピットとEvenグリッドのピッチは同等である。図5は、カットパターンにおける複数のカット要素9をEvenグリッドに従って配置した例を示す図である。しかしながら、近年における回路パターンの更なる微細化および高集積化に伴い、露光装置の解像限界より小さい線幅のライン1を有するL&Sパターンを部分的に除去することが求められている。この場合、カットパターンにおける複数のカット要素9をEvenグリッドに従って配置するように設計すると、複数のカット要素の線幅やピッチも露光装置の解像限界より小さくなる。そのため、当該露光装置を用いて複数のカット要素9をL&Sパターン上に形成することが困難になりうる。そこで、本実施形態では、カットパターンにおける複数のカット要素9を、図6に示すように、千鳥状のグリッドに従って配置する。図6は、カットパターンにおける複数のカット要素9を千鳥状のグリッドに従って配置した例を示す図である。カットパターンは、例えば、L&Sパターンにおける複数のライン上に複数のカット要素9が配置されるように構成される。そして、1つのライン上における複数のカット要素9は、L&Sパターンのピッチの2倍の間隔でライン1が伸びる方向(Y方向)に沿って配列される。また、隣り合う2つのラインのうち一方のカット要素9の配列と他方のカット要素9の配列とは、Y方向にL&Sパターンのピッチだけ互いにずれている。このようにカットパターンを構成することにより、カットパターンにおける複数のカット要素9同士の間隔を広げることができる。その結果、上述したように基板上に形成されたL&Sパターンにおける複数のライン1上に、複数のカット要素9を形成することが容易になる。
以下に、本実施形態におけるパターン形成方法について、図7〜図9を参照しながら説明する。図7は、本実施形態におけるパターン形成方法を示すフローチャートである。また、図8は、パターン形成方法の各工程におけるスタンダードセル4を示す図であり、図9は、パターン形成方法の各工程における基板の断面(XZ断面)を示す図である。図9は、図6における破線A−A’における断面を示している。以下の説明では、図4において示したゲート酸化膜11を省略し、シリコン基板10を単に「基板3」を呼ぶ。
Claims (7)
- 基板上に形成されたラインアンドスペースパターンを部分的に除去することにより基板上にパターンを形成するパターン形成方法であって、
複数の第1開口を有する第1層を前記ラインアンドスペースパターンの上に形成する第1形成工程と、
前記複数の第1開口のうち前記ラインアンドスペースパターンを部分的に除去するために用いる第1開口を露出させる第2開口を有する第2層を前記第1層の上に形成する第2形成工程と、
前記第2開口と前記第1開口とを介して前記ラインアンドスペースパターンを部分的に除去する除去工程と、
を含み、
前記複数の第1開口は、前記ラインアンドスペースパターンにおける複数のライン上に配置され、
1つのライン上における複数の第1開口は、前記ラインアンドスペースパターンのピッチの2倍の間隔で当該ラインが伸びる方向に沿って配列され、且つ、前記ラインアンドスペースパターンの隣り合う2つのラインのうち一方のライン上の前記複数の第1開口の配列と他方のライン上の前記複数の第1開口の配列は、前記方向に前記ピッチだけ互いにずれている、ことを特徴とするパターン形成方法。 - 前記基板は、複数の活性領域を電気的に分離するための分離領域を有し、
前記ラインアンドスペースパターンは、前記分離領域上に形成され、
前記第1形成工程では、前記分離領域の上のラインアンドスペースパターンの各ラインに少なくとも1つの第1開口が配置され、
前記第2開口によって露出される前記第1開口は、前記分離領域の上に形成されている、ことを特徴とする請求項1に記載のパターン形成方法。 - 前記基板は、第1活性領域および第2活性領域を更に含み、
前記分離領域は、前記第1活性領域と前記第2活性領域との間に配置され
前記ラインアンドスペースパターンにおけるラインは、前記第1活性領域、前記第2活性領域および前記分離領域にわたって、それらの上に形成されている、ことを特徴とする請求項2に記載のパターン形成方法。 - 前記複数のラインは、前記方向における前記分離領域の上の長さが互いに異なって前記基板上に形成されている、ことを特徴とする請求項2又は3に記載のパターン形成方法。
- 前記第2形成工程では、前記ラインアンドスペースパターンを部分的に除去するために用いる2つ以上の第1開口が1つの前記第2開口によって露出されるように前記第2層を形成する、ことを特徴とする請求項1乃至4のうちいずれか1項に記載のパターン形成方法。
- 前記第1開口の寸法は、前記ラインアンドスペースパターンにおける1つのラインの幅より大きい、ことを特徴とする請求項1乃至5のうちいずれか1項に記載のパターン形成方法。
- 前記第1形成工程では、EKBプロセスおよびDTDプロセスのうち一方を用いて前記複数の第1開口を形成する、ことを特徴とする請求項1乃至6のうちいずれか1項に記載のパターン形成方法。
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US9412649B1 (en) * | 2015-02-13 | 2016-08-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of fabricating semiconductor device |
CN113539832A (zh) * | 2016-03-24 | 2021-10-22 | 东京毅力科创株式会社 | 半导体装置的制造方法 |
JP6966686B2 (ja) | 2016-10-21 | 2021-11-17 | 株式会社ソシオネクスト | 半導体装置 |
US9741823B1 (en) | 2016-10-28 | 2017-08-22 | Internation Business Machines Corporation | Fin cut during replacement gate formation |
KR20180068653A (ko) | 2016-12-14 | 2018-06-22 | 삼성전자주식회사 | 반도체 장치 |
US11901190B2 (en) * | 2017-11-30 | 2024-02-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of patterning |
CN110828460B (zh) * | 2018-08-14 | 2022-07-19 | 中芯国际集成电路制造(北京)有限公司 | 半导体器件及其形成方法 |
CN110828466B (zh) * | 2019-11-11 | 2022-03-29 | 上海华力微电子有限公司 | 字线制作方法 |
JP2021153133A (ja) * | 2020-03-24 | 2021-09-30 | キオクシア株式会社 | パターン形成方法およびテンプレートの製造方法 |
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JP2011258822A (ja) * | 2010-06-10 | 2011-12-22 | Toshiba Corp | 半導体装置の製造方法 |
JP2012033923A (ja) * | 2010-07-29 | 2012-02-16 | Nikon Corp | 露光方法及び露光装置、並びにデバイス製造方法 |
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JP5881567B2 (ja) * | 2012-08-29 | 2016-03-09 | 株式会社東芝 | パターン形成方法 |
WO2014061760A1 (ja) * | 2012-10-19 | 2014-04-24 | 株式会社ニコン | パターン形成方法及びデバイス製造方法 |
US9349604B2 (en) * | 2013-10-20 | 2016-05-24 | Tokyo Electron Limited | Use of topography to direct assembly of block copolymers in grapho-epitaxial applications |
US9224617B2 (en) * | 2014-01-29 | 2015-12-29 | Globalfoundries Inc. | Forming cross-coupled line segments |
US9287131B2 (en) * | 2014-02-21 | 2016-03-15 | Globalfoundries Inc. | Methods of patterning line-type features using a multiple patterning process that enables the use of tighter contact enclosure spacing rules |
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US9502306B2 (en) | 2016-11-22 |
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