TWI538015B - 半導體元件的製作方法 - Google Patents

半導體元件的製作方法 Download PDF

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TWI538015B
TWI538015B TW103115886A TW103115886A TWI538015B TW I538015 B TWI538015 B TW I538015B TW 103115886 A TW103115886 A TW 103115886A TW 103115886 A TW103115886 A TW 103115886A TW I538015 B TWI538015 B TW I538015B
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holes
hard mask
photoresist layer
patterned photoresist
semiconductor device
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TW201537620A (zh
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周國耀
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華亞科技股份有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0338—Process specially adapted to improve the resolution of the mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/66181—Conductor-insulator-semiconductor capacitors, e.g. trench capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/92—Capacitors having potential barriers
    • H01L29/94—Metal-insulator-semiconductors, e.g. MOS
    • H01L29/945—Trench capacitors

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  • Condensed Matter Physics & Semiconductors (AREA)
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  • General Chemical & Material Sciences (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Preparing Plates And Mask In Photomechanical Process (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

半導體元件的製作方法
本發明係關於一種增進半導體元件之圖案密度的製作方法，尤其是關於一種利用單一光罩藉由單次曝光提升圖案密度的製作方法。
在積體電路的製造中，轉印(transfer)圖案於基底上的方法係使用微影技術，微影技術主要是使用微影曝光裝置，轉印光罩之圖案於基底上。隨著積體電路領域的快速發展，高效能、高積集度、低成本、輕薄短小已成為電子產品設計製造上所追尋之目標。在電路積集化越來越高的情況下，整個電路元件大小的設計也被迫往尺寸不停縮小的方向前進。因此，元件之間的臨界尺寸或是間距也就越來越小。
一般而言，微影裝置會有一個解析度上限，在製作高密度圖案時，光罩圖案的臨界尺寸、間距、線寬或是其它關鍵尺寸經常小於微影裝置的解析度上限，此時微影裝置就無法正確地將圖案轉印到基底上。傳統的製程會利用二次以上的曝光，即，藉由將預定圖案分散到數個光罩上，再以多次曝光完成所需的圖案，來達成目的。
然而，使用多次曝光會增加光罩對準誤差的機率，並且耗費光罩的製作費用。
有鑑於此，為解決上述問題，本發明提出一種使用單次曝光，並且可增加圖案密度的方法。
根據本發明之第一較佳實施例，本發明提供一種半導體元件的製作方法，包含以下步驟：首先提供一基底，一硬遮罩和一圖案化光阻層覆蓋基底，其中圖案化光阻層包含至少四個第一孔洞，前述的第一孔洞排列成二行二列，接著以圖案化光阻層為遮罩，移除部分的硬遮罩以在硬遮罩中形成至少四個第二孔洞，然後擴大各個第一孔洞，再以一填充材料填滿各個擴大的第一孔洞以及填滿各個第二孔洞，之後完全移除圖案化光阻層並且曝露出部分的硬遮罩，接續以填充材料為遮罩，移除部分之硬遮罩，以在硬遮罩中形成至少四個第四孔洞，最後完全移除填充材料。
根據本發明之第二較佳實施例，本發明提供一種半導體元件的製作方法，包含以下步驟：首先提供一硬遮罩，一圖案化光阻層覆蓋硬遮罩，其中圖案化光阻層包含複數個第一孔洞，前述的第一孔洞排列成複數行和複數列，然後以圖案化光阻層為遮罩，移除部分之硬遮罩以在硬遮罩中形成複數個第二孔洞，前述的第二孔洞排列成複數行和複數列，之後擴大各個第一孔洞，其中擴大的各個第一孔洞彼此互相連通，再以一填充材料填滿各個擴大的第一孔洞以及填滿各個第二孔洞，接續完全移除圖案化光阻層並且曝露出部分的硬遮罩，最後以填充材料為遮罩，移除部分之硬遮罩以在硬遮罩中形成複數個第三孔洞。
為讓本發明之上述目的、特徵及優點能更明顯易懂，下文特舉較佳實施方式，並配合所附圖式，作詳細說明如下。然而如下之較佳實施方式與圖式僅供參考與說明用，並非用來對本發明加以限制者
10‧‧‧基底
12‧‧‧硬遮罩
14‧‧‧圖案化光阻層
16‧‧‧孔洞
16’‧‧‧擴大的孔洞
18‧‧‧孔洞
20‧‧‧填充材料
22‧‧‧孔洞
24‧‧‧孔洞
26‧‧‧交錯圖案
201‧‧‧柱狀元件
第1圖至第6圖為根據本發明之較佳實施例所繪示的半導體元件之製作方法的上視示意圖。第1A、2A、3A、4A、5A和6A圖分別繪示第1圖至第 6圖沿AA’切線方向之側視圖。第3B、4B、5B和6B圖分別繪示第3圖至第6圖沿BB’切線方向之側視圖。
如第1圖和第1A圖所示，首先提供一基底10，基底10上依序覆有一硬遮罩12和一圖案化光阻層14，圖案化光阻層14覆蓋在硬遮罩12上，本發明之基底10可以為一矽(Silicon)基底、一鍺(Germanium)基底、一砷化錄(Gallium Arsenide)基底、一矽鍺(Silicon Germanium)基底、一磷化銦(Indium Phosphide)基底、一氮化鎵(Gallium Nitride)基、一碳化矽(Silicon Carbide)基底或是一矽覆絕緣(silicon on insulator,SOI)基底、金屬、介電層或是其它適合的材料。硬遮罩12可以為氮化矽、氧化矽、氮氧化矽或是其它適合的材料。請參閱第1圖中的實施例(a)，圖案化光阻層14之中設置有至少四個孔洞16，孔洞16排列成二行二列，一夾角x位在其中之一行和其中之一列之間，夾角x本質上為90度；依據本發明之另一較佳實施例，如第1圖中的實施例(b)所示，夾角x較佳小於90度。以下的製作方法將採用第1圖中的實施例(a)為例接續說明，但本發明的製作方法同時適用於第1圖中的實施例(a)和實施例(b)的情況。請繼續參閱第1圖中的實施例(a)，在較佳的情況下，在圖案化光阻層14中有超過四個孔洞16排列成複數行和複數列，此外，硬遮罩12會由孔洞16曝露出來。再者圖案化光阻層14可以經由標準的微影技術搭配一個傳統的光罩，利用微影機台進行單次曝光而形成。
如第2圖和第2A圖所示，在圖案化光阻層14中的孔洞16被轉印到硬遮罩12上，以形成複數個孔洞18。孔洞18可以為圓形、矩形、多邊形或其它適合的形狀。轉印的製程，舉例而言，首先以圖案化光阻層14為遮罩，移除部分的硬遮罩12，以在硬遮罩12中形成對應孔洞16的孔洞18，硬遮罩12較佳可以採用乾蝕刻進行移除。此外，在較佳的情況下，在硬遮罩12中有超過四個孔洞18排列成複數行和複數列。此時各個孔洞16與其對應 的孔洞18相連通，並且基底10由孔洞16和孔洞18曝露出來。
如第3圖、第3A圖和第3B圖所示，擴大所有在圖案化光阻層14中的孔洞16以形成複數個擴大的孔洞16’，其中擴大的孔洞16’較佳藉由修整步驟(trimming process)來形成，並且各個擴大的孔洞16’彼此互相連通。硬遮罩12由擴大的孔洞16’曝露出來，此外圖案化光阻層14、硬遮罩12和基底10形成一階梯輪廓(圖未示)。接著如第4圖、第4A圖和第4B圖所示，全面形成一填充材料20覆蓋圖案化光阻層14並且填滿各個擴大的孔洞16’以及填滿各個孔洞18。然後回蝕刻填充材料20使得填充材料20的一上表面和圖案化光阻層14的一上表面切齊，填充材料20可以為氮化矽、氧化矽、氮氧化矽和其它適合的材料。值得注意的是，填充材料20和硬遮罩12係利用不同的材料形成。此外，填充材料20相對於硬遮罩12有高蝕刻選擇比。
請參閱第5圖、第5A圖和第5B圖。完全移除圖案化光阻層14使得部分的硬遮罩12由填充材料20曝露出來，詳細來說，如第5圖和第5B圖所示，在完全移除圖案化光阻層14之後，填充材料20形成複數個柱狀元件201，柱狀元件201彼此相連，並且四個柱狀元件201定義出一個孔洞22，硬遮罩12係由孔洞22曝露出來。然後如第6圖、第6A圖和第6B圖所示，以填充材料20為遮罩，將曝露出來的硬遮罩12移除，以在剩餘的硬遮罩12中形成複數個孔洞24，孔洞24可以為圓形、矩形、多邊形或其它適合的形狀。請繼續參閱第6圖，此時孔洞18和孔洞24在硬遮罩12上形成一交錯圖案26，再者，至少一孔洞24被四個孔洞18環繞，其中四個孔洞18中，各個孔洞18之中心至孔洞24之中心的距離相同。根據本發明之另一較佳實施例，在其它的情況下，例如第1圖中的夾角x小於90度的情況，最後會形成兩個孔洞24被四個孔洞18環繞。之後，完全移除填充材料20，然後交錯圖案26可以被轉印到基底10上以形成一高密度圖案(圖未示)。高密度圖案亦包含複數個孔洞，前述孔洞可以用來形成溝渠式電容、接觸插塞或是其它半導體元件。另外，前述在基底10中的孔洞可以為圓形、矩形、多邊形或其它適 合的形狀。
由於傳統的微影機台具有解析度的上限，若是要微影的高密度圖案其臨界尺寸或是其它關鍵尺寸超過微影機台解析度，則微影機台就無法在單次曝光的製程形成前述的高密度圖案，因此傳統的解決方法使用兩個以上的光罩，藉由多次曝光來形成高密度圖案，然而如此製程不但浪費時間並且需消耗較高的製程費用。因此，本發明提供一種相異於多次曝光的製作方法來形成高密度圖案，藉由本發明的方法，高密度圖案可以利用一個光罩和單次曝光來形成，由於只需要單次曝光，所以可以降低光罩對準偏差的機率，最後產品的缺陷可以因此而減少。
以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
10‧‧‧基底
12‧‧‧硬遮罩
14‧‧‧圖案化光阻層
16’‧‧‧擴大的孔洞
18‧‧‧孔洞

Claims (10)

  1. 一種半導體元件的製作方法，包含：提供一基底，一硬遮罩和一圖案化光阻層覆蓋該基底，其中該圖案化光阻層包含至少四個第一孔洞，該等第一孔洞排列成二行二列；以該圖案化光阻層為遮罩，移除部分之該硬遮罩以在該硬遮罩中形成至少四個第二孔洞；擴大各該第一孔洞；以一填充材料填滿各該擴大的第一孔洞以及填滿各該第二孔洞；完全移除該圖案化光阻層並且曝露出部分的該硬遮罩；以該填充材料為遮罩，移除部分之該硬遮罩，以在該硬遮罩中形成至少四個第四孔洞；以及完全移除該填充材料。
  2. 如請求項1所述之半導體元件的製作方法，其中在各該第一孔洞擴大之後，各該擴大的第一孔洞互相連通，並且該硬遮罩由該等擴大的第一孔洞曝露出來。
  3. 如請求項1所述之半導體元件的製作方法，其中在完全移除該圖案化光阻層之後，該填充材料形成四個柱狀元件，該等柱狀元件定義出一第三孔洞，並且該硬遮罩由該第三孔洞曝露出來。
  4. 如請求項1所述之半導體元件的製作方法，其中該第四孔洞被該四個第二孔洞環繞。
  5. 如請求項1所述之半導體元件的製作方法，另包含：在完全移除該填充材料後，以該硬遮罩為遮罩，蝕刻該基底。
  6. 如請求項1所述之半導體元件的製作方法，其中該硬遮罩和該填充材料係利用不同材料製作。
  7. 一種半導體元件的製作方法，包含：提供一硬遮罩，一圖案化光阻層覆蓋該硬遮罩，其中該圖案化光阻層包含複數個第一孔洞，該等第一孔洞排列成複數行和複數列；以該圖案化光阻層為遮罩，移除部分之該硬遮罩以在該硬遮罩中形成複數個第二孔洞，該等第二孔洞排列成複數行和複數列；擴大各該第一孔洞，其中擴大的各該第一孔洞彼此互相連通；以一填充材料填滿各該擴大的第一孔洞以及填滿各該第二孔洞；完全移除該圖案化光阻層並且曝露出部分的該硬遮罩；以及以該填充材料為遮罩，移除部分之該硬遮罩以在該硬遮罩中形成複數個第三孔洞。
  8. 如請求項7所述之半導體元件的製作方法，其中該等第一孔洞和該等第三孔洞形成交錯圖案。
  9. 如請求項7所述之半導體元件的製作方法，另包含在該等第三孔洞形成之後，完全移除該填充材料。
  10. 如請求項7所述之半導體元件的製作方法，其中其中該硬遮罩和該填充材料係利用不同材料製作。
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