JP6360457B2 - 半導体装置及びその製造方法 - Google Patents

半導体装置及びその製造方法 Download PDF

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Publication number
JP6360457B2
JP6360457B2 JP2015078949A JP2015078949A JP6360457B2 JP 6360457 B2 JP6360457 B2 JP 6360457B2 JP 2015078949 A JP2015078949 A JP 2015078949A JP 2015078949 A JP2015078949 A JP 2015078949A JP 6360457 B2 JP6360457 B2 JP 6360457B2
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layer
film
intermediate layer
metal
metal layer
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JP2015078949A
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JP2016201407A (ja
JP2016201407A5 (enExample
Inventor
健士 石崎
健士 石崎
和田　純一
純一 和田
坂田　敦子
敦子 坂田
桂 渡邉
桂 渡邉
政幸 北村
政幸 北村
大輔 池野
大輔 池野
啓 若月
啓 若月
博隆 荻原
博隆 荻原
真也 奥田
真也 奥田
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Kioxia Corp
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Toshiba Memory Corp
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Priority to JP2015078949A priority Critical patent/JP6360457B2/ja
Priority to US14/828,830 priority patent/US9780111B2/en
Publication of JP2016201407A publication Critical patent/JP2016201407A/ja
Publication of JP2016201407A5 publication Critical patent/JP2016201407A5/ja
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND

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  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
JP2015078949A 2015-04-08 2015-04-08 半導体装置及びその製造方法 Active JP6360457B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2015078949A JP6360457B2 (ja) 2015-04-08 2015-04-08 半導体装置及びその製造方法
US14/828,830 US9780111B2 (en) 2015-04-08 2015-08-18 Semiconductor device and method for manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2015078949A JP6360457B2 (ja) 2015-04-08 2015-04-08 半導体装置及びその製造方法

Publications (3)

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JP2016201407A JP2016201407A (ja) 2016-12-01
JP2016201407A5 JP2016201407A5 (enExample) 2017-09-14
JP6360457B2 true JP6360457B2 (ja) 2018-07-18

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JP2015078949A Active JP6360457B2 (ja) 2015-04-08 2015-04-08 半導体装置及びその製造方法

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US (1) US9780111B2 (enExample)
JP (1) JP6360457B2 (enExample)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105934819B (zh) 2014-01-21 2019-04-26 应用材料公司 用于3d闪存应用的电介质-金属堆叠
US10451489B2 (en) * 2015-07-10 2019-10-22 The Charles Stark Draper Laboratory, Inc. Thermal event sensor
DE102016207307A1 (de) * 2016-04-28 2017-11-02 Carl Zeiss Smt Gmbh Optisches Element und optische Anordnung damit
JP2019165050A (ja) 2018-03-19 2019-09-26 東芝メモリ株式会社 半導体装置およびその製造方法
US10840259B2 (en) 2018-08-13 2020-11-17 Sandisk Technologies Llc Three-dimensional memory device including liner free molybdenum word lines and methods of making the same
JP2020047706A (ja) 2018-09-18 2020-03-26 キオクシア株式会社 半導体装置およびその製造方法
JP2020150147A (ja) * 2019-03-14 2020-09-17 キオクシア株式会社 半導体記憶装置
JP2020150218A (ja) 2019-03-15 2020-09-17 キオクシア株式会社 半導体記憶装置
US11158718B2 (en) * 2019-04-15 2021-10-26 Micron Technology, Inc. Assemblies which include wordlines having a first metal-containing material at least partially surrounding a second metal-containing material and having different crystallinity than the second metal-containing material
CN111583795B (zh) * 2020-05-12 2022-03-08 Tcl华星光电技术有限公司 显示面板的制备方法及显示装置
KR20220011092A (ko) 2020-07-20 2022-01-27 에이에스엠 아이피 홀딩 비.브이. 전이 금속층을 포함하는 구조체를 형성하기 위한 방법 및 시스템
TWI878570B (zh) * 2020-07-20 2025-04-01 荷蘭商Ａｓｍ Ｉｐ私人控股有限公司 用於沉積鉬層之方法及系統

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3248262B2 (ja) * 1992-09-25 2002-01-21 松下電器産業株式会社 半導体装置の製造方法
JP2010080685A (ja) * 2008-09-26 2010-04-08 Toshiba Corp 不揮発性記憶装置及びその製造方法
KR101604054B1 (ko) * 2009-09-03 2016-03-16 삼성전자주식회사 반도체 소자 및 그 형성방법
US20120064682A1 (en) * 2010-09-14 2012-03-15 Jang Kyung-Tae Methods of Manufacturing Three-Dimensional Semiconductor Memory Devices
JP5670704B2 (ja) 2010-11-10 2015-02-18 株式会社東芝 不揮発性半導体記憶装置及びその製造方法
JP2012146861A (ja) 2011-01-13 2012-08-02 Toshiba Corp 半導体記憶装置
JP5351201B2 (ja) 2011-03-25 2013-11-27 株式会社東芝 不揮発性半導体記憶装置及びその製造方法
KR102101841B1 (ko) * 2013-10-28 2020-04-17 삼성전자 주식회사 수직형 비휘발성 메모리 소자

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JP2016201407A (ja) 2016-12-01
US20160300845A1 (en) 2016-10-13
US9780111B2 (en) 2017-10-03

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