JP6258597B2 - Led装置の製造方法 - Google Patents
Led装置の製造方法 Download PDFInfo
- Publication number
- JP6258597B2 JP6258597B2 JP2013083654A JP2013083654A JP6258597B2 JP 6258597 B2 JP6258597 B2 JP 6258597B2 JP 2013083654 A JP2013083654 A JP 2013083654A JP 2013083654 A JP2013083654 A JP 2013083654A JP 6258597 B2 JP6258597 B2 JP 6258597B2
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- electrode
- light emitting
- molten material
- led device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 239000000758 substrate Substances 0.000 claims description 75
- 239000012768 molten material Substances 0.000 claims description 29
- 239000002923 metal particle Substances 0.000 claims description 25
- 238000010438 heat treatment Methods 0.000 claims description 22
- 229920005989 resin Polymers 0.000 claims description 11
- 239000011347 resin Substances 0.000 claims description 11
- 229920005992 thermoplastic resin Polymers 0.000 claims description 3
- 238000002844 melting Methods 0.000 description 21
- 230000008018 melting Effects 0.000 description 20
- 239000000463 material Substances 0.000 description 7
- 239000004065 semiconductor Substances 0.000 description 6
- 239000010949 copper Substances 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 239000007787 solid Substances 0.000 description 3
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000007789 sealing Methods 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical class [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 229920001169 thermoplastic Polymers 0.000 description 1
- 239000004416 thermosoftening plastic Substances 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
- H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
- Led Device Packages (AREA)
Description
12 発光素子
13 サブマウント基板
14 素子電極
15 基板電極
15a 上面
15b 側面
16 溶融材
16a 第1の金属粒子
16b 第2の金属粒子
17 回路基板
18 レジスト層
19 外部電極
20 導通接合部
21 集合サブマウント基板
22 樹脂シート
23 電極パターン
Claims (3)
- 集合サブマウント基板の上面に有する複数の基板電極と、集合サブマウント基板の上面に載置される複数の発光素子の下面に有する素子電極との間に溶融材を介在させた後、
前記集合サブマウント基板上に載置された複数の発光素子を熱可塑性の樹脂シートで被覆し、
樹脂シートと集合サブマウント基板との間を減圧した後、前記基板電極と素子電極との間に介在させた溶融材を加熱溶融することで、基板電極の上面から側面までを前記溶融材で覆うようにして素子電極との電気的接続を図ることを特徴とするLED装置の製造方法。 - 前記溶融材は、前記素子電極を基板電極に接合させる際の最初の加熱によって溶融する第1の金属粒子と、前記最初の加熱時の温度では溶融しない第2の金属粒子とを含有している請求項1に記載のLED装置の製造方法。
- 前記各基板電極は、素子電極よりも小さく形成される請求項1又は2に記載のLED装置の製造方法。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2013083654A JP6258597B2 (ja) | 2013-04-12 | 2013-04-12 | Led装置の製造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2013083654A JP6258597B2 (ja) | 2013-04-12 | 2013-04-12 | Led装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2014207307A JP2014207307A (ja) | 2014-10-30 |
JP6258597B2 true JP6258597B2 (ja) | 2018-01-10 |
Family
ID=52120658
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2013083654A Active JP6258597B2 (ja) | 2013-04-12 | 2013-04-12 | Led装置の製造方法 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP6258597B2 (ja) |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3877642B2 (ja) * | 2002-05-21 | 2007-02-07 | ローム株式会社 | 半導体チップを使用した半導体装置 |
JP2005038892A (ja) * | 2003-07-15 | 2005-02-10 | Matsushita Electric Ind Co Ltd | 半導体発光装置およびその製造方法 |
US20060208364A1 (en) * | 2005-03-19 | 2006-09-21 | Chien-Jen Wang | LED device with flip chip structure |
JP4667103B2 (ja) * | 2005-04-01 | 2011-04-06 | 旭化成イーマテリアルズ株式会社 | 導電性フィラー、及び低温はんだ材料 |
-
2013
- 2013-04-12 JP JP2013083654A patent/JP6258597B2/ja active Active
Also Published As
Publication number | Publication date |
---|---|
JP2014207307A (ja) | 2014-10-30 |
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