JP6254259B2 - 静電放電ダイオード - Google Patents

静電放電ダイオード Download PDF

Info

Publication number
JP6254259B2
JP6254259B2 JP2016512918A JP2016512918A JP6254259B2 JP 6254259 B2 JP6254259 B2 JP 6254259B2 JP 2016512918 A JP2016512918 A JP 2016512918A JP 2016512918 A JP2016512918 A JP 2016512918A JP 6254259 B2 JP6254259 B2 JP 6254259B2
Authority
JP
Japan
Prior art keywords
substrate
diode
layer
semiconductor material
tsv wafer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2016512918A
Other languages
English (en)
Japanese (ja)
Other versions
JP2016526285A5 (enExample
JP2016526285A (ja
Inventor
ヴィディヤ・ラマチャンドラン
ブライアン・エム・ヘンダーソン
シーチュン・グ
チュウ−グアン・タン
ジュン・ピル・キム
テヒュン・キム
Original Assignee
クアルコム，インコーポレイテッド
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by クアルコム，インコーポレイテッド filed Critical クアルコム，インコーポレイテッド
Publication of JP2016526285A publication Critical patent/JP2016526285A/ja
Publication of JP2016526285A5 publication Critical patent/JP2016526285A5/ja
Application granted granted Critical
Publication of JP6254259B2 publication Critical patent/JP6254259B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/113—Isolations within a component, i.e. internal isolations
    • H10D62/115—Dielectric isolations, e.g. air gaps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00—Diodes
    • H10D8/01—Manufacture or treatment
    • H10D8/043—Manufacture or treatment of planar diodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00—Diodes
    • H10D8/01—Manufacture or treatment
    • H10D8/051—Manufacture or treatment of Schottky diodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00—Diodes
    • H10D8/411—PN diodes having planar bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00—Diodes
    • H10D8/60—Schottky-barrier diodes 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/201—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits
    • H10D84/204—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits of combinations of diodes or capacitors or resistors
    • H10D84/221—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits of combinations of diodes or capacitors or resistors of only diodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D88/00—Three-dimensional [3D] integrated devices
    • H10D88/101—Three-dimensional [3D] integrated devices comprising components on opposite major surfaces of semiconductor substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
    • H10D89/611—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using diodes as protective elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
    • H10D89/931—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs characterised by the dispositions of the protective arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P52/00—Grinding, lapping or polishing of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0245—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising use of blind vias during the manufacture
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0249—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias wherein the through-semiconductor via protrudes from backsides of the chips, wafers or substrates during the manufacture
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices
    • H10W42/60—Arrangements for protection of devices protecting against electrostatic charges or discharges, e.g. Faraday shields
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H10W70/635—Through-vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/49—Adaptable interconnections, e.g. fuses or antifuses
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/66—Conductive materials thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H10W72/01204—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using temporary auxiliary members, e.g. using sacrificial coatings or handle substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/0198—Manufacture or treatment batch processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H10W72/242—Dispositions, e.g. layouts relative to the surface, e.g. recessed, protruding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H10W72/244—Dispositions, e.g. layouts relative to underlying supporting features, e.g. bond pads, RDLs or vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/29—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/922—Bond pads being integral with underlying chip-level interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/942—Dispositions of bond pads relative to underlying supporting features, e.g. bond pads, RDLs or vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/297—Configurations of stacked chips characterised by the through-semiconductor vias [TSVs] in the stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
JP2016512918A 2013-05-06 2014-04-23 静電放電ダイオード Expired - Fee Related JP6254259B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/887,723 2013-05-06
US13/887,723 US9093462B2 (en) 2013-05-06 2013-05-06 Electrostatic discharge diode
PCT/US2014/035076 WO2014182449A1 (en) 2013-05-06 2014-04-23 Electrostatic discharge diode

Publications (3)

Publication Number Publication Date
JP2016526285A JP2016526285A (ja) 2016-09-01
JP2016526285A5 JP2016526285A5 (enExample) 2017-03-23
JP6254259B2 true JP6254259B2 (ja) 2017-12-27

Family

ID=50819974

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2016512918A Expired - Fee Related JP6254259B2 (ja) 2013-05-06 2014-04-23 静電放電ダイオード

Country Status (6)

Country Link
US (2) US9093462B2 (enExample)
EP (1) EP2994937B1 (enExample)
JP (1) JP6254259B2 (enExample)
KR (1) KR101755555B1 (enExample)
CN (1) CN105190888B (enExample)
WO (1) WO2014182449A1 (enExample)

Families Citing this family (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9093462B2 (en) 2013-05-06 2015-07-28 Qualcomm Incorporated Electrostatic discharge diode
US9443764B2 (en) * 2013-10-11 2016-09-13 GlobalFoundries, Inc. Method of eliminating poor reveal of through silicon vias
US9786580B2 (en) 2013-11-15 2017-10-10 Taiwan Semiconductor Manufacturing Company, Ltd. Self-alignment for redistribution layer
TWI581325B (zh) 2014-11-12 2017-05-01 精材科技股份有限公司 晶片封裝體及其製造方法
EP3035385A1 (en) * 2014-12-16 2016-06-22 IMEC vzw Semiconductor interposer comprising a schottky diode and a method for fabricating the interposer
US9583462B2 (en) * 2015-01-22 2017-02-28 Qualcomm Incorporated Damascene re-distribution layer (RDL) in fan out split die application
US9922970B2 (en) 2015-02-13 2018-03-20 Qualcomm Incorporated Interposer having stacked devices
DE102016118709B3 (de) * 2016-10-04 2018-01-25 Infineon Technologies Ag Schutzvorrichtung vor elektrostatischer entladung und elektronische schaltvorrichtung
CN112164688B (zh) * 2017-07-21 2023-06-13 联华电子股份有限公司 芯片堆叠结构及管芯堆叠结构的制造方法
US10559520B2 (en) * 2017-09-29 2020-02-11 Qualcomm Incorporated Bulk layer transfer processing with backside silicidation
CN108054139B (zh) * 2017-12-15 2020-12-18 浙江清华柔性电子技术研究院 Tsv转接板及其制备方法
CN108109961A (zh) * 2017-12-15 2018-06-01 西安科锐盛创新科技有限公司 基于二极管的集成电路抗静电转接板及其制备方法
CN108063114B (zh) * 2017-12-15 2019-11-22 台州第五空间航空科技有限公司 基于横向二极管的tsv转接板及其制备方法
CN108109962A (zh) * 2017-12-15 2018-06-01 西安科锐盛创新科技有限公司 集成电路抗静电转接板
CN108109957B (zh) * 2017-12-15 2020-12-25 浙江清华柔性电子技术研究院 系统级封装抗静电转接板
CN108109996B (zh) * 2017-12-15 2021-06-22 西安科锐盛创新科技有限公司 基于二极管的集成电路抗静电转接板及其制备方法
CN107994000B (zh) * 2017-12-15 2021-01-12 浙江清华柔性电子技术研究院 用于系统级封装的tsv转接板及其制备方法
CN108109988B (zh) * 2017-12-15 2020-12-22 浙江清华柔性电子技术研究院 用于系统级封装的防静电装置
CN108109953B (zh) * 2017-12-15 2020-12-25 浙江清华柔性电子技术研究院 用于系统级封装的tsv转接板
CN108122889B (zh) * 2017-12-15 2020-10-30 西安科锐盛创新科技有限公司 基于横向二极管的tsv转接板
CN107946240A (zh) * 2017-12-15 2018-04-20 西安科锐盛创新科技有限公司 Tsv转接板及其制备方法
CN108054133A (zh) * 2017-12-15 2018-05-18 西安科锐盛创新科技有限公司 集成电路抗静电转接板及其制备方法
CN108054156B (zh) * 2017-12-15 2021-09-03 西安科锐盛创新科技有限公司 用于系统级封装的防静电装置
CN109994425B (zh) * 2019-04-04 2021-07-30 上海迈铸半导体科技有限公司 填充基片的制备方法、填充基片及微孔互连结构制备方法
US11837641B2 (en) 2019-12-18 2023-12-05 Intel Corporation Gate-all-around integrated circuit structures having adjacent deep via substrate contacts for sub-fin electrical contact
US11264373B2 (en) 2019-12-21 2022-03-01 Intel Corporation Die backend diodes for electrostatic discharge (ESD) protection
US11424239B2 (en) * 2019-12-21 2022-08-23 Intel Corporation Diodes for package substrate electrostatic discharge (ESD) protection
DE102021107976A1 (de) * 2020-05-21 2021-11-25 Taiwan Semiconductor Manufacturing Co., Ltd. Elektrostatische entladungsschaltung und verfahren zum bilden dergleichen
US12046567B2 (en) 2020-05-21 2024-07-23 Taiwan Semiconductor Manufacturing Company Ltd. Electrostatic discharge circuit and method of forming the same
US11342246B2 (en) * 2020-07-21 2022-05-24 Qualcomm Incorporated Multi-terminal integrated passive devices embedded on die and a method for fabricating the multi-terminal integrated passive devices
CN116529974A (zh) * 2020-11-16 2023-08-01 Tdk电子股份有限公司 带有esd保护元件的硅衬底
US11973075B2 (en) 2021-02-22 2024-04-30 Taiwan Semiconductor Manufacturing Company, Ltd. Dual substrate side ESD diode for high speed circuit
WO2025258351A1 (ja) * 2024-06-10 2025-12-18 ソニーセミコンダクタソリューションズ株式会社 半導体装置、固体撮像素子及び電子機器

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7655999B2 (en) 2006-09-15 2010-02-02 Udt Sensors, Inc. High density photodiodes
US7473979B2 (en) * 2006-05-30 2009-01-06 International Business Machines Corporation Semiconductor integrated circuit devices having high-Q wafer back-side capacitors
JP5319084B2 (ja) 2007-06-19 2013-10-16 ルネサスエレクトロニクス株式会社 半導体装置
US8816486B2 (en) 2008-05-12 2014-08-26 Taiwan Semiconductor Manufacturing Co., Ltd. Pad structure for 3D integrated circuit
US8017471B2 (en) 2008-08-06 2011-09-13 International Business Machines Corporation Structure and method of latchup robustness with placement of through wafer via within CMOS circuitry
US8080862B2 (en) * 2008-09-09 2011-12-20 Qualcomm Incorporate Systems and methods for enabling ESD protection on 3-D stacked devices
TWI372457B (en) 2009-03-20 2012-09-11 Ind Tech Res Inst Esd structure for 3d ic tsv device
US8232625B2 (en) 2009-03-26 2012-07-31 International Business Machines Corporation ESD network circuit with a through wafer via structure and a method of manufacture
US8264065B2 (en) * 2009-10-23 2012-09-11 Synopsys, Inc. ESD/antenna diodes for through-silicon vias
TWI413236B (zh) 2010-06-11 2013-10-21 財團法人工業技術研究院 半導體裝置之堆疊製程的靜電放電保護方案
US8502338B2 (en) * 2010-09-09 2013-08-06 Taiwan Semiconductor Manufacturing Company, Ltd. Through-substrate via waveguides
US8193039B2 (en) 2010-09-24 2012-06-05 Advanced Micro Devices, Inc. Semiconductor chip with reinforcing through-silicon-vias
US8633562B2 (en) 2011-04-01 2014-01-21 Qualcomm Incorporated Voltage switchable dielectric for die-level electrostatic discharge (ESD) protection
US8872235B2 (en) 2012-02-23 2014-10-28 Infineon Technologies Austria Ag Integrated Schottky diode for HEMTs
KR102013770B1 (ko) * 2012-08-30 2019-08-23 에스케이하이닉스 주식회사 반도체 소자 및 그 제조 방법
JP2014165358A (ja) * 2013-02-26 2014-09-08 Panasonic Corp 半導体装置及びその製造方法
US9093462B2 (en) 2013-05-06 2015-07-28 Qualcomm Incorporated Electrostatic discharge diode

Also Published As

Publication number Publication date
US9093462B2 (en) 2015-07-28
US9379201B2 (en) 2016-06-28
US20150333053A1 (en) 2015-11-19
EP2994937B1 (en) 2016-12-14
CN105190888A (zh) 2015-12-23
US20140327105A1 (en) 2014-11-06
EP2994937A1 (en) 2016-03-16
CN105190888B (zh) 2017-08-22
WO2014182449A1 (en) 2014-11-13
JP2016526285A (ja) 2016-09-01
KR20160004356A (ko) 2016-01-12
KR101755555B1 (ko) 2017-07-07

Similar Documents

Publication Publication Date Title
JP6254259B2 (ja) 静電放電ダイオード
US11626388B2 (en) Interconnect structure with redundant electrical connectors and associated systems and methods
CN107690700B (zh) 用于层叠封装结构的中介体
US9530758B2 (en) 3D integrated circuit package with through-mold first level interconnects
US10163792B2 (en) Semiconductor device having an airgap defined at least partially by a protective structure
JP2016048780A (ja) 積層集積回路のための二面の相互接続されたｃｍｏｓ
JP2012527129A (ja) 磁気トンネル接合デバイスおよび製作
US12087836B2 (en) Contact over active gate structures with metal oxide-caped contacts to inhibit shorting
KR20150127581A (ko) 디바이스 하부의 인터커넥트 구조체들을 형성하는 방법
US9466554B2 (en) Integrated device comprising via with side barrier layer traversing encapsulation layer
US12581692B2 (en) Transistor devices with double-side contacts
WO2016123115A1 (en) Package-on-package (pop) structure
US20200321395A1 (en) Independently scaling selector and memory in memory cell
CN116266555A (zh) 用于先进的集成电路结构制作的等高度通孔
WO2019117904A1 (en) Vertical thyristors for cross-point dynamic memories
TWI878889B (zh) 半導體晶粒封裝件以及製造其的方法
US20250273613A1 (en) Methods and apparatus to improve reliability of multi-layer vias
TW202515372A (zh) 背側雙向互連件
CN121729995A (zh) 堆叠集成电路器件
KR20140038195A (ko) Ｔｓｖ구조 형성 방법

Legal Events

Date Code Title Description
A529 Written submission of copy of amendment under article 34 pct

Free format text: JAPANESE INTERMEDIATE CODE: A529

Effective date: 20151029

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20170213

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20170213

A871 Explanation of circumstances concerning accelerated examination

Free format text: JAPANESE INTERMEDIATE CODE: A871

Effective date: 20170213

A975 Report on accelerated examination

Free format text: JAPANESE INTERMEDIATE CODE: A971005

Effective date: 20170227

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20170313

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20170516

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20170731

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20171019

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20171106

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20171129

R150 Certificate of patent or registration of utility model

Ref document number: 6254259

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees