CN105190888B - 静电放电二极管 - Google Patents

静电放电二极管 Download PDF

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Publication number
CN105190888B
CN105190888B CN201480025342.7A CN201480025342A CN105190888B CN 105190888 B CN105190888 B CN 105190888B CN 201480025342 A CN201480025342 A CN 201480025342A CN 105190888 B CN105190888 B CN 105190888B
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substrate
diode
backside
layer
semiconductor material
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Expired - Fee Related
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Chinese (zh)
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CN105190888A (zh
Inventor
V·拉马钱德兰
B·M·亨德森
S·顾
C-G·谭
J·P·金
T·金
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Qualcomm Inc
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Qualcomm Inc
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/113—Isolations within a component, i.e. internal isolations
    • H10D62/115—Dielectric isolations, e.g. air gaps
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00—Diodes
    • H10D8/01—Manufacture or treatment
    • H10D8/043—Manufacture or treatment of planar diodes
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00—Diodes
    • H10D8/01—Manufacture or treatment
    • H10D8/051—Manufacture or treatment of Schottky diodes
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/201—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits
    • H10D84/204—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits of combinations of diodes or capacitors or resistors
    • H10D84/221—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits of combinations of diodes or capacitors or resistors of only diodes
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D88/00—Three-dimensional [3D] integrated devices
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    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
    • H10D89/611—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using diodes as protective elements
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    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
    • H10D89/931—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs characterised by the dispositions of the protective arrangements
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    • H10W10/01—Manufacture or treatment
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    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
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    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0245—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising use of blind vias during the manufacture
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    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0249—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias wherein the through-semiconductor via protrudes from backsides of the chips, wafers or substrates during the manufacture
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    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices
    • H10W42/60—Arrangements for protection of devices protecting against electrostatic charges or discharges, e.g. Faraday shields
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H10W70/635—Through-vias
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    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/49—Adaptable interconnections, e.g. fuses or antifuses
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    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
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    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H10W72/01204—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using temporary auxiliary members, e.g. using sacrificial coatings or handle substrates
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    • H10W72/00—Interconnections or connectors in packages
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    • H10W72/241—Dispositions, e.g. layouts
    • H10W72/242—Dispositions, e.g. layouts relative to the surface, e.g. recessed, protruding
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    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H10W72/244—Dispositions, e.g. layouts relative to underlying supporting features, e.g. bond pads, RDLs or vias
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/29—Bond pads specially adapted therefor
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/922—Bond pads being integral with underlying chip-level interconnections
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    • H10W72/941—Dispositions of bond pads
    • H10W72/942—Dispositions of bond pads relative to underlying supporting features, e.g. bond pads, RDLs or vias
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    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/297—Configurations of stacked chips characterised by the through-semiconductor vias [TSVs] in the stacked chips
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    • H10W90/00—Package configurations
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    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
CN201480025342.7A 2013-05-06 2014-04-23 静电放电二极管 Expired - Fee Related CN105190888B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/887,723 2013-05-06
US13/887,723 US9093462B2 (en) 2013-05-06 2013-05-06 Electrostatic discharge diode
PCT/US2014/035076 WO2014182449A1 (en) 2013-05-06 2014-04-23 Electrostatic discharge diode

Publications (2)

Publication Number Publication Date
CN105190888A CN105190888A (zh) 2015-12-23
CN105190888B true CN105190888B (zh) 2017-08-22

Family

ID=50819974

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201480025342.7A Expired - Fee Related CN105190888B (zh) 2013-05-06 2014-04-23 静电放电二极管

Country Status (6)

Country Link
US (2) US9093462B2 (enExample)
EP (1) EP2994937B1 (enExample)
JP (1) JP6254259B2 (enExample)
KR (1) KR101755555B1 (enExample)
CN (1) CN105190888B (enExample)
WO (1) WO2014182449A1 (enExample)

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EP3035385A1 (en) * 2014-12-16 2016-06-22 IMEC vzw Semiconductor interposer comprising a schottky diode and a method for fabricating the interposer
US9583462B2 (en) * 2015-01-22 2017-02-28 Qualcomm Incorporated Damascene re-distribution layer (RDL) in fan out split die application
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US10559520B2 (en) * 2017-09-29 2020-02-11 Qualcomm Incorporated Bulk layer transfer processing with backside silicidation
CN108054139B (zh) * 2017-12-15 2020-12-18 浙江清华柔性电子技术研究院 Tsv转接板及其制备方法
CN108109961A (zh) * 2017-12-15 2018-06-01 西安科锐盛创新科技有限公司 基于二极管的集成电路抗静电转接板及其制备方法
CN108063114B (zh) * 2017-12-15 2019-11-22 台州第五空间航空科技有限公司 基于横向二极管的tsv转接板及其制备方法
CN108109962A (zh) * 2017-12-15 2018-06-01 西安科锐盛创新科技有限公司 集成电路抗静电转接板
CN108109957B (zh) * 2017-12-15 2020-12-25 浙江清华柔性电子技术研究院 系统级封装抗静电转接板
CN108109996B (zh) * 2017-12-15 2021-06-22 西安科锐盛创新科技有限公司 基于二极管的集成电路抗静电转接板及其制备方法
CN107994000B (zh) * 2017-12-15 2021-01-12 浙江清华柔性电子技术研究院 用于系统级封装的tsv转接板及其制备方法
CN108109988B (zh) * 2017-12-15 2020-12-22 浙江清华柔性电子技术研究院 用于系统级封装的防静电装置
CN108109953B (zh) * 2017-12-15 2020-12-25 浙江清华柔性电子技术研究院 用于系统级封装的tsv转接板
CN108122889B (zh) * 2017-12-15 2020-10-30 西安科锐盛创新科技有限公司 基于横向二极管的tsv转接板
CN107946240A (zh) * 2017-12-15 2018-04-20 西安科锐盛创新科技有限公司 Tsv转接板及其制备方法
CN108054133A (zh) * 2017-12-15 2018-05-18 西安科锐盛创新科技有限公司 集成电路抗静电转接板及其制备方法
CN108054156B (zh) * 2017-12-15 2021-09-03 西安科锐盛创新科技有限公司 用于系统级封装的防静电装置
CN109994425B (zh) * 2019-04-04 2021-07-30 上海迈铸半导体科技有限公司 填充基片的制备方法、填充基片及微孔互连结构制备方法
US11837641B2 (en) 2019-12-18 2023-12-05 Intel Corporation Gate-all-around integrated circuit structures having adjacent deep via substrate contacts for sub-fin electrical contact
US11264373B2 (en) 2019-12-21 2022-03-01 Intel Corporation Die backend diodes for electrostatic discharge (ESD) protection
US11424239B2 (en) * 2019-12-21 2022-08-23 Intel Corporation Diodes for package substrate electrostatic discharge (ESD) protection
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US12046567B2 (en) 2020-05-21 2024-07-23 Taiwan Semiconductor Manufacturing Company Ltd. Electrostatic discharge circuit and method of forming the same
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