KR101755555B1 - 정전기 방전 다이오드 - Google Patents

정전기 방전 다이오드 Download PDF

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KR101755555B1
KR101755555B1 KR1020157033748A KR20157033748A KR101755555B1 KR 101755555 B1 KR101755555 B1 KR 101755555B1 KR 1020157033748 A KR1020157033748 A KR 1020157033748A KR 20157033748 A KR20157033748 A KR 20157033748A KR 101755555 B1 KR101755555 B1 KR 101755555B1
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substrate
diode
backside
layer
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KR20160004356A (ko
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비드야 라마찬드란
브라이언 엠. 헨더슨
쉬쿤 구
치에우-구안 탄
정필 김
태현 김
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퀄컴 인코포레이티드
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    • H01L29/66128—
    • H01L23/481—
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    • H01L23/535—
    • H01L25/0657—
    • H01L27/0255—
    • H01L27/0296—
    • H01L27/0694—
    • H01L29/8611—
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/113—Isolations within a component, i.e. internal isolations
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00—Diodes
    • H10D8/01—Manufacture or treatment
    • H10D8/043—Manufacture or treatment of planar diodes
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    • H10D84/201—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits
    • H10D84/204—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits of combinations of diodes or capacitors or resistors
    • H10D84/221—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits of combinations of diodes or capacitors or resistors of only diodes
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    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
    • H10D89/611—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using diodes as protective elements
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    • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
    • H10D89/931—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs characterised by the dispositions of the protective arrangements
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    • H10W20/00—Interconnections in chips, wafers or substrates
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    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
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    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0245—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising use of blind vias during the manufacture
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    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0249—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias wherein the through-semiconductor via protrudes from backsides of the chips, wafers or substrates during the manufacture
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    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
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    • H10W42/00—Arrangements for protection of devices
    • H10W42/60—Arrangements for protection of devices protecting against electrostatic charges or discharges, e.g. Faraday shields
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H10W70/635—Through-vias
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    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/49—Adaptable interconnections, e.g. fuses or antifuses
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    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
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    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
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    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H10W72/01204—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using temporary auxiliary members, e.g. using sacrificial coatings or handle substrates
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    • H10W72/00—Interconnections or connectors in packages
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    • H10W72/241—Dispositions, e.g. layouts
    • H10W72/242—Dispositions, e.g. layouts relative to the surface, e.g. recessed, protruding
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    • H10W72/241—Dispositions, e.g. layouts
    • H10W72/244—Dispositions, e.g. layouts relative to underlying supporting features, e.g. bond pads, RDLs or vias
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/29—Bond pads specially adapted therefor
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    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
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    • H10W72/941—Dispositions of bond pads
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    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/297—Configurations of stacked chips characterised by the through-semiconductor vias [TSVs] in the stacked chips
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    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
KR1020157033748A 2013-05-06 2014-04-23 정전기 방전 다이오드 Expired - Fee Related KR101755555B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/887,723 2013-05-06
US13/887,723 US9093462B2 (en) 2013-05-06 2013-05-06 Electrostatic discharge diode
PCT/US2014/035076 WO2014182449A1 (en) 2013-05-06 2014-04-23 Electrostatic discharge diode

Publications (2)

Publication Number Publication Date
KR20160004356A KR20160004356A (ko) 2016-01-12
KR101755555B1 true KR101755555B1 (ko) 2017-07-07

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KR1020157033748A Expired - Fee Related KR101755555B1 (ko) 2013-05-06 2014-04-23 정전기 방전 다이오드

Country Status (6)

Country Link
US (2) US9093462B2 (enExample)
EP (1) EP2994937B1 (enExample)
JP (1) JP6254259B2 (enExample)
KR (1) KR101755555B1 (enExample)
CN (1) CN105190888B (enExample)
WO (1) WO2014182449A1 (enExample)

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US9786580B2 (en) 2013-11-15 2017-10-10 Taiwan Semiconductor Manufacturing Company, Ltd. Self-alignment for redistribution layer
TWI581325B (zh) 2014-11-12 2017-05-01 精材科技股份有限公司 晶片封裝體及其製造方法
EP3035385A1 (en) * 2014-12-16 2016-06-22 IMEC vzw Semiconductor interposer comprising a schottky diode and a method for fabricating the interposer
US9583462B2 (en) * 2015-01-22 2017-02-28 Qualcomm Incorporated Damascene re-distribution layer (RDL) in fan out split die application
US9922970B2 (en) 2015-02-13 2018-03-20 Qualcomm Incorporated Interposer having stacked devices
DE102016118709B3 (de) * 2016-10-04 2018-01-25 Infineon Technologies Ag Schutzvorrichtung vor elektrostatischer entladung und elektronische schaltvorrichtung
CN112164688B (zh) * 2017-07-21 2023-06-13 联华电子股份有限公司 芯片堆叠结构及管芯堆叠结构的制造方法
US10559520B2 (en) * 2017-09-29 2020-02-11 Qualcomm Incorporated Bulk layer transfer processing with backside silicidation
CN108054139B (zh) * 2017-12-15 2020-12-18 浙江清华柔性电子技术研究院 Tsv转接板及其制备方法
CN108109961A (zh) * 2017-12-15 2018-06-01 西安科锐盛创新科技有限公司 基于二极管的集成电路抗静电转接板及其制备方法
CN108063114B (zh) * 2017-12-15 2019-11-22 台州第五空间航空科技有限公司 基于横向二极管的tsv转接板及其制备方法
CN108109962A (zh) * 2017-12-15 2018-06-01 西安科锐盛创新科技有限公司 集成电路抗静电转接板
CN108109957B (zh) * 2017-12-15 2020-12-25 浙江清华柔性电子技术研究院 系统级封装抗静电转接板
CN108109996B (zh) * 2017-12-15 2021-06-22 西安科锐盛创新科技有限公司 基于二极管的集成电路抗静电转接板及其制备方法
CN107994000B (zh) * 2017-12-15 2021-01-12 浙江清华柔性电子技术研究院 用于系统级封装的tsv转接板及其制备方法
CN108109988B (zh) * 2017-12-15 2020-12-22 浙江清华柔性电子技术研究院 用于系统级封装的防静电装置
CN108109953B (zh) * 2017-12-15 2020-12-25 浙江清华柔性电子技术研究院 用于系统级封装的tsv转接板
CN108122889B (zh) * 2017-12-15 2020-10-30 西安科锐盛创新科技有限公司 基于横向二极管的tsv转接板
CN107946240A (zh) * 2017-12-15 2018-04-20 西安科锐盛创新科技有限公司 Tsv转接板及其制备方法
CN108054133A (zh) * 2017-12-15 2018-05-18 西安科锐盛创新科技有限公司 集成电路抗静电转接板及其制备方法
CN108054156B (zh) * 2017-12-15 2021-09-03 西安科锐盛创新科技有限公司 用于系统级封装的防静电装置
CN109994425B (zh) * 2019-04-04 2021-07-30 上海迈铸半导体科技有限公司 填充基片的制备方法、填充基片及微孔互连结构制备方法
US11837641B2 (en) 2019-12-18 2023-12-05 Intel Corporation Gate-all-around integrated circuit structures having adjacent deep via substrate contacts for sub-fin electrical contact
US11264373B2 (en) 2019-12-21 2022-03-01 Intel Corporation Die backend diodes for electrostatic discharge (ESD) protection
US11424239B2 (en) * 2019-12-21 2022-08-23 Intel Corporation Diodes for package substrate electrostatic discharge (ESD) protection
DE102021107976A1 (de) * 2020-05-21 2021-11-25 Taiwan Semiconductor Manufacturing Co., Ltd. Elektrostatische entladungsschaltung und verfahren zum bilden dergleichen
US12046567B2 (en) 2020-05-21 2024-07-23 Taiwan Semiconductor Manufacturing Company Ltd. Electrostatic discharge circuit and method of forming the same
US11342246B2 (en) * 2020-07-21 2022-05-24 Qualcomm Incorporated Multi-terminal integrated passive devices embedded on die and a method for fabricating the multi-terminal integrated passive devices
CN116529974A (zh) * 2020-11-16 2023-08-01 Tdk电子股份有限公司 带有esd保护元件的硅衬底
US11973075B2 (en) 2021-02-22 2024-04-30 Taiwan Semiconductor Manufacturing Company, Ltd. Dual substrate side ESD diode for high speed circuit
WO2025258351A1 (ja) * 2024-06-10 2025-12-18 ソニーセミコンダクタソリューションズ株式会社 半導体装置、固体撮像素子及び電子機器

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