JP6244138B2 - 配線基板及び配線基板の製造方法 - Google Patents

配線基板及び配線基板の製造方法 Download PDF

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Publication number
JP6244138B2
JP6244138B2 JP2013170366A JP2013170366A JP6244138B2 JP 6244138 B2 JP6244138 B2 JP 6244138B2 JP 2013170366 A JP2013170366 A JP 2013170366A JP 2013170366 A JP2013170366 A JP 2013170366A JP 6244138 B2 JP6244138 B2 JP 6244138B2
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JP
Japan
Prior art keywords
layer
wiring
insulating layer
hole
insulating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2013170366A
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English (en)
Japanese (ja)
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JP2015041630A5 (enExample
JP2015041630A (ja
Inventor
国本　裕治
裕治 国本
清水　規良
規良 清水
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Original Assignee
Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2013170366A priority Critical patent/JP6244138B2/ja
Priority to US14/459,706 priority patent/US9332658B2/en
Publication of JP2015041630A publication Critical patent/JP2015041630A/ja
Publication of JP2015041630A5 publication Critical patent/JP2015041630A5/ja
Application granted granted Critical
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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09509—Blind vias, i.e. vias having one side closed
    • H05K2201/09518—Deep blind vias, i.e. blind vias connecting the surface circuit to circuit layers deeper than the first buried circuit layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09609—Via grid, i.e. two-dimensional array of vias or holes in a single plane

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structure Of Printed Boards (AREA)
JP2013170366A 2013-08-20 2013-08-20 配線基板及び配線基板の製造方法 Active JP6244138B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2013170366A JP6244138B2 (ja) 2013-08-20 2013-08-20 配線基板及び配線基板の製造方法
US14/459,706 US9332658B2 (en) 2013-08-20 2014-08-14 Wiring board, semiconductor device, and method for manufacturing wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2013170366A JP6244138B2 (ja) 2013-08-20 2013-08-20 配線基板及び配線基板の製造方法

Publications (3)

Publication Number Publication Date
JP2015041630A JP2015041630A (ja) 2015-03-02
JP2015041630A5 JP2015041630A5 (enExample) 2016-07-14
JP6244138B2 true JP6244138B2 (ja) 2017-12-06

Family

ID=52479355

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2013170366A Active JP6244138B2 (ja) 2013-08-20 2013-08-20 配線基板及び配線基板の製造方法

Country Status (2)

Country Link
US (1) US9332658B2 (enExample)
JP (1) JP6244138B2 (enExample)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN205726710U (zh) * 2014-02-07 2016-11-23 株式会社村田制作所 树脂多层基板及元器件模块
JP2017009725A (ja) * 2015-06-19 2017-01-12 ソニー株式会社 表示装置
WO2018128082A1 (ja) * 2017-01-05 2018-07-12 住友電工プリントサーキット株式会社 フレキシブルプリント配線板
JP2019062092A (ja) * 2017-09-27 2019-04-18 イビデン株式会社 プリント配線板
US10892213B2 (en) * 2018-12-28 2021-01-12 Advanced Semiconductor Engineering, Inc. Wiring structure and method for manufacturing the same
US11417821B2 (en) * 2019-03-07 2022-08-16 Northrop Grumman Systems Corporation Superconductor ground plane patterning geometries that attract magnetic flux
US11139232B2 (en) * 2020-03-06 2021-10-05 Advanced Semiconductor Engineering, Inc. Wiring structure and method for manufacturing the same
US11398419B2 (en) * 2020-07-16 2022-07-26 Advanced Semiconductor Engineering, Inc. Wiring structure and method for manufacturing the same
JP2022107282A (ja) 2021-01-08 2022-07-21 イビデン株式会社 配線基板

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3325351B2 (ja) * 1993-08-18 2002-09-17 株式会社東芝 半導体装置
JPH11112142A (ja) * 1997-10-01 1999-04-23 Kyocera Corp 多層配線基板
JP2000133941A (ja) * 1998-10-28 2000-05-12 Ibiden Co Ltd 多層ビルドアップ配線板
JP2000101237A (ja) 1998-09-18 2000-04-07 Fujitsu Ltd ビルドアップ基板
US6184477B1 (en) * 1998-12-02 2001-02-06 Kyocera Corporation Multi-layer circuit substrate having orthogonal grid ground and power planes
US6586682B2 (en) * 2000-02-23 2003-07-01 Kulicke & Soffa Holdings, Inc. Printed wiring board with controlled line impedance
US6621384B1 (en) * 2000-12-28 2003-09-16 Nortel Networks Limited Technology implementation of suspended stripline within multi-layer substrate used to vary time delay and to maximize the reach of signals with high data rates or high frequencies
JP2003224227A (ja) * 2002-01-30 2003-08-08 Kyocera Corp 配線基板およびこれを用いた半導体装置
EP1720389B1 (en) * 2005-04-25 2019-07-03 Brother Kogyo Kabushiki Kaisha Method for forming pattern and a wired board
US8115113B2 (en) * 2007-11-30 2012-02-14 Ibiden Co., Ltd. Multilayer printed wiring board with a built-in capacitor
WO2011089936A1 (ja) * 2010-01-22 2011-07-28 日本電気株式会社 機能素子内蔵基板及び配線基板
JP5473074B2 (ja) 2010-10-29 2014-04-16 京セラＳｌｃテクノロジー株式会社 配線基板

Also Published As

Publication number Publication date
JP2015041630A (ja) 2015-03-02
US9332658B2 (en) 2016-05-03
US20150053460A1 (en) 2015-02-26

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