JP6234132B2 - 配線基板の製造方法 - Google Patents

配線基板の製造方法 Download PDF

Info

Publication number
JP6234132B2
JP6234132B2 JP2013193882A JP2013193882A JP6234132B2 JP 6234132 B2 JP6234132 B2 JP 6234132B2 JP 2013193882 A JP2013193882 A JP 2013193882A JP 2013193882 A JP2013193882 A JP 2013193882A JP 6234132 B2 JP6234132 B2 JP 6234132B2
Authority
JP
Japan
Prior art keywords
layer
opening
insulating layer
conductive layer
wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2013193882A
Other languages
English (en)
Japanese (ja)
Other versions
JP2015060960A (ja
Inventor
佐藤　圭吾
圭吾 佐藤
章司 渡辺
章司 渡辺
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Original Assignee
Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2013193882A priority Critical patent/JP6234132B2/ja
Priority to KR1020140120781A priority patent/KR102054198B1/ko
Priority to TW103132035A priority patent/TWI635790B/zh
Publication of JP2015060960A publication Critical patent/JP2015060960A/ja
Application granted granted Critical
Publication of JP6234132B2 publication Critical patent/JP6234132B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
JP2013193882A 2013-09-19 2013-09-19 配線基板の製造方法 Active JP6234132B2 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2013193882A JP6234132B2 (ja) 2013-09-19 2013-09-19 配線基板の製造方法
KR1020140120781A KR102054198B1 (ko) 2013-09-19 2014-09-12 배선 기판의 제조 방법
TW103132035A TWI635790B (zh) 2013-09-19 2014-09-17 佈線基板之製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2013193882A JP6234132B2 (ja) 2013-09-19 2013-09-19 配線基板の製造方法

Publications (2)

Publication Number Publication Date
JP2015060960A JP2015060960A (ja) 2015-03-30
JP6234132B2 true JP6234132B2 (ja) 2017-11-22

Family

ID=52818247

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2013193882A Active JP6234132B2 (ja) 2013-09-19 2013-09-19 配線基板の製造方法

Country Status (3)

Country Link
JP (1) JP6234132B2 (ko)
KR (1) KR102054198B1 (ko)
TW (1) TWI635790B (ko)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7007882B2 (ja) * 2017-12-08 2022-01-25 新光電気工業株式会社 配線基板及びその製造方法

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3299243B2 (ja) 1996-12-19 2002-07-08 イビデン株式会社 多層プリント配線板の製造方法
JP2002241440A (ja) * 2001-02-19 2002-08-28 Toppan Printing Co Ltd アルカリ可溶性重合体及び感光性樹脂組成物
JP2004055618A (ja) * 2002-07-16 2004-02-19 Kanegafuchi Chem Ind Co Ltd 多層プリント配線板の製造方法
JP4328196B2 (ja) 2003-12-24 2009-09-09 京セラ株式会社 配線基板及びその製造方法並びに電気装置
JP2006108165A (ja) * 2004-09-30 2006-04-20 Sumitomo Bakelite Co Ltd 樹脂組成物、積層体、配線板および配線板の製造方法
JP2008218540A (ja) 2007-03-01 2008-09-18 Matsushita Electric Ind Co Ltd 配線基板の製造方法
TWI455671B (zh) * 2007-10-23 2014-10-01 Ube Industries 印刷電路板之製造方法
EP2204079B1 (en) * 2007-10-26 2013-05-01 E. I. du Pont de Nemours and Company Asymmetric dielectric films and process for forming such a film
JP5322531B2 (ja) 2008-05-27 2013-10-23 新光電気工業株式会社 配線基板の製造方法
JP5231340B2 (ja) * 2009-06-11 2013-07-10 新光電気工業株式会社 配線基板の製造方法
JP5539150B2 (ja) * 2010-10-25 2014-07-02 矢崎総業株式会社 配線基板の製造方法
JP2013172137A (ja) * 2012-02-23 2013-09-02 Kyocer Slc Technologies Corp 配線基板およびそれを用いたプローブカード
JP5479551B2 (ja) * 2012-09-14 2014-04-23 新光電気工業株式会社 配線基板の製造方法

Also Published As

Publication number Publication date
KR102054198B1 (ko) 2019-12-11
TW201524299A (zh) 2015-06-16
TWI635790B (zh) 2018-09-11
JP2015060960A (ja) 2015-03-30
KR20150032629A (ko) 2015-03-27

Similar Documents

Publication Publication Date Title
US9756735B2 (en) Method for manufacturing printed wiring board
JP6711509B2 (ja) プリント回路基板、半導体パッケージ及びその製造方法
US20100139969A1 (en) Printed circuit board comprising metal bump and method of manufacturing the same
US20140102767A1 (en) Multi-layer type printed circuit board and method of manufacturing the same
JP6795137B2 (ja) 電子素子内蔵型印刷回路基板の製造方法
KR20030063140A (ko) 프린트 기판과 그 제조 방법
WO2018110437A1 (ja) 配線基板、多層配線基板、及び配線基板の製造方法
US10763031B2 (en) Method of manufacturing an inductor
US10674608B2 (en) Printed circuit board and manufacturing method thereof
JP2006286724A (ja) 配線基板及びその製造方法
JP2009283671A (ja) プリント配線板の製造方法
TW201444440A (zh) 配線基板及其製造方法
KR20150031649A (ko) 인쇄회로기판 및 인쇄회로기판 제조 방법
JP6234132B2 (ja) 配線基板の製造方法
KR101222828B1 (ko) 코어리스 기판의 제조방법
JP2000269647A (ja) 片面回路基板、多層プリント配線板およびその製造方法
JP4797310B2 (ja) アライメントマーク
JP2014222733A (ja) プリント配線板およびその製造方法
JP4483247B2 (ja) 多層フレキシブル配線基板の製造方法及び多層フレキシブル配線基板
KR101015780B1 (ko) 미세 패턴을 포함하는 인쇄회로기판 및 그 제조 방법
JP2017005096A (ja) 配線基板の製造方法
JP4492071B2 (ja) 配線基板の製造方法
KR200412591Y1 (ko) 내층 알씨씨에 범퍼가 구비된 범프 홀을 갖는 다층인쇄회로기판
JP2005223010A (ja) 多層配線基板の製造方法
KR20130116981A (ko) 스터브 제거기술 및 이를 적용한 초박형 다층인쇄회로기판 제조방법

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20160608

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20170721

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20170801

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20170824

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20171003

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20171024

R150 Certificate of patent or registration of utility model

Ref document number: 6234132

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150