JP6170967B2 - ハンダ相互接続パッド構造及びこれの製造方法 - Google Patents
ハンダ相互接続パッド構造及びこれの製造方法 Download PDFInfo
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- JP6170967B2 JP6170967B2 JP2015122799A JP2015122799A JP6170967B2 JP 6170967 B2 JP6170967 B2 JP 6170967B2 JP 2015122799 A JP2015122799 A JP 2015122799A JP 2015122799 A JP2015122799 A JP 2015122799A JP 6170967 B2 JP6170967 B2 JP 6170967B2
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- pad
- passivation layer
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- opening
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- H01L2924/1904—Component type
- H01L2924/19043—Component type being a resistor
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Description
115は、無機誘電体材料を含むことができる。1つの例において、誘電体パッシベーション層115は、第1番目に形成された二酸化シリコン層の上面に第2番目に形成された窒化シリコン層を含む。1つの例において、端子パッド120は、アルミニウムを含む。1つの例において、有機誘電体層125はポリイミドを含む。1つの例において、電流拡散パッド130Aは、アルミニウムを含む。1つの例において、図15に示されているように、電流拡散パッド130Aは、下側保護層及び上側保護層の間の銅層、ニッケル層、銅の層とニッケルの層の複合層、若しくは銅及びニッケルの混合物を含む。下側保護層及び上側保護層は、ハンダ・バンプ(図11参照)の金属と電流拡散パッド130Aのコアの金属との間で金属間化合物が形成されるのを形成を防止する。1つの例において、ハンダ・バンプ・パッド130Bは、銅及びニッケルの混合物、ニッケルのみ、銅のみ、若しくは銅及び金の混合物を含む。電流拡散パッド130Aまたはハンダ・バンプ130Bあるいはその両方が2つの金属の混合物である場合には、これらは、同時に付着され若しくは同時にメッキされる。
導電性電流拡散パッドは、
アルミニウム層から成る第1構造と、
ニッケル層と、このニッケル層及び導電性ハンダ・バンプ・パッドの間に配置され錫に対する拡散バリアとして働く拡散バリア層とを含む第2構造と、
銅層と、この銅層及び導電性ハンダ・バンプ・パッドの間に配置され錫に対する拡散バリアとして働く拡散バリア層とを含む第3構造と、
ニッケル及び銅の混合層と、この混合層及び導電性ハンダ・バンプ・パッドの間に配置され、錫に対する拡散バリアとして働く拡散バリア層とを含む第4構造と、
ニッケル層及び銅層から成る層と、この層及び導電性ハンダ・バンプ・パッドの間に配置され錫に対する拡散バリアとして働く拡散バリア層とを含む第5構造とのうちいずれかの構造を有する。
導電性電流拡散パッドは、
拡散バリア層及びアルミニウム層を有し、このアルミニウム層が拡散バリア層及び導電性ハンダ・バンプ・パッドの間に配置されている第6構造と、
第1拡散バリア層、ニッケル層及び錫に対する拡散バリアとして働く第2拡散バリア層を有し、ニッケル層は第1拡散バリア層及び第2拡散バリア層の間にあり、第2拡散バリア層がニッケル層及びハンダ・バンプ・パッドの間に配置されている第7構造と、
第1拡散バリア層、銅層及び錫に対する拡散バリアとして働く第2拡散バリア層を有し、銅層は第1拡散バリア層及び第2拡散バリア層の間にあり、第2拡散バリア層が銅層及びハンダ・バンプ・パッドの間に配置されている第8構造と、
第1拡散バリア層、ニッケル及び銅の混合層及び錫に対する拡散バリアとして働く第2拡散バリア層を有し、混合層は第1拡散バリア層及び第2拡散バリア層の間にあり、第2拡散バリア層が混合層及びハンダ・バンプ・パッドの間に配置されている第9構造と、
第1拡散バリア層、ニッケル層、銅層及び錫に対する拡散バリアとして働く第2拡散バリア層を有し、ニッケル層及び銅層は第1拡散バリア層及び第2拡散バリア層の間にあり、第2拡散バリア層が銅層層及びハンダ・バンプ・パッドの間に配置されている第10構造とのうちいずれかの構造を有する。
られる。ハンダ・バンプは図14に示されている。
ワイヤ110に対して非反応性である場合には、下側保護層185を省略することができる。下側保護層185は、銅に対する拡散バリア又は接着強化層あるいはその両方をして働く。
たフォトレジスト層を形成し、そして溶剤を使用するウエット・エッチングを使用して有機誘電体パッシベーション層125を等方性エッチングすることにより形成される。等方性エッチングは、図4,図6,図11及び図12に示されているように、開口TVの凹状の側壁を形成し、そして有機誘電体パッシベーション層125の上面及び側壁の間の境界に尖端部を形成する。次いで、有機誘電体パッシベーション層125は加熱若しくは紫外線により硬化される。
105 層間誘電体層
110 ワイヤ
115 誘電体パッシベーション層
120 導電性端子パッド
125 有機誘電体パッシベーション層
130A 電流拡散パッド
130B ハンダ・バンプ・パッド
140 側壁
145 上面
170 ハンダ・バンプ
Claims (4)
- 基板上に延びるように設けられた有機誘電体パッシベーション層と、
前記有機誘電体パッシベーション層の上面に設けられた導電性電流拡散パッドと、
前記導電性電流拡散パッド上に設けられ1つ以上の層を有する導電性ハンダ・バンプ・パッドと、
前記導電性ハンダ・バンプ・パッド上に設けられ錫を含む導電性ハンダ・バンプと、を備え、
前記導電性電流拡散パッドは1つ以上の層を有し、前記導電性電流拡散パッドの前記1つ以上の層の少なくとも1つは、錫と金属間化合物を形成しない材料から成り、又は、前記導電性電流拡散パッドの前記1つ以上の層の少なくとも1つは、錫に対して拡散バリアとして働く材料でありそして前記導電性ハンダ・バンプ・パッドに隣接し、
前記基板に設けられた層間誘電体層内の導電性ワイヤと、
前記導電性ワイヤの上面の一部を露出する第1開口を有し、前記層間誘電体層の上面及び前記ワイヤの前記一部以外の上面に設けられた誘電体パッシベーション層と、を備え、
前記有機誘電体パッシベーション層は、前記導電性ワイヤの前記露出された一部を露出する第2開口を有し、前記第1開口を囲む前記誘電体パッシベーション層は前記第2開口内にあり、
前記導電性電流拡散パッドは、前記第1開口内に露出された前記導電性ワイヤの前記露出された一部に物理的に且つ電気的に接触し、前記誘電体パッシベーション層のうち前記第1開口を囲む領域に物理的に接触し、そして前記有機誘電体パッシベーション層の上面及び前記第2開口の側壁に物理的に接触し、
前記有機誘電体パッシベーション層の前記第2開口の側壁のうち、前記有機誘電体パッシベーション層の上面に隣接する上側領域は凸状であり、前記第2開口の側壁のうち、前記誘電体パッシベーション層に隣接する下側領域は凹状であり、
前記導電性電流拡散パッドは、アルミニウム層を含む、構造。 - 前記導電性ワイヤは銅である、請求項1に記載の構造。
- (a)基板上に延びる有機誘電体パッシベーション層を形成するステップと、
(b)ステップ(a)の後に、前記有機誘電体パッシベーション層の上面に導電性電流拡散パッドを形成するステップと、
(c)ステップ(b)の後に、前記導電性電流拡散パッドの上面に1つ以上の層を有する導電性ハンダ・バンプ・パッドを形成するステップと、
(d)ステップ(c)の後に、錫を含む導電性ハンダ・バンプを前記導電性ハンダ・バンプ・パッドの上に形成するステップと、を含み、
前記導電性電流拡散パッドは1つ以上の層を含み、前記導電性電流拡散パッドの前記1つ以上の層の少なくとも1つは、錫と金属間化合物を形成しない材料から成り、又は、前記導電性電流拡散パッドの前記1つ以上の層の少なくとも1つは、錫に対して拡散バリアとして働く材料でありそして前記導電性ハンダ・バンプ・パッドに隣接し、
前記ステップ(a)の前に、
前記基板上の層間誘電体層内に導電性ワイヤを形成するステップと、
前記導電性ワイヤの上面及び前記層間誘電体層の上面に誘電体パッシベーション層を形成するステップと、
前記誘電体パッシベーション層に、前記導電性ワイヤの一部を露出する第1開口を形成するステップと、を行い、そして
前記ステップ(a)と前記ステップ(b)との間に、前記有機誘電体パッシベーション層に第2開口を形成するステップを行い、
前記導電性ワイヤの上面の中央領域は前記第1開口内にあり、そして前記第1開口を取り囲む前記誘電体パッシベーション層の領域は前記第2開口内にあり、
前記導電性電流拡散パッドは、前記第1開口内の前記導電性ワイヤの上面に物理的に且つ電気的に接触し、前記第2開口内に位置する前記第1開口を取り囲む前記誘電体パッシベーション層に物理的に接触し、そして前記第2開口の縁に隣接する前記有機誘電体パッシベーション層の上面に物理的に接触し、
前記第2開口を形成するステップは、
前記有機誘電体パッシベーション層の上面に設けられたパターン化されたフォトマスクを介して前記有機誘電体パッシベーション層を等方性エッチングするステップと、
前記フォトマスクを除去するステップと、
前記有機誘電体パッシベーション層の上面及び前記側壁をスパッタリングするステップと、を含み、
前記有機誘電体パッシベーション層の前記第2開口の側壁のうち、前記有機誘電体パッシベーション層の上面に隣接する上側領域は凸状であり、前記第2開口の側壁のうち、前記誘電体パッシベーション層に隣接する下側領域は凹状であり、
前記導電性電流拡散パッドは、アルミニウム層を含む、方法。 - 前記導電性ワイヤは銅である、請求項3に記載の方法。
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DE102006001254B4 (de) * | 2005-11-30 | 2015-03-19 | Globalfoundries Inc. | Verfahren zur Herstellung von Lotkugeln mit einer stabilen Oxidschicht durch Steuern der Aufschmelzumgebung |
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TWI264788B (en) * | 2005-12-22 | 2006-10-21 | Advanced Semiconductor Eng | Chip structure and chip manufacturing process |
US7863183B2 (en) | 2006-01-18 | 2011-01-04 | International Business Machines Corporation | Method for fabricating last level copper-to-C4 connection with interfacial cap structure |
KR100859641B1 (ko) * | 2006-02-20 | 2008-09-23 | 주식회사 네패스 | 금속간 화합물 성장을 억제시킨 솔더 범프가 형성된 반도체칩 및 제조 방법 |
JP5050384B2 (ja) * | 2006-03-31 | 2012-10-17 | 富士通セミコンダクター株式会社 | 半導体装置およびその製造方法 |
US7868453B2 (en) | 2008-02-15 | 2011-01-11 | International Business Machines Corporation | Solder interconnect pads with current spreading layers |
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- 2009-02-11 WO PCT/US2009/033724 patent/WO2009102742A1/en active Application Filing
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Also Published As
Publication number | Publication date |
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KR101456321B1 (ko) | 2014-11-03 |
TW201001660A (en) | 2010-01-01 |
US20130105971A1 (en) | 2013-05-02 |
WO2009102742A1 (en) | 2009-08-20 |
KR20100123840A (ko) | 2010-11-25 |
US7868453B2 (en) | 2011-01-11 |
US8669660B2 (en) | 2014-03-11 |
US20110006421A1 (en) | 2011-01-13 |
US20120126405A1 (en) | 2012-05-24 |
US8138602B2 (en) | 2012-03-20 |
JP2011512679A (ja) | 2011-04-21 |
JP2015181197A (ja) | 2015-10-15 |
US20090206479A1 (en) | 2009-08-20 |
JP5800506B2 (ja) | 2015-10-28 |
TWI423413B (zh) | 2014-01-11 |
US8338947B2 (en) | 2012-12-25 |
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