CN109075186B - 超导凸起接合件 - Google Patents

超导凸起接合件 Download PDF

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Publication number
CN109075186B
CN109075186B CN201580085714.XA CN201580085714A CN109075186B CN 109075186 B CN109075186 B CN 109075186B CN 201580085714 A CN201580085714 A CN 201580085714A CN 109075186 B CN109075186 B CN 109075186B
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chip
circuit element
barrier layer
quantum
interconnect pad
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CN109075186A (zh
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乔舒亚·优素夫·穆图什
埃里克·安东尼·卢塞罗
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Google LLC
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Abstract

本公开提供了一种设备(100)，所述设备(100)包括：第一芯片(104)，所述第一芯片(104)包括第一电路元件(112)、与所述第一电路元件电接触(118)的第一互连焊盘(116)、和在所述第一互连焊盘上的阻挡物层(120)；在所述阻挡物层上的超导凸起接合件(106)；以及第二芯片(102)，所述第二芯片(102)通过所述超导凸起接合件连结至所述第一芯片，所述第二芯片具有第一量子电路元件(108)，其中，所述超导凸起接合件在所述第一电路元件与所述第一量子电路元件之间提供电连接。

Description

超导凸起接合件
技术领域
本公开涉及超导凸起接合件。
背景技术
量子计算是一种利用诸如基态叠加和量子纠缠等量子效应来执行比经典数字计算机更有效的某些计算的相对新的计算方法。与存储和操纵位(例如，“1”和“0”)形式的信息的数字计算机相比，量子计算系统可以使用量子比特来操纵信息。量子比特可以涉及使多种状态(例如，在“0”和“1”状态下的数据)能够叠加和/或使本身处于多种状态下的数据能够叠加的量子设备。根据传统的术语，在量子系统中的“0”和“1”状态的叠加可以被表示为例如α︱0＞+β︳0＞。数字计算机的“0”和“1”状态分别类似于量子比特的︱0＞和︱1＞基态。值︱α︱2表示量子比特处于︱0＞状态的概率，而值︱β︱2表示量子比特处于︱1＞基态的概率。
发明内容
一般而言，在一些方面中，本公开涉及一种或者多种设备，该设备包括：第一芯片，该第一芯片包括第一电路元件、与第一电路元件电接触的第一互连焊盘、和在第一互连焊盘上的阻挡物层；在阻挡物层上的超导凸起接合件；以及第二芯片，该第二芯片通过超导凸起接合件连结至第一芯片，第二芯片包括第一量子电路元件，其中，超导凸起接合件在第一电路元件与第一量子电路元件之间提供电连接。
设备的实施方式可以包括以下特征中的一个或多个。例如，在一些实施方式中，第一互连焊盘包括铝。
在一些实施方式中，阻挡物层包括氮化钛。
在一些实施方式中，超导凸起接合件包括铟。
在一些实施方式中，第一电路元件包括快速单通量量子(RSFQ)设备。
在一些实施方式中，第一电路元件包括第二量子电路元件。
在一些实施方式中，第一芯片和第二芯片中的至少一个包括硅衬底。
在一些实施方式中，第一芯片和第二芯片中的至少一个包括蓝宝石衬底。
在一些实施方式中，第一芯片的第一表面与第二芯片的第一表面间隔开并且面向第二芯片的第一表面以形成间隙，并且在第一芯片的第一表面与第二芯片的第一表面之间的间隙的厚度在约5微米与约10微米之间。
在一些实施方式中，第一芯片的第一表面与第二芯片的第一表面间隔开并且面向第二芯片的第一表面以形成间隙，并且在第一芯片的第一表面与第二芯片的第一表面之间的间隙的厚度为约1微米。
在另一方面中，本公开的主题可以体现为方法，该方法包括：提供包括第一电路元件的第一芯片；在第一芯片的第一表面上形成第一铝互连焊盘从而将第一铝互连焊盘电连接至第一电路元件；在第一铝互连焊盘上形成第一氮化钛阻挡物层；提供包括第二电路元件的第二芯片；形成铟凸起接合件；以及用铟凸起接合件将第一芯片接合至第二芯片从而将第一电路元件电连接至第二电路元件，其中，将第一芯片接合至第二芯片是在室温下进行的。
方法的实施方式可以包括以下特征中的一个或多个。例如，在一些实施方式中，室温在约18℃与约30℃之间。
在一些实施方式中，方法进一步包括：在形成第一氮化钛阻挡物层之前从第一铝互连焊盘去除原生氧化物。去除原生氧化物包括：对第一铝互连焊盘的表面进行离子研磨。
在一些实施方式中，形成第一氮化钛阻挡物包括：将氮化钛反应溅射在第一铝互连焊盘上。在一些实施方式中，方法进一步包括：在将第一芯片接合至第二芯片之前对第一氮化铝阻挡物层的表面进行离子研磨。
在一些实施方式中，方法进一步包括：将铟凸起接合件的表面暴露于H2等离子。
在一些实施方式中，方法进一步包括：在第二芯片的第一表面上形成第二铝互连焊盘从而将第二铝互连焊盘电连接至第二电路元件；以及在第二芯片的第二铝互连焊盘上形成第二氮化钛阻挡物层。方法可以进一步包括：在形成第二氮化钛阻挡物层之前从第二芯片的第二铝互连焊盘去除原生氧化物。从第二铝互连焊盘去除原生氧化物包括：对第二铝互连焊盘的表面进行离子研磨。
在一些实施方式中，在第二铝互连焊盘上形成第二氮化钛阻挡物层包括：将氮化钛反应溅射在第二铝互连焊盘上。
在一些实施方式中，方法进一步包括：在将第一芯片接合至第二芯片之前对第二氮化铝阻挡物层的表面进行离子研磨。
在一些实施方式中，形成铟凸起接合件包括：将铟沉积在第一氮化钛阻挡物上、在第二氮化钛阻挡物上、或者在第一氮化钛阻挡物和第二氮化钛阻挡物两者上。
在一些实施方式中，第一电路元件包括快速单通量量子(RSFQ)设备，并且第二电路元件包括量子电路元件。
在一些实施方式中，第一电路元件包括第一量子电路元件，并且第二电路元件包括第二量子电路元件。
一般而言，在另一方面中，本公开的主题涵盖方法，该方法包括：提供包括第一电路元件的第一芯片；在第一芯片上形成互连焊盘从而将互连焊盘电连接至第一电路元件；在互连焊盘上形成阻挡物层；提供包括量子电路元件的第二芯片；形成超导凸起接合件；以及用超导凸起接合件将第一芯片接合至第二芯片从而通过超导凸起接合件将第一电路元件电连接至量子电路元件。
方法的实施方式可以包括以下特征中的一个或多个。例如，在一些实施方式中，形成超导凸起接合件包括：将超导体材料沉积在第一芯片的阻挡物层上、在第二芯片上、或者在第一芯片的阻挡物层和第二芯片两者上。
一般而言，在另一方面中，本公开的主题可以体现为操作包括通过超导凸起接合件连接至包括第一量子电路元件的第二芯片的包括第一电路元件的第一芯片的设备的一种或者多种方法，其中，一种或者多种方法包括：通过超导凸起接合件在第二芯片与第一芯片之间传输数据。第一芯片可以进一步包括与第一电路元件电接触的第一互连焊盘和在第一互连焊盘上的阻挡物层，其中，超导凸起接合件设置在阻挡物层上以在第一电路元件与第一量子电路元件之间提供电连接。
方法的实施方式可以包括以下特征中的一个或多个。例如，在一些实施方式中，方法可以进一步包括操作第一量子电路元件以产生数据，其中，传输数据包括：将数据从第二芯片的第一量子电路元件传输至第一芯片的第一电路元件。在一些实施方式中，方法进一步包括操作第一电路元件以产生数据，其中，传输数据包括：将数据从第一芯片的第一电路元件传输至第二芯片的第一量子电路元件。
各种实施例和实施方式可以包括以下特征中的一个或者多个特征。例如，在一些实施方式中，设备和方法允许通过3D集成来提高量子比特密度和/或量子比特耦合。此外，在一些实施方式中，设备和方法允许在降低与处理方法和材料相关联的损耗的同时实现3D集成。
在附图和以下描述中陈述了本发明的一个或者多个实施例的细节。本发明的其它特征、目的和优点通过说明书和附图并且通过权利要求书将变得显而易见。
附图说明
图1是图示了包括通过一个或者多个超导凸起接合件而被接合至第二芯片的第一芯片的设备的示例的示意图。
图2是图示了用超导凸起接合件将第一芯片接合至第二芯片以形成设备的示例过程的流程图。
图3A至图3E是图示了在图2中阐述的制造过程的示意图。
具体实施方式
量子计算需要条理清楚地处理存储在量子计算机的量子比特中的量子信息。在某些类型的量子计算处理器(诸如，量子退火机)中，量子处理器的量子比特以可控方式被耦合在一起从而使每个量子比特的量子状态影响与其耦合的其它量子比特的对应量子状态。根据处理器设计，选定架构可以限制用于耦合的量子比特的密度和总数，从而限制处理器执行需要多个量子比特的复杂问题的能力。此外，在某些量子计算设计中，量子比特可能遭受因为与二能级系统交互而产生的能量损耗和退相干。例如，在使用由超导体材料形成的量子比特的量子计算机中，例如，来自与量子计算机通信的经典电路元件和来自在经典电路元件与量子电路元件之间的连接的有损非超导材料的存在可能导致退相干增加。为了提高量子比特密度和增加用于在量子处理器(诸如，包括超导量子电路元件的量子退火机)中耦合的量子比特的数量，处理器和相关联的电路元件可以使用3D集成来构建。也就是说，除了在沿一个和/或两个维度(例如，x方向和/或y方向)延伸的芯片的单个平面内制造处理器的量子电路元件之外，量子电路元件也可以形成在沿第三维度(例如，z方向)耦合在一起的多个芯片中。在没有引入有损处理/电介质的情况下，实现3D集成的方法是使用凸起接合件来耦合芯片，在凸起接合件中，芯片通过超导凸起接合件彼此连结。同样，在一些实施方式中，包括经典电路元件的芯片也可以使用3D集成和超导凸起接合件而被耦合至包括量子电路元件的芯片。通过使用用于耦合的超导凸起接合件，可以实现减少也可能与有损非超导材料一起出现的能量损耗和退相干。此外，为了避免在超导凸起接合件和芯片上的任何底层互连焊盘之间形成合金，提供阻挡物层以防止来自凸起接合件的材料扩散到互连焊盘上，反之亦然。
图1是设备100的示例，该设备100包括通过一个或者多个超导凸起接合件106连结(例如，接合)至第二芯片104的第一芯片102。每个芯片都可以包括用于执行数据处理操作的一个或者多个电路元件。例如，第一芯片102可以包括形成在衬底110上的一个或者多个第一电路元件108。例如，第一电路元件108可以包括用于执行量子处理操作的量子电路元件。也就是说，量子电路元件可以配置为使用诸如叠加和量子纠缠等量子力学现象以不确定的方式对数据进行操作。诸如量子比特等某些量子电路元件可以配置为同时表示处于一种以上的状态下的信息并且对该信息进行操作。在一些实施方式中，量子电路元件包括部分由超导材料形成的电路元件，例如，超导共面波导、量子LC振荡器、通量量子比特、超导量子干涉设备(SQUIDS)(例如，RF-SQUID或者DC-SQUID)等。超导体材料包括在低于对应超导临界温度的条件下表现出超导性能的材料，诸如，铝(例如，1.2开的超导临界温度)或者铌(例如，9.3开的超导临界温度)。根据元件类型和设计，电路元件108可以由一层或者多层材料(诸如，例如，超导材料和电介质)形成。为了减少能量损耗和退相干，量子电路元件的衬底110可以由低损耗介电材料(诸如，单晶硅或者蓝宝石)形成。
第二芯片104包括形成在衬底114上或者内的一个或者多个第二电路元件112。第二电路元件112也可以包括本文所描述的量子电路元件。同样，衬底114可以由适合于量子电路元件的低损耗介电材料(诸如，单晶硅或者蓝宝石)形成。可替代地，第二电路元件112包括经典电路元件。经典电路元件通常以不确定的方式来处理数据并且包括例如电路元件，诸如，快速单通量量子(RSFQ)设备。RSFQ是使用超导设备(即，约瑟夫森结)来处理数字信号的数字电子技术。在RSFQ逻辑中，信息以磁通量量子的形式被存储并且以单通量量子(SFQ)电压脉冲的形式被传输。约瑟夫森结是RSFQ电子器件的有源元件，正如晶体管是半导体电子器件的有源元件。RSFQ是超导或者SFQ逻辑的家族。例如，其它包括相互量子逻辑(RQL)和ERSFQ，其是不使用偏压电阻器的RSFQ的节能版本。经典电路元件的其它示例包括数字或者模拟互补金属氧化物半导体(CMOS)器件。由数字电路元件操纵的数据通常用两种不同状态中的任何一种状态(例如，0或者1)表示。经典电路元件112可以配置为通过对数据执行基本算术、逻辑和输入/输出操作来执行计算机程序的指令，在该基本算术、逻辑和输入/输出操作中，数据用模拟或者数字形式表示。在一些实施方式中，第二芯片104的经典电路元件112可以用于通过由超导凸起接合件106建立的连接来发送和接收来自在第一芯片102上制造的量子电路元件的数据。尽管在图1中被示出为单个组件，但是经典电路元件112可以使用在标准CMOS制造中众所周知的多层不同的材料(例如，半导体、电介质和金属)来构建。使用这些制造方法的优点在于，它们允许在相对复杂的3D几何结构中路由布线，从而通过接合106在芯片102中的量子比特之间形成数量更多的连接。衬底114可以由诸如单晶硅、硅锗或者砷化镓等材料形成。
经典电路元件未被形成在相同的芯片上或者内作为量子电路元件。这是因为，至少在一些实施方式中，用于制造经典电路元件的电介质(例如，SiO2)和/或非超导金属往往是能量损耗和退相干的源，从而使它们妨碍量子电路元件并且渲染量子处理器的低效且不可靠的操作。然而，通过用超导凸起接合件106将第二芯片104耦合至第一芯片102，可以减少经典电路元件和/或材料对量子电路元件的退相干效应。用作超导凸起接合件106的合适的超导材料包括包括薄金层的铟、铅、铼、钯或者铌等。
一般而言，凸起接合件形成在提供到芯片102的电路元件和芯片104的电路元件的电连接。例如，在一些实施方式中，第一芯片102的互连焊盘116通过形成在衬底110上和/或内的互连件电连接至一个或者多个第一电路元件108。第二芯片104的互连焊盘116通过形成在衬底114上和/或内的互连件118电连接至一个或者多个第二电路元件112。尽管互连件118和电路元件112被示出为延伸通过衬底110，但是互连件118和电路元件112也可以作为在衬底表面(例如，与焊盘116共面)上的单个金属化层的部分而被形成。当互连焊盘116设置在包含量子电路元件的芯片上时，焊盘116可以由用于减少退相干和能量损耗的半导体材料形成。同样，在芯片104上的焊盘116和互联件118可以由用于减少从芯片104生成的热量的超导材料形成。例如，在芯片102上的互连焊盘116和互联件118可以由铝形成，该铝是用于制造量子电路元件的超导金属。例如，可以用于焊盘116和互联件118的其它超导材料包括铌或者氮化钛。第二芯片104的互联件118和焊盘116也可以由诸如铝、铌或者氮化钛等超导材料形成，或者在一些实施方式中，由非超导导电材料形成。
然而，当铟和铝被放置为彼此接触时，铟与铝之间的扩散导致形成增加退相干效应的非超导合金。铟与铝之间的扩散也可以导致设备的机械故障以及诸如孔洞和点蚀等问题。为了避免在超导凸起接合件106与互连焊盘之间形成合金，在超导凸起接合件106与互连焊盘116之间设置阻挡物层120。该阻挡物层120包括超导材料，该超导材料也用作阻止凸起接合件材料扩散到互连焊盘116中的导电阻挡物，反之亦然。
图2是图示了用于利用超导凸起接合件将第一芯片连结至第二芯片以形成设备(诸如，图1所示的设备100)的示例过程200的流程图。图3A至图3E是图示了在图2中阐述的制造过程的示意图。图3A至图3E所示的视图与制造过程的侧视图对应，其中，层延伸到页面内或者外。图中所示的层的大小并不是按比例绘制的。
在过程200中，提供了第一衬底114(202)。图3A是图示了第一衬底114的示例的示意图。例如，第一衬底114可以包括其中形成有一个或者多个电路元件112的单晶硅晶片。可替代地，衬底114和电路元件112可以与从已经被切成方块的晶片获得的模具对应。如本文所阐述的，电路元件112可以包括量子电路元件和经典电路元件。对于本示例，假设电路元件112是经典电路元件并且衬底114是单晶硅衬底。电路元件112可以通过互联件118电连接至一个或者多个互连焊盘116。例如，通过用于在衬底114内限定开口的光刻组合以及用互连材料填充开口的沉积和去除计算(诸如，气相沉积和湿式或者干式蚀刻)，例如，互联件118可以由超导材料或者其它导电材料形成。虽然被示出为形成在衬底114的主体中，但是互联件118也可以形成在衬底114的表面上。例如，互连焊盘116可以由铝或者超导的另一种材料形成。互连焊盘116也可以使用光刻组合以及标准沉积和湿式或者干式蚀刻技术来沉积和限定。
接下来，制备互连焊盘116的表面(204)。在一些实施方式中，金属互连焊盘在其表面上包括薄原生氧化物。例如，铝可以包括AlOx层。薄原生氧化物是绝缘的，从而降低到超导凸起接合件的连接的电导率。为了去除原生氧化物，将互连焊盘116的表面暴露于离子研磨(ion milling)工艺。离子研磨包括：从一定角度将离子(例如，Ar离子)传递至互连焊盘116的表面，从而将材料从表面溅射。通常，离子研磨工艺是在真空条件下执行的。例如，离子研磨可以在3mTorr的真空压力和约28℃的温度下执行。
一旦原生氧化物被去除，便将阻挡物层120沉积在互连焊盘116的制备表面上(206)。阻挡物层包括阻止凸起接合件材料扩散到互连焊盘116中和/或将凸起接合件材料扩散到互连焊盘116中但是也保持超导性的材料。阻挡物层也优选地不会本身与互连焊盘116或者待形成的超导凸起接合件形成合金。为了减少可能由阻挡物层在附近量子电路元件中产生的退相干，阻挡物层材料可以由超导体材料形成。例如，阻挡物层材料可以由氮化钛(包括约4.2K的超导临界温度)形成。可替代地，阻挡物层材料可以包括经由邻近效应而变得超导的金属，诸如，铂或者钨。例如，沉积阻挡物层可以包括执行有效反应溅射。反应溅射是在将与目标材料反应以形成不同化学成分的涂层的气体或者气体混合物(例如，Ar离子或者N2)存在的情况下溅射一种化学成分的目标的工艺。氩在大多数情况下是主要气体，并且控制被引入处理腔中的反应气体的数量以产生完全反应的化合物。作为一个示例，可以在约2*10-8Torr的基础压力和约3mTorr的背景压力以及约28℃的温度下使用Ar和N2的混合物来执行反应溅射。在沉积阻挡物层材料之后，可以对阻挡物层材料进行图案化以仅仅覆盖互连焊盘116的表面，从而形成图3B所示的层120。对阻挡物层材料进行图案化可能需要使用，例如，用于限定对阻挡物层材料将保持在对在阻挡物层材料待被去除的区域中的阻挡物层材料进行湿式和/或干式蚀刻之后的区域的光刻。可替代地，可以使用剥离工艺，其中，将阻挡物层材料沉积在图案化光致抗蚀剂层上。在阻挡物层材料待被去除的区域中，然后使用溶剂来有效地“剥离(lift-off)”光致抗蚀剂和阻挡物层材料涂层。在任何一种情况下，在对阻挡物层材料进行图案化之后，将芯片暴露于O2等离子以去除任何可能存在于芯片的表面上的任何剩余光致抗蚀剂和/或者其它有机材料。
在对阻挡物层进行沉积和图案化之后，可以可选地对阻挡物层120的暴露表面进行离子研磨(208)。研磨去除了原生氧化物在阻挡物层上的痕迹以提高随后的超导接头的电导率和可靠性。随后，将形成超导凸起接合件的超导材料层沉积在阻挡物层的表面上(210)。例如，将形成凸起接合件的超导材料可以包括铟(约3.4K的超导临界温度)。超导材料可以是在真空下(例如，在约1*10-6Torr下)使用例如热蒸发沉积工艺来沉积的。与阻挡物层120一样，可以使用用于限定图3C所示的凸起接合件区域106的光刻组合和湿式或者干式蚀刻技术来对如此沉积的超导材料106进行图案化。可替代地，通过使用剥离工艺来对将形成凸起接合件的超导材料进行图案化，在该剥离工艺中，在沉积超导体凸起接合件材料之前，对光致抗蚀剂层进行沉积和图案化。然后，在沉积超导体凸起接合件材料之后，使用溶剂来去除抗蚀剂和覆盖抗蚀剂的不需要的超导体材料。
如图3D的示例所示，提供附加衬底110。该附加衬底110也可以包括多个电路元件108。如本文所阐述的，电路元件108可以包括量子电路元件，诸如，量子比特，例如，超导共面波导、量子LC振荡器、通量量子比特、或者SQUIDS等。衬底110可以由诸如蓝宝石或者单晶硅等低损耗介电材料形成，并且可以呈晶片或者切割芯片的形式。一个或者多个电路元件108可以通过形成在衬底110内或者上的互联件118电连接至一个或者多个互连焊盘116。为了减少退相干，互联件118和互连焊盘116由诸如铝等超导材料形成。
也可以对附加衬底执行如上面关于图3B至图3C所描述的用于制备互连焊盘116和形成阻挡物层120的相同工艺。例如，可以使用例如离子研磨来制备互连焊盘116的表面，将超导扩散阻挡物120沉积在互连焊盘116的制备表面上并且对其进行图案化，可以进一步对阻挡物层的暴露表面进行离子研磨。另外，可以可选地将形成超导凸起接合件的超导材料层沉积在阻挡物层的表面上。如本文所阐述的，例如，将形成凸起接合件的超导材料可以包括使用热蒸发沉积工艺沉积的和使用光刻组合和湿式或者干式蚀刻技术或者通过剥离工艺图案化的铟。
然后将在一个或者两个芯片上形成凸起接合件106的材料的表面暴露于H2等离子(214)。等离子有助于从铟表面去除氧化物，从而允许铟接合至纯铟，并且提高随后的连接的电导率并且促进粘合。在将超导凸起接合件106暴露于H2等离子之后，如图3E所示将两个芯片结合在一起并且将它们彼此连结(216)(例如，使用凸起接合器)以产生堆叠式器件。压力接合可以在没有施加热量的情况下(例如，在室温下)执行。用于形成接合的压力的示例针对6平方毫米芯片中的1000个接合是25牛顿。在室温下(例如，在约18℃到约30℃的范围内)执行接合的优点在于，可以减少在材料界面上形成小山和空洞。这种小山和空洞也可能导致干扰附近量子电路元件的操作的二能级系统的形成，从而导致退相干效应。在室温下执行接合也可以减少跨越不同材料之间的界面的材料扩散，这也与在量子电路元件中产生退干扰相关联。低温/室温压力接合可以使用例如SETNA,LLC的FC 150来执行。在一些实施方式中，在将芯片连结在一起之前，将晶片切割成单独芯片。
可以设置超导凸起接合件106的厚度，从而将第一芯片和第二芯片间隔开期望量。例如，在第一芯片的表面与第二芯片的相对表面之间的距离300可以设置为在约0.5μm与约100μm之间(例如，在约0.5μm与约20μm之间、在约0.5μm与约15μm之间、在约0.5μm与约10μm之间、在约0.5μm与约5μm之间，或者在约0.5μm与约2.5μm之间)。对于包含量子电路元件的第一芯片连结(例如，接合)至包含量子电路元件的第二芯片的设备，距离300最好在上述范围的低端。例如，距离300可以在约0.5μm到约1μm的范围内。当耦合随着芯片之间的距离减小而增强时，需要下限，因为其允许更好的电耦合。另外，由于两个芯片包括低损耗电介质，人们不太关系在芯片间的距离减小时在量子电路元件中导致损耗和退相干的电介质。相反，当包含量子电路元件的芯片连结(例如，接合)至包含经典电路元件的芯片时，包括经典电路元件的芯片也可以包括在包括量子电路元件的芯片中引起损耗和退相干的有损材料。因此，在这些情况下需要将芯片间隔开距离300，该距离是较大的(相对于两个芯片包含量子电路元件的情况的距离)以降低有损材料将导致量子电路元件的退相干的概率。例如，距离300可以在约5μm到约10μm的范围内。可替代地，对于包含量子电路元件的芯片连结至包含经典电路元件的芯片的实施方式，例如，距离300可以是在约2.5μm与约15μm之间、在约5μm与约15μm之间、或者在约7.5μm与约15μm之间。适当的厚度基于用于沉积和/或去除材料的沉积技术和用来测量厚度的计量技术的准确性和精确度限制可以是不确定的。虽然本文所呈现的示例术语仅仅包含彼此连结的两个芯片的堆叠设备，但是可以将远离和技术扩展到包含三个或者三个以上的芯片的芯片堆叠。例如，堆叠设备可以包括包括量子电路元件的两个芯片，其中，每个芯片都使用本文所描述的超导凸起接合件彼此连结，以及其中，例如，两个芯片中的一个芯片也通过本文所描述的超导体凸起接合件连结至包括任何量子电路元件或者经典电路元件的第三芯片。
本说明书中所描述的量子主题和量子操作的实施例可以实施在合适的量子电路系统中，或者更一般而言，可以实施在量子计算系统中(该量子计算系统包括在本说明书中公开的结构及其结构等效物)，或者可以实施在它们中的一个或者多个的组合中。术语“量子计算系统”可以包括但不限于量子计算机、量子信息处理系统、量子密码系统或者量子模拟器。
术语“量子信息(quantum information)”和“量子数据(quantum data)”指由量子系统携带、被保存或者存储在量子系统中的信息，其中，最小的非平凡系统是量子比特，即，限定量子信息单位的系统。要理解，术语“量子比特(qubit)”涵盖可能是在对应背景下特别适合二能级系统的所有量子系统。这种量子系统可以包括多能级系统，例如，包括两个或者两个以上的能级。例如，这种系统可以包括原子、电子、光子、离子或者超导量子比特。在许多实施方式中，计算基态等同于基态和第一激发态，然而，要理解，计算状态等同于更高能级的激发态的其它设置是可能的。要理解，量子存储器是可以高保真和高效长期存储量子数据的设备，例如，光与物质接口，其中，光用于传输并且物质用于存储和保留量子数据的量子特征，诸如，叠加或者量子相干。
虽然本说明书包含许多具体实施方式细节，但是不应该将这些细节视作对可能被要求的内容的范围的限制，而是对可能特定于具体实施例的特征的描述。本说明书中在单独实施例的背景下描述的某些特征还可以组合形式实施在单个实施例中。相反，在单个实施例的背景下描述的各种特征也可以单独地或者按照任何合适的子组合实施在多个实施例中。此外，虽然上面可能描述了特征，作为某些组合的代表，并且最初甚至同样地对该特征进行了要求，但是可以从组合中删除来自所要求的组合的一个或者多个特征，并且所要求的组合可能涉及子组合或者子组合的变化。
同样，虽然按照特定顺序在附图中图示了操作，但是这不应该理解为：需要按照所示的特定顺序或者按照相继顺序来进行这类操作，或者进行了所有所示操作以实现期望结果。例如，在权利要求书中所引用的动作可以按照不同的顺序进行并且仍然可以实现期望结果。在某些环境下，多任务和并行处理可能是有利的。而且，在上述实施例中的各种组件的分离应该被理解为在所有实施例中需要这种分离。
已经描述了主题的特定实施例。其它实施例在下面的权利要求书的范围内。

Claims (22)

1.一种用于量子计算的设备，包括：
第一芯片，所述第一芯片包括第一电路元件、与所述第一电路元件电接触的第一互连焊盘、和在所述第一互连焊盘上的阻挡物层，其中，所述阻挡物层是氮化钛；
在所述阻挡物层上的超导凸起接合件，所述超导凸起接合件是由铟构成的；以及
第二芯片，所述第二芯片通过所述超导凸起接合件连结至所述第一芯片，所述第二芯片包括第一量子电路元件，其中，所述超导凸起接合件在所述第一电路元件与所述第一量子电路元件之间提供电连接。
2.根据权利要求1所述的设备，其中，所述第一互连焊盘是铝。
3.根据权利要求1所述的设备，其中，所述第一电路元件包括快速单通量量子(RSFQ)设备。
4.根据权利要求1所述的设备，其中，所述第一电路元件包括第二量子电路元件。
5.根据权利要求1所述的设备，其中，所述第一芯片和所述第二芯片中的至少一个包括硅衬底。
6.根据权利要求1所述的设备，其中，所述第一芯片和所述第二芯片中的至少一个包括蓝宝石衬底。
7.根据权利要求1所述的设备，其中，所述第一芯片的第一表面与所述第二芯片的第一表面间隔开并且面向所述第二芯片的所述第一表面，以形成间隙。
8.一种用于制造量子计算设备的方法，包括：
提供包括第一电路元件的第一芯片；
在所述第一芯片的第一表面上形成第一铝互连焊盘，从而将所述第一铝互连焊盘电连接至所述第一电路元件；
在所述第一铝互连焊盘上形成第一氮化钛阻挡物层；
提供包括第二电路元件的第二芯片；
形成铟凸起接合件；以及
通过所述铟凸起接合件将所述第一芯片连结至所述第二芯片，从而将所述第一电路元件电连接至所述第二电路元件，其中，将所述第一芯片连结至所述第二芯片是在室温下进行的。
9.根据权利要求8所述的方法，其中，室温在18℃与30℃之间。
10.根据权利要求9所述的方法，所述方法进一步包括：在形成所述第一氮化钛阻挡物层之前，从所述第一铝互连焊盘去除原生氧化物。
11.根据权利要求10所述的方法，其中，去除所述原生氧化物包括：对所述第一铝互连焊盘的表面进行离子研磨。
12.根据权利要求9所述的方法，其中，形成所述第一氮化钛阻挡物层包括：将氮化钛反应溅射在所述第一铝互连焊盘上。
13.根据权利要求9所述的方法，所述方法进一步包括：在将所述第一芯片连结至所述第二芯片之前，对所述第一氮化铝阻挡物层的表面进行离子研磨。
14.根据权利要求9所述的方法，所述方法进一步包括：将所述铟凸起接合件的表面暴露于H2等离子。
15.根据权利要求9所述的方法，所述方法进一步包括：
在所述第二芯片的第一表面上形成第二铝互连焊盘，从而将所述第二铝互连焊盘电连接至所述第二电路元件；以及
在所述第二芯片的所述第二铝互连焊盘上形成第二氮化钛阻挡物层。
16.根据权利要求15所述的方法，所述方法进一步包括：在形成所述第二氮化钛阻挡物层之前，从所述第二芯片的所述第二铝互连焊盘去除原生氧化物。
17.根据权利要求16所述的方法，其中，从所述第二铝互连焊盘去除所述原生氧化物包括：对所述第二铝互连焊盘的表面进行离子研磨。
18.根据权利要求15所述的方法，其中，在所述第二铝互连焊盘上形成所述第二氮化钛阻挡物层包括：将氮化钛反应溅射在所述第二铝互连焊盘上。
19.根据权利要求15所述的方法，所述方法进一步包括：在将所述第一芯片连结至所述第二芯片之前对所述第二氮化铝阻挡物层的表面进行离子研磨。
20.根据权利要求15所述的方法，其中，形成所述铟凸起接合件包括：将铟沉积在所述第一氮化钛阻挡物层上、在所述第二氮化钛阻挡物层上、或者在所述第一氮化钛阻挡物层和所述第二氮化钛阻挡物层两者上。
21.根据权利要求9所述的方法，其中，所述第一电路元件包括快速单通量量子(RSFQ)设备，并且所述第二电路元件包括量子电路元件。
22.根据权利要求9所述的方法，其中，所述第一电路元件包括第一量子电路元件，并且所述第二电路元件包括第二量子电路元件。
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