JP6139159B2 - 薄膜トランジスター表示板及びその製造方法 - Google Patents
薄膜トランジスター表示板及びその製造方法 Download PDFInfo
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- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
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- G02F1/1362—Active matrix addressed cells
- G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
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- G02—OPTICS
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- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
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- G—PHYSICS
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- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
- G02F1/136295—Materials; Compositions; Manufacture processes
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- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
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- H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
Description
121:ゲート線
122:第1ゲートサブパッド
123:降圧ゲート線
124:ゲート電極
125:保持電極線
129:降圧ゲート電極
131:第1キャッピング層
140:ゲート絶縁膜
140a、140b:第1、第2ゲート副絶縁膜
154:半導体膜
171:データ線
171s1:正画素連結部材
171s2:副画素連結部材
171s3:ゲートパッド連結部材
173h:第1ソース電極
175h:第1ドレイン電極
180:保護膜
180a、180b,180c:第1、第2、第3副保護膜
191h、191l:正画素、副画素電極
191p:第2ゲートサブパッド
GP:ゲートパッド
CTh1、CTh2、CTh3:第1、第2、第3正画素サブコンタクトホール
CTl1、CTl2:第1、第2副画素サブコンタクトホール
CTd1、CTd2、CTd3、CTd4:第1、第2、第3、第4データコンタクトホール
CTp1、CTp2、CTp3:第1、第2、第3ゲートパッドサブコンタクトホール
Claims (10)
- 基板上の薄膜トランジスターに含まれたゲート電極、ソース電極及びドレイン電極と、
前記ゲート電極と一体に形成されたゲート線と、
前記ゲート線の一端に、前記ゲート線と一体に形成された第1ゲートサブパッドと、
前記ゲート線、前記ゲート電極及び前記第1ゲートサブパッドを覆うゲート絶縁膜と、
前記ソース電極に連結されたデータ線と、
前記薄膜トランジスター及び前記データ線の上に配置される平坦化膜と、
前記平坦化膜の上に配置される画素電極及び第2ゲートサブパッドと、
前記ドレイン電極と前記画素電極を連結する画素連結部材と、
前記第1ゲートサブパッドと前記第2ゲートサブパッドを連結するゲートパッド連結部材とを備え、
前記ゲート線、前記ゲート電極及び前記第1ゲートサブパッドは、前記基板上に、いずれの部分も互いに同一の材料で同一の厚みに形成されるゲート層パターンに含まれ、
前記データ線、前記画素連結部材及び前記ゲートパッド連結部材は、前記ゲート絶縁膜上に、いずれの部分も互いに同一の材料で同一の厚みに形成されるデータ層パターンに含まれ、
前記データ層パターン及び前記ゲート層パターンは、いずれも、厚さが前記のソース電極及びドレイン電極より大きく、前記のソース電極及びドレイン電極とは異なる材料を含み、
前記データ層パターンは、前記画素連結部材及び前記ゲートパッド連結部材の上面をそれぞれ部分的に露出させるコンタクトホールの領域を除き、前記平坦化膜により覆われており、
これらのコンタクトホールを通じて、前記画素電極の一部が、前記画素連結部材の上面と接触しており、前記第2ゲートサブパッドの一部が、前記ゲートパッド連結部材の上面と接触していることを特徴とする薄膜トランジスター表示板。 - 前記ゲート絶縁膜は、第1ゲート絶縁膜と、この上に配置される第2ゲート絶縁膜とを含み、
前記第1ゲート絶縁膜は、前記ゲート層パターンの上面を露出させるように、前記ゲート層パターンの間に配置されることにより平坦化絶縁層をなし、
前記第2ゲート絶縁膜は、前記ゲート層パターン及び前記第1ゲート絶縁膜の上面を覆うことを特徴とする請求項1に記載の薄膜トランジスター表示板。 - 前記ゲート層パターンは、その上面から離間して配置された、銅(Cu)を含む材料からなる層を含み、
前記第1ゲート絶縁膜の下には、キャッピング層が配置され、このキャッピング層は、前記ゲート層パターンの側面を、その上端部以外で覆い、
前記キャッピング層における、前記ゲート層パターンの側面を覆う部分は、上端が、前記第1ゲート絶縁膜の上面と一致し、
これにより、前記第1ゲート絶縁膜の上面は、前記基板の上面からの高さが、前記ゲート層パターンの上面よりも低いことを特徴とする請求項2に記載の薄膜トランジスター表示板。 - 前記ゲート層パターンは、その上面に露出する層として、チタン(Ti)又はチタン合金から形成された層を含むことを特徴とする請求項3に記載の薄膜トランジスター表示板。
- 前記データ層パターンは、銅(Cu)を含む材料から形成されており、
前記データ層パターンと前記薄膜トランジスターとの間に配置される第1副保護膜と、
前記データ層パターンと前記平坦化膜との間に配置される第2副保護膜とをさらに含むことを特徴とする請求項1〜4のいずれかに記載の薄膜トランジスター表示板。 - 前記平坦化膜及び前記第1ゲート絶縁膜は、ポリシロキサン(polysiloxane)、フェニルシロキサン(phenylsiloxane)、ポリイミド(polyimide)、シルセスキオキサン(silsesquioxane)、シラン(silane)又は、その他の有機絶縁物質を用いて形成されていることを特徴とする請求項2〜4のいずれかに記載の薄膜トランジスター表示板。
- 前記データ層パターン及び前記ゲート層パターンは、いずれも、厚さが1μm〜4μmの範囲内にあることを特徴とする請求項1〜6のいずれかに記載の薄膜トランジスター表示板。
- 前記データ層パターン及び前記ゲート層パターンは、いずれも、厚さが前記のソース電極及びドレイン電極の4倍以上であることを特徴とする請求項1〜7のいずれかに記載の薄膜トランジスター表示板。
- 前記ドレイン電極及び前記ソース電極は、チタン(Ti)又はモリブデン(Mo)を含むことを特徴とする請求項1〜8のいずれかに記載の薄膜トランジスター表示板。
- 請求項1〜9のいずれかに記載の薄膜トランジスター表示板を製造する方法であって、
前記ゲート層パターンを形成した後、前記基板上に、第1の絶縁層と第2の絶縁層とを順次に積層してから、全面蝕刻を、前記ゲート層パターンの上面、及び側面の上端部が露出するまで進行することにより、前記ゲート層パターンの間に配置される平坦化絶縁層としての第1ゲート絶縁膜のパターンを形成するとともに、前記ゲート層パターンの側面を、その上端部以外にて覆うキャッピング層を形成することを特徴とする薄膜トランジスター表示板の製造方法。
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KR1020120012334A KR101975263B1 (ko) | 2012-02-07 | 2012-02-07 | 박막트랜지스터 표시판과 이를 제조하는 방법 |
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EP (1) | EP2626739B1 (ja) |
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WO2015030086A1 (en) | 2013-08-30 | 2015-03-05 | Semiconductor Energy Laboratory Co., Ltd. | Display device |
CN103730475B (zh) * | 2013-12-26 | 2016-08-31 | 京东方科技集团股份有限公司 | 一种阵列基板及其制造方法、显示装置 |
TWI561906B (en) * | 2016-01-08 | 2016-12-11 | Au Optronics Corp | Pixel structure and display panel |
CN107689383B (zh) * | 2016-08-05 | 2021-06-22 | 群创光电股份有限公司 | 显示装置及其制造方法 |
KR20180051739A (ko) * | 2016-11-08 | 2018-05-17 | 삼성디스플레이 주식회사 | 표시 장치 |
TWI685696B (zh) * | 2018-10-01 | 2020-02-21 | 友達光電股份有限公司 | 主動元件基板及其製造方法 |
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