JP6130312B2 - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
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- JP6130312B2 JP6130312B2 JP2014023101A JP2014023101A JP6130312B2 JP 6130312 B2 JP6130312 B2 JP 6130312B2 JP 2014023101 A JP2014023101 A JP 2014023101A JP 2014023101 A JP2014023101 A JP 2014023101A JP 6130312 B2 JP6130312 B2 JP 6130312B2
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
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- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
- H01L2224/8182—Diffusion bonding
- H01L2224/8183—Solid-solid interdiffusion
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- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/83053—Bonding environment
- H01L2224/83095—Temperature settings
- H01L2224/83096—Transient conditions
- H01L2224/83097—Heating
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- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
- H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
- H01L2224/83862—Heat curing
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- H01L2224/93—Batch processes
- H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
- H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
- H01L25/10—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices having separate containers
- H01L25/105—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15313—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a land array, e.g. LGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
- H01L2924/15321—Connection portion the connection portion being formed on the die mounting surface of the substrate being a ball array, e.g. BGA
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Wire Bonding (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2014023101A JP6130312B2 (ja) | 2014-02-10 | 2014-02-10 | 半導体装置及びその製造方法 |
| US14/554,550 US9530744B2 (en) | 2014-02-10 | 2014-11-26 | Semiconductor device and method of manufacturing the same |
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| Application Number | Priority Date | Filing Date | Title |
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| JP2014023101A JP6130312B2 (ja) | 2014-02-10 | 2014-02-10 | 半導体装置及びその製造方法 |
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| JP2015149459A JP2015149459A (ja) | 2015-08-20 |
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| JP6130312B2 true JP6130312B2 (ja) | 2017-05-17 |
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| KR101799668B1 (ko) * | 2016-04-07 | 2017-11-20 | 앰코 테크놀로지 코리아 주식회사 | 반도체 패키지 및 그 제조 방법 |
| JP6836121B2 (ja) | 2016-08-19 | 2021-02-24 | セイコーエプソン株式会社 | 実装構造体、超音波デバイス、超音波探触子、超音波装置、電子機器、及び実装構造体の製造方法 |
| JP6691031B2 (ja) * | 2016-10-05 | 2020-04-28 | 新光電気工業株式会社 | 配線基板及びその製造方法、半導体パッケージ |
| EP3322267B1 (en) * | 2016-11-10 | 2025-02-19 | AT & S Austria Technologie & Systemtechnik Aktiengesellschaft | Component carrier with adhesion promoting shape of wiring structure |
| US11444048B2 (en) * | 2017-10-05 | 2022-09-13 | Texas Instruments Incorporated | Shaped interconnect bumps in semiconductor devices |
| JP7117615B2 (ja) * | 2017-12-08 | 2022-08-15 | パナソニックIpマネジメント株式会社 | 半導体装置の製造方法 |
| JP7238271B2 (ja) * | 2018-05-21 | 2023-03-14 | 住友ベークライト株式会社 | 電子装置、及び電子装置の製造方法 |
| JP7322456B2 (ja) * | 2019-03-28 | 2023-08-08 | Tdk株式会社 | 電子部品搭載基板 |
| US12381193B2 (en) | 2020-12-01 | 2025-08-05 | Intel Corporation | Integrated circuit assemblies |
| US12224267B2 (en) | 2020-12-04 | 2025-02-11 | Yibu Semiconductor Co., Ltd. | Chip interconnecting method, interconnect device and method for forming chip packages |
| CN112542391B (zh) * | 2020-12-04 | 2022-11-11 | 上海易卜半导体有限公司 | 芯片互联方法、互联器件以及形成封装件的方法 |
| US11756886B2 (en) * | 2020-12-08 | 2023-09-12 | Intel Corporation | Hybrid manufacturing of microeletronic assemblies with first and second integrated circuit structures |
| TWI885204B (zh) * | 2020-12-08 | 2025-06-01 | 美商英特爾股份有限公司 | 積體電路裝置及組件的混合製造 |
| US11817442B2 (en) | 2020-12-08 | 2023-11-14 | Intel Corporation | Hybrid manufacturing for integrated circuit devices and assemblies |
| US12412835B2 (en) | 2021-04-27 | 2025-09-09 | Intel Corporation | Back-side power delivery with glass support at the front |
| US12400997B2 (en) | 2021-06-11 | 2025-08-26 | Intel Corporation | Hybrid manufacturing with modified via-last process |
| US20240079307A1 (en) * | 2022-09-07 | 2024-03-07 | Qualcomm Incorporated | Package comprising a substrate with post interconnects having a profile cross section of a trapezoid shape |
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| JP3378334B2 (ja) | 1994-01-26 | 2003-02-17 | 株式会社東芝 | 半導体装置実装構造体 |
| JP2001044319A (ja) * | 1999-07-27 | 2001-02-16 | Kyocera Corp | 配線基板およびその実装構造 |
| TW200507218A (en) * | 2003-03-31 | 2005-02-16 | North Corp | Layout circuit substrate, manufacturing method of layout circuit substrate, and circuit module |
| TWI241702B (en) * | 2003-07-28 | 2005-10-11 | Siliconware Precision Industries Co Ltd | Ground pad structure for preventing solder extrusion and semiconductor package having the ground pad structure |
| WO2007069606A1 (ja) * | 2005-12-14 | 2007-06-21 | Shinko Electric Industries Co., Ltd. | チップ内蔵基板およびチップ内蔵基板の製造方法 |
| JP2007305799A (ja) * | 2006-05-11 | 2007-11-22 | Fujitsu Ltd | 半導体装置の製造方法 |
| JP2006279062A (ja) * | 2006-05-25 | 2006-10-12 | Nec Corp | 半導体素子および半導体装置 |
| JP2008306128A (ja) * | 2007-06-11 | 2008-12-18 | Shinko Electric Ind Co Ltd | 半導体装置およびその製造方法 |
| JP2010153778A (ja) * | 2008-11-21 | 2010-07-08 | Panasonic Corp | 半導体装置 |
| US8415781B2 (en) * | 2010-08-09 | 2013-04-09 | Ibiden Co., Ltd. | Electronic component and method for manufacturing the same |
| JP2013187353A (ja) | 2012-03-08 | 2013-09-19 | Renesas Electronics Corp | 電子装置および電子装置の製造方法 |
| JP5951414B2 (ja) * | 2012-08-29 | 2016-07-13 | 新光電気工業株式会社 | 電子部品内蔵基板及び電子部品内蔵基板の製造方法 |
| US9536850B2 (en) * | 2013-03-08 | 2017-01-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package having substrate with embedded metal trace overlapped by landing pad |
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| US20150228551A1 (en) | 2015-08-13 |
| US9530744B2 (en) | 2016-12-27 |
| JP2015149459A (ja) | 2015-08-20 |
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