JP6126725B2 - ナノ構造処理のための導電性補助層の形成及び選択的除去 - Google Patents
ナノ構造処理のための導電性補助層の形成及び選択的除去 Download PDFInfo
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- JP6126725B2 JP6126725B2 JP2016103110A JP2016103110A JP6126725B2 JP 6126725 B2 JP6126725 B2 JP 6126725B2 JP 2016103110 A JP2016103110 A JP 2016103110A JP 2016103110 A JP2016103110 A JP 2016103110A JP 6126725 B2 JP6126725 B2 JP 6126725B2
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Description
本出願は、その全開示を出典明示によりここに援用する2008年2月25日出願の米国仮出願番号第61/031333号に基づく優先権を主張する。
ここに記載された技術は概して、ナノ構造の化学的蒸着法(CVD)の分野に関し、より特定すると、ナノ構造の成長中のプラズマ誘起損傷の低減又は除去、及び導電性及び絶縁表面の両方でナノ構造の自己整合成長を可能にすることに関する。
100−導電性基板
102−個別のナノ構造の成長を支えるためにパターン形成された触媒層
104−ナノ構造の「フォレスト」(複数の密集したナノ構造)の成長を支えるためにパターン形成された触媒層
106−個別のナノ構造
108−ナノ構造の「フォレスト」(複数の密集したナノ構造)
110−絶縁基板
112−連続金属下層
114−絶縁体の上部にあるパターン金属下層
116−絶縁基板の上面と同じ高さにある上面を有したパターン金属下層(研磨後の平坦なチップ)
118−ヴィア(垂直配線)
120−連続導電性補助層
122−残留触媒層(自己整合エッチング後)
124−残留導電性補助層(自己整合エッチング後)
126−任意の層
128−導波路のための基板
130−導波路材料
132−導電性補助層の残存する垂直側壁
134−パターン導電性補助層
136−絶縁体を通るヴィアホール
200−導電性補助層の形成
210−任意の付加的な層の形成
220−触媒層の形成及びパターン形成
230−ナノ構造の成長
240−補助層の選択的及び自己整合除去
本明細書に記載された技術の重要な応用は、例えばコンピュータデバイスで使用されうる集積回路の配線及び/又は熱エレベータの作製である。ナノ構造は、集積回路チップ内部で又は集積回路チップへ/から熱及び電気を運ぶために用いられる。使用される成長方法及びデバイスは、研磨による金属のパターン形成を伴う現行の処理基準と適合し、また関与する金属とも適合する。また、集積回路(複数のデバイス層)の三次元積層がここに記載された方法で作られたナノ構造を配線として利用できる。例えば、ヴィアホール配線構造を作製するために本発明を利用する方法が図8A−8Cに記載されている。図12は、ここに記載された技術及び方法を用いて作製された例示的なデバイスとして、酸化物絶縁体にヴィアホールを介して炭素ナノ構造が成長しているデバイスのSEM顕微鏡写真を示す。図12で、明るく平坦な領域は絶縁領域であり、残りの領域には垂直に成長したナノ構造が見られる。
原理を実証するために、パターン金(下)層(下にチタン接着促進層を有する)が、そうでなければ絶縁性の酸化物表面上に(標準的なリソグラフィ技術を用いて)形成された。触媒をパターン金属下層上に直接配するのは、成長中に大きなプラズマ誘起損傷が生じうるため望ましくない。代わりに、タングステン補助層(50nm)がチップ表面全体にスパッタされた。次いでパターン触媒層(Si10nm及びNi10nm)が標準的なリフトオフ工程によって(パターン金属下層と並んで)形成された。成長後、構造が図9A及び9Bに示されたように現れた。当該例で、成長温度は約700度、及びプラズマは約4トールの圧力でC2H2及びNH3ガス(それぞれ20及び100sccm)を混合して生成された。プラズマ電流は20mAに設定され、成長時間は約60分だった。この特定の例で、触媒は、成長工程後にナノ繊維の薄膜(「フォレスト」)が生じるようにパターン形成されたが、触媒域をもっと小さくすれば個別の垂直配向したナノ繊維が生じることとなる。
Claims (7)
- 少なくとも1つの絶縁領域によって分離された露出金属島を有する基板と、
前記露出金属島上に配置された少なくとも1つのナノ構造と、
前記少なくとも1つの絶縁領域上に配置された少なくとも1つのナノ構造と、
前記基板と前記少なくとも1つのナノ構造との間に配置された導電性補助層と、
を備え、
前記導電性補助層は前記少なくとも1つのナノ構造の真下にのみ存在する、集積回路。 - さらに、前記導電性補助層と前記少なくとも1つのナノ構造との間に配置された触媒層を備える、請求項1に記載の集積回路。
- 前記触媒層は、前記少なくとも1つのナノ構造の真下にのみ存在する、請求項2に記載の集積回路。
- 前記導電性補助層は複数の層を含む、請求項1から3のいずれか1項に記載の集積回路。
- 前記導電性補助層は、自己整合マスクとしての前記少なくとも1つのナノ構造を使用して、エッチングによりパターン形成されている、請求項1から4のいずれか1項に記載の集積回路。
- 前記少なくとも1つのナノ構造は前記基板からの成長構造として形成されている、請求項1から5のいずれか1項に記載の集積回路。
- 請求項1から6のいずれか1項に記載の第1の集積回路と、
前記第1の集積回路上に積層された第2の集積回路と
を備え、
前記第2の集積回路は、複数の配線を有し、各配線は、前記露出金属島上に配置された前記少なくとも1つのナノ構造を介して、前記第1の集積回路に設けられた複数の露出金属島のうち対応する露出金属島に電気的及び/または熱的に接続されている、電子デバイス。
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US20110076841A1 (en) * | 2009-09-30 | 2011-03-31 | Kahen Keith B | Forming catalyzed ii-vi semiconductor nanowires |
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EP2541581A1 (en) * | 2011-06-29 | 2013-01-02 | Khalid Waqas | Device comprising nanostructures and method of manufacturing thereof |
RU2497319C1 (ru) * | 2012-02-28 | 2013-10-27 | Федеральное государственное автономное образовательное учреждение высшего профессионального образования "Национальный исследовательский университет "Высшая школа экономики" | Печатная плата для бортовой радиоэлектронной аппаратуры космических аппаратов |
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CN102007571A (zh) | 2011-04-06 |
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EP2250661B1 (en) | 2020-04-08 |
RU2010138584A (ru) | 2012-04-10 |
TW200944474A (en) | 2009-11-01 |
JP5474835B2 (ja) | 2014-04-16 |
KR20100117075A (ko) | 2010-11-02 |
EP2250661A4 (en) | 2011-09-07 |
US8508049B2 (en) | 2013-08-13 |
KR20160078517A (ko) | 2016-07-04 |
JP2016195257A (ja) | 2016-11-17 |
KR101638463B1 (ko) | 2016-07-11 |
EP2250661A1 (en) | 2010-11-17 |
US20150318085A1 (en) | 2015-11-05 |
US20130334704A1 (en) | 2013-12-19 |
JP2014140039A (ja) | 2014-07-31 |
US20150004092A1 (en) | 2015-01-01 |
CN105441903A (zh) | 2016-03-30 |
JP2011517366A (ja) | 2011-06-02 |
JP5943947B2 (ja) | 2016-07-05 |
WO2009108101A1 (en) | 2009-09-03 |
JP2017152716A (ja) | 2017-08-31 |
US9114993B2 (en) | 2015-08-25 |
TWI465389B (zh) | 2014-12-21 |
US8866307B2 (en) | 2014-10-21 |
US20090233124A1 (en) | 2009-09-17 |
CN105441903B (zh) | 2018-04-24 |
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