JP6085803B2 - 半導体装置の製造方法 - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims description 138
- 238000004519 manufacturing process Methods 0.000 title claims description 106
- 238000000034 method Methods 0.000 claims description 120
- 238000002955 isolation Methods 0.000 claims description 35
- 125000006850 spacer group Chemical group 0.000 claims description 30
- 239000000463 material Substances 0.000 claims description 19
- 238000000059 patterning Methods 0.000 claims description 18
- 239000000758 substrate Substances 0.000 claims description 14
- 229910021332 silicide Inorganic materials 0.000 claims description 13
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 13
- 238000012545 processing Methods 0.000 claims description 8
- 239000000126 substance Substances 0.000 claims description 7
- 239000007769 metal material Substances 0.000 claims description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 50
- 229910052814 silicon oxide Inorganic materials 0.000 description 50
- 239000010410 layer Substances 0.000 description 43
- 239000012535 impurity Substances 0.000 description 21
- 238000005530 etching Methods 0.000 description 15
- 239000002184 metal Substances 0.000 description 14
- 229910052751 metal Inorganic materials 0.000 description 14
- 238000005468 ion implantation Methods 0.000 description 12
- 229910052581 Si3N4 Inorganic materials 0.000 description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 11
- 229910052710 silicon Inorganic materials 0.000 description 11
- 239000010703 silicon Substances 0.000 description 11
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 11
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 10
- 229920002120 photoresistant polymer Polymers 0.000 description 9
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- 238000000206 photolithography Methods 0.000 description 7
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 238000001312 dry etching Methods 0.000 description 5
- 238000009413 insulation Methods 0.000 description 5
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- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 4
- 239000007864 aqueous solution Substances 0.000 description 4
- 238000004380 ashing Methods 0.000 description 4
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- 229910021417 amorphous silicon Inorganic materials 0.000 description 3
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
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- 229910052721 tungsten Inorganic materials 0.000 description 3
- 229910004129 HfSiO Inorganic materials 0.000 description 2
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 2
- 229910004166 TaN Inorganic materials 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
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- 229910052802 copper Inorganic materials 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 239000007772 electrode material Substances 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
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- 239000011810 insulating material Substances 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 239000005368 silicate glass Substances 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 description 1
- 229910019001 CoSi Inorganic materials 0.000 description 1
- 229910005883 NiSi Inorganic materials 0.000 description 1
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- 230000004913 activation Effects 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
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- 238000005452 bending Methods 0.000 description 1
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- 238000006243 chemical reaction Methods 0.000 description 1
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- 239000000470 constituent Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000007687 exposure technique Methods 0.000 description 1
- 125000001475 halogen functional group Chemical group 0.000 description 1
- QOSATHPSBFQAML-UHFFFAOYSA-N hydrogen peroxide;hydrate Chemical compound O.OO QOSATHPSBFQAML-UHFFFAOYSA-N 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 239000012466 permeate Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 229910052707 ruthenium Inorganic materials 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28247—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon passivation or protection of the electrode, e.g. using re-oxidation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
一実施形態による半導体装置の製造方法について図1乃至図48を用いて説明する。
第1参考例による半導体装置の製造方法について図49乃至63を用いて説明する。図1乃至図48に示す一実施形態による半導体装置の製造方法と同様の構成要素には同一の符号を付し説明を省略し或いは簡潔にする。
第2参考例による半導体装置の製造方法について図64乃至73を用いて説明する。図1乃至図48に示す一実施形態による半導体装置の製造方法及び図49乃至図63に示す第1参考例による半導体装置の製造方法と同様の構成要素には同一の符号を付し説明を省略し或いは簡潔にする。
上記実施形態に限らず種々の変形が可能である。
12…素子分離絶縁膜
14…活性領域
16…シリコン酸化膜
18…高誘電率絶縁膜
20…ゲート絶縁膜
22…緩衝材層
24…ゲート膜
26…第1ハードマスク
28…第2ハードマスク
30…第1マスクパターン
32…第2マスクパターン
34…開口部
36,44…不純物層
38…スペーサ絶縁膜
40…第3マスクパターン
42…サイドウォール絶縁膜
46…シリサイド層
48,52…層間絶縁膜
50…ゲート電極
54,56…コンタクトホール
58…コンタクトプラグ
60…マスクパターン
Claims (9)
- 半導体基板上に、ゲート絶縁膜を形成する工程と、
前記ゲート絶縁膜上に、ゲート膜を形成する工程と、
前記ゲート膜上に、ハードマスク膜を形成する工程と、
前記ハードマスク膜を、第1のマスクパターンを用いてパターニングする工程と、
パターニングされた前記ハードマスク膜を、第2のマスクパターンを用いてゲートパターンに加工する工程と、
前記ゲートパターンを有する前記ハードマスク膜をマスクとして、前記ゲート膜及び前記ゲート絶縁膜をパターニングする工程と、
パターニングした前記ゲート膜及び前記ゲート絶縁膜が形成された前記半導体基板上に、スペーサ絶縁膜を形成する工程と、
前記スペーサ絶縁膜上に、パターニングした前記ゲート膜及び前記ゲート絶縁膜の端部を覆う第3のマスクパターンを形成する工程と、
前記第3のマスクパターンをマスクとして前記スペーサ絶縁膜をエッチングし、前記第3のマスクパターン下に前記スペーサ絶縁膜を残しつつ、パターニングした前記ゲート膜及び前記ゲート絶縁膜の側壁部分に、前記スペーサ絶縁膜よりなるサイドウォール絶縁膜を形成する工程と
を有することを特徴とする半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
前記第3のマスクパターンは、前記第2のマスクパターンの反転パターンを有する
ことを特徴とする半導体装置の製造方法。 - 請求項1又は2記載の半導体装置の製造方法において、
前記ゲート絶縁膜は、高誘電率絶縁膜を有する
ことを特徴とする半導体装置の製造方法。 - 請求項1乃至3のいずれか1項に記載の半導体装置の製造方法において、
前記ゲート絶縁膜を形成する工程の前に、活性領域を画定する素子分離絶縁膜を形成する工程を更に有し、
前記第2のマスクパターンが露出する領域は、前記素子分離絶縁膜上に位置している
ことを特徴とする半導体装置の製造方法。 - 請求項4記載の半導体装置の製造方法において、
前記第3のマスクパターンを除去する工程の後、薬液処理により前記活性領域の前記半導体基板を露出する工程と、前記半導体基板を露出した前記活性領域上にシリサイド層を形成する工程を更に有する
ことを特徴とする半導体装置の製造方法。 - 請求項1乃至5のいずれか1項に記載の半導体装置の製造方法において、
前記第3のマスクパターンを除去する工程の後、前記ハードマスク膜を除去する工程と、前記ゲート膜を除去する工程と、前記ゲート膜を除去した部分にメタル材料を埋め込み、前記メタル材料よりなるゲート電極を形成する工程とを更に有する
ことを特徴とする半導体装置の製造方法。 - 請求項6記載の半導体装置の製造方法において、
前記ゲート絶縁膜を形成する工程の後、前記ゲート膜を形成する工程の前に、緩衝材層を形成する工程を更に有し、
前記ゲート膜を除去する工程では、前記緩衝材層をストッパとして、前記ゲート膜を除去する
ことを特徴とする半導体装置の製造方法。 - 請求項1乃至7のいずれか1項に記載の半導体装置の製造方法において、
前記ハードマスク膜は、第1のハードマスク膜と、前記第1のハードマスク膜上に形成された第2のハードマスク膜とを有し、
前記ハードマスク膜をパターニングする工程では、前記第1のハードマスク膜をストッパとして前記第2のハードマスク膜をパターニングし、
前記ゲート膜及び前記ゲート絶縁膜をパターニングする工程では、前記第2のハードマスク膜をマスクとして、前記第1のハードマスク膜、前記ゲート膜及び前記ゲート絶縁膜をパターニングする
ことを特徴とする半導体装置の製造方法。 - 請求項1乃至8のいずれか1項に記載の半導体装置の製造方法において、
前記第2のマスクパターンを用いて前記ハードマスク膜を加工する工程では、複数の前記ゲートパターンを形成する
ことを特徴とする半導体装置の製造方法。
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JP2013030321A JP6085803B2 (ja) | 2013-02-19 | 2013-02-19 | 半導体装置の製造方法 |
US14/066,416 US9087783B2 (en) | 2013-02-19 | 2013-10-29 | Method of manufacturing semiconductor device |
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JP2013030321A JP6085803B2 (ja) | 2013-02-19 | 2013-02-19 | 半導体装置の製造方法 |
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JP2014160735A JP2014160735A (ja) | 2014-09-04 |
JP6085803B2 true JP6085803B2 (ja) | 2017-03-01 |
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US10699943B2 (en) * | 2018-04-30 | 2020-06-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming contacts in a semiconductor device |
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JPH05109764A (ja) * | 1991-10-21 | 1993-04-30 | Nec Corp | 絶縁ゲート型電界効果トランジスタの製造方法 |
JP2000260952A (ja) * | 1999-03-05 | 2000-09-22 | Toshiba Corp | 半導体装置 |
US6329240B1 (en) * | 1999-10-07 | 2001-12-11 | Monolithic System Technology, Inc. | Non-volatile memory cell and methods of fabricating and operating same |
JP2002231938A (ja) * | 2001-01-30 | 2002-08-16 | Hitachi Ltd | 半導体集積回路装置およびその製造方法 |
JP4776813B2 (ja) * | 2001-06-12 | 2011-09-21 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
JP2003303963A (ja) | 2002-04-11 | 2003-10-24 | Hitachi Ltd | 半導体装置およびその製造方法 |
JP2007123342A (ja) * | 2005-10-25 | 2007-05-17 | Nec Electronics Corp | 半導体装置の製造方法。 |
US8203182B2 (en) * | 2007-03-14 | 2012-06-19 | Nxp B.V. | FinFET with two independent gates and method for fabricating the same |
US20080286698A1 (en) * | 2007-05-18 | 2008-11-20 | Haoren Zhuang | Semiconductor device manufacturing methods |
JP5233219B2 (ja) * | 2007-09-20 | 2013-07-10 | 富士通セミコンダクター株式会社 | 半導体装置の製造方法及びフォトマスクの設計方法 |
DE102009046261B4 (de) * | 2009-10-30 | 2012-05-16 | GLOBALFOUNDRIES Dresden Module One Ltd. Liability Company & Co. KG | Verfahren zur Herstellung von Transistoren mit Metallgateelektrodenstrukturen mit großem ε, die vor den Drain/Source-Gebieten auf der Grundlage eines Opferkohlenstoffabstandshalters hergestellt werden |
JP5521726B2 (ja) | 2010-04-16 | 2014-06-18 | 富士通セミコンダクター株式会社 | 半導体装置及びその製造方法 |
JP5569173B2 (ja) * | 2010-06-18 | 2014-08-13 | ソニー株式会社 | 半導体装置の製造方法及び半導体装置 |
KR101692407B1 (ko) | 2010-08-19 | 2017-01-04 | 삼성전자주식회사 | 라인 패턴 구조물의 형성 방법 |
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2013
- 2013-02-19 JP JP2013030321A patent/JP6085803B2/ja not_active Expired - Fee Related
- 2013-10-29 US US14/066,416 patent/US9087783B2/en not_active Expired - Fee Related
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JP2014160735A (ja) | 2014-09-04 |
US9087783B2 (en) | 2015-07-21 |
US20140235045A1 (en) | 2014-08-21 |
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