JP6041731B2 - インターポーザ、及び電子部品パッケージ - Google Patents

インターポーザ、及び電子部品パッケージ Download PDF

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Publication number
JP6041731B2
JP6041731B2 JP2013067463A JP2013067463A JP6041731B2 JP 6041731 B2 JP6041731 B2 JP 6041731B2 JP 2013067463 A JP2013067463 A JP 2013067463A JP 2013067463 A JP2013067463 A JP 2013067463A JP 6041731 B2 JP6041731 B2 JP 6041731B2
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Japan
Prior art keywords
inorganic
insulating layer
inorganic insulating
layer
wiring
Prior art date
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Application number
JP2013067463A
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English (en)
Japanese (ja)
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JP2014192386A5 (https=
JP2014192386A (ja
Inventor
村山　啓
啓 村山
光浩 相澤
光浩 相澤
浩児 原
浩児 原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
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Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2013067463A priority Critical patent/JP6041731B2/ja
Priority to US14/202,140 priority patent/US9374889B2/en
Publication of JP2014192386A publication Critical patent/JP2014192386A/ja
Publication of JP2014192386A5 publication Critical patent/JP2014192386A5/ja
Application granted granted Critical
Publication of JP6041731B2 publication Critical patent/JP6041731B2/ja
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0271—Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/467—Adding a circuit layer by thin film methods
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0245—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising use of blind vias during the manufacture
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H10W70/635—Through-vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/012—Manufacture or treatment of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0137—Materials
    • H05K2201/0179—Thin film deposited insulating layer, e.g. inorganic layer for printed capacitor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/06—Thermal details
    • H05K2201/068—Thermal details wherein the coefficient of thermal expansion is important
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10227—Other objects, e.g. metallic pieces
    • H05K2201/10378—Interposers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
    • H05K3/4053—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques
    • H05K3/4061—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques for via connections in inorganic insulating substrates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4688—Composite multilayer circuits, i.e. comprising insulating layers having different properties
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/682—Shapes or dispositions thereof comprising holes having chips therein
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W99/00—Subject matter not provided for in other groups of this subclass

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP2013067463A 2013-03-27 2013-03-27 インターポーザ、及び電子部品パッケージ Active JP6041731B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2013067463A JP6041731B2 (ja) 2013-03-27 2013-03-27 インターポーザ、及び電子部品パッケージ
US14/202,140 US9374889B2 (en) 2013-03-27 2014-03-10 Interposer and electronic component package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2013067463A JP6041731B2 (ja) 2013-03-27 2013-03-27 インターポーザ、及び電子部品パッケージ

Publications (3)

Publication Number Publication Date
JP2014192386A JP2014192386A (ja) 2014-10-06
JP2014192386A5 JP2014192386A5 (https=) 2016-02-12
JP6041731B2 true JP6041731B2 (ja) 2016-12-14

Family

ID=51620660

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2013067463A Active JP6041731B2 (ja) 2013-03-27 2013-03-27 インターポーザ、及び電子部品パッケージ

Country Status (2)

Country Link
US (1) US9374889B2 (https=)
JP (1) JP6041731B2 (https=)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20160080965A (ko) * 2014-12-30 2016-07-08 앰코 테크놀로지 코리아 주식회사 반도체 디바이스 및 그 제조 방법
JP2018041750A (ja) * 2015-01-21 2018-03-15 ソニー株式会社 インターポーザ、モジュールおよびインターポーザの製造方法
US10535615B2 (en) * 2015-03-03 2020-01-14 Intel Corporation Electronic package that includes multi-layer stiffener
DE102016105910A1 (de) * 2016-03-31 2017-10-05 Epcos Ag Kondensatoranordnung
AU2017334390B2 (en) * 2016-09-27 2022-12-15 Perkinelmer Health Sciences Canada, Inc Capacitors and radio frequency generators and other devices using them
JP2018106048A (ja) * 2016-12-27 2018-07-05 大日本印刷株式会社 構造体および構造体を用いた回折格子
KR102545168B1 (ko) * 2019-03-26 2023-06-19 삼성전자주식회사 인터포저 및 이를 포함하는 반도체 패키지
KR102861815B1 (ko) * 2020-06-16 2025-09-17 삼성전자주식회사 인터포저 및 이를 포함하는 반도체 패키지
JP7643910B2 (ja) * 2021-03-31 2025-03-11 株式会社デンソー 半導体装置
CN115966518A (zh) * 2021-10-08 2023-04-14 群创光电股份有限公司 电子装置

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW210422B (https=) * 1991-06-04 1993-08-01 Akzo Nv
US5778523A (en) * 1996-11-08 1998-07-14 W. L. Gore & Associates, Inc. Method for controlling warp of electronic assemblies by use of package stiffener
JP4079699B2 (ja) * 2001-09-28 2008-04-23 富士通株式会社 多層配線回路基板
WO2003083543A1 (en) * 2002-04-01 2003-10-09 Ibiden Co., Ltd. Ic chip mounting substrate, ic chip mounting substrate manufacturing method, optical communication device, and optical communication device manufacturing method
US7070207B2 (en) * 2003-04-22 2006-07-04 Ibiden Co., Ltd. Substrate for mounting IC chip, multilayerd printed circuit board, and device for optical communication
JP4112448B2 (ja) * 2003-07-28 2008-07-02 株式会社東芝 電気光配線基板及び半導体装置
JP2006120956A (ja) * 2004-10-22 2006-05-11 Ibiden Co Ltd 多層プリント配線板
JP4072176B2 (ja) * 2005-08-29 2008-04-09 新光電気工業株式会社 多層配線基板の製造方法
JP5082321B2 (ja) * 2006-07-28 2012-11-28 大日本印刷株式会社 多層プリント配線板及びその製造方法
JP5137059B2 (ja) 2007-06-20 2013-02-06 新光電気工業株式会社 電子部品用パッケージ及びその製造方法と電子部品装置
JP5248084B2 (ja) 2007-10-26 2013-07-31 新光電気工業株式会社 シリコンインターポーザとこれを用いた半導体装置用パッケージおよび半導体装置
JP5248179B2 (ja) 2008-04-17 2013-07-31 新光電気工業株式会社 電子装置の製造方法
US8829355B2 (en) * 2009-03-27 2014-09-09 Ibiden Co., Ltd. Multilayer printed wiring board
JP5271214B2 (ja) 2009-09-15 2013-08-21 日本電信電話株式会社 半導体装置およびその製造方法
US8809690B2 (en) * 2010-03-04 2014-08-19 Rogers Corporation Dielectric bond plies for circuits and multilayer circuits, and methods of manufacture thereof
WO2011108308A1 (ja) * 2010-03-04 2011-09-09 日本電気株式会社 半導体素子内蔵配線基板
WO2011125380A1 (ja) * 2010-04-08 2011-10-13 日本電気株式会社 半導体素子内蔵配線基板
US9173299B2 (en) * 2010-09-30 2015-10-27 KYOCERA Circuit Solutions, Inc. Collective printed circuit board
US20130337648A1 (en) * 2012-06-14 2013-12-19 Bridge Semiconductor Corporation Method of making cavity substrate with built-in stiffener and cavity
US20140048951A1 (en) * 2012-08-14 2014-02-20 Bridge Semiconductor Corporation Semiconductor assembly with dual connecting channels between interposer and coreless substrate
US9209154B2 (en) * 2013-12-04 2015-12-08 Bridge Semiconductor Corporation Semiconductor package with package-on-package stacking capability and method of manufacturing the same
US9184104B1 (en) * 2014-05-28 2015-11-10 Stats Chippac, Ltd. Semiconductor device and method of forming adhesive layer over insulating layer for bonding carrier to mixed surfaces of semiconductor die and encapsulant

Also Published As

Publication number Publication date
US9374889B2 (en) 2016-06-21
US20140293564A1 (en) 2014-10-02
JP2014192386A (ja) 2014-10-06

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