JP6031059B2 - 半導体装置、積層型半導体装置、封止後積層型半導体装置、及びこれらの製造方法 - Google Patents

半導体装置、積層型半導体装置、封止後積層型半導体装置、及びこれらの製造方法 Download PDF

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JP6031059B2
JP6031059B2 JP2014071301A JP2014071301A JP6031059B2 JP 6031059 B2 JP6031059 B2 JP 6031059B2 JP 2014071301 A JP2014071301 A JP 2014071301A JP 2014071301 A JP2014071301 A JP 2014071301A JP 6031059 B2 JP6031059 B2 JP 6031059B2
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insulating layer
semiconductor device
electrode
semiconductor element
forming
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JP2014071301A
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Japanese (ja)
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JP2015195238A5 (enExample
JP2015195238A (ja
Inventor
竹村　勝也
勝也 竹村
曽我　恭子
恭子 曽我
淺井　聡
聡 淺井
和紀 近藤
和紀 近藤
菅生　道博
道博 菅生
加藤　英人
英人 加藤
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Shin Etsu Chemical Co Ltd
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Shin Etsu Chemical Co Ltd
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Application filed by Shin Etsu Chemical Co Ltd filed Critical Shin Etsu Chemical Co Ltd
Priority to JP2014071301A priority Critical patent/JP6031059B2/ja
Priority to PCT/JP2015/001433 priority patent/WO2015151426A1/ja
Priority to US15/126,116 priority patent/US10141272B2/en
Priority to EP15772875.9A priority patent/EP3128548B1/en
Priority to CN201580018117.5A priority patent/CN106415823B/zh
Priority to KR1020167027165A priority patent/KR102263433B1/ko
Priority to TW104110257A priority patent/TWI648438B/zh
Publication of JP2015195238A publication Critical patent/JP2015195238A/ja
Publication of JP2015195238A5 publication Critical patent/JP2015195238A5/ja
Publication of JP6031059B2 publication Critical patent/JP6031059B2/ja
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
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    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10431—Details of mounted components
    • H05K2201/10507—Involving several components
    • H05K2201/10515—Stacked components

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US15/126,116 US10141272B2 (en) 2014-03-31 2015-03-16 Semiconductor apparatus, stacked semiconductor apparatus and encapsulated stacked-semiconductor apparatus each having photo-curable resin layer
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