WO2015151426A1 - 半導体装置、積層型半導体装置、封止後積層型半導体装置、及びこれらの製造方法 - Google Patents

半導体装置、積層型半導体装置、封止後積層型半導体装置、及びこれらの製造方法 Download PDF

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WO2015151426A1
WO2015151426A1 PCT/JP2015/001433 JP2015001433W WO2015151426A1 WO 2015151426 A1 WO2015151426 A1 WO 2015151426A1 JP 2015001433 W JP2015001433 W JP 2015001433W WO 2015151426 A1 WO2015151426 A1 WO 2015151426A1
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Prior art keywords
insulating layer
semiconductor device
electrode
semiconductor element
forming
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PCT/JP2015/001433
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English (en)
French (fr)
Japanese (ja)
Inventor
竹村　勝也
曽我　恭子
淺井　聡
和紀 近藤
菅生　道博
加藤　英人
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Shin Etsu Chemical Co Ltd
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Shin Etsu Chemical Co Ltd
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Application filed by Shin Etsu Chemical Co Ltd filed Critical Shin Etsu Chemical Co Ltd
Priority to CN201580018117.5A priority Critical patent/CN106415823B/zh
Priority to US15/126,116 priority patent/US10141272B2/en
Priority to EP15772875.9A priority patent/EP3128548B1/en
Priority to KR1020167027165A priority patent/KR102263433B1/ko
Publication of WO2015151426A1 publication Critical patent/WO2015151426A1/ja
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10431—Details of mounted components
    • H05K2201/10507—Involving several components
    • H05K2201/10515—Stacked components

Definitions

  • the present invention relates to a semiconductor device, a stacked semiconductor device, a post-sealing stacked semiconductor device, and a manufacturing method thereof.
  • a photosensitive insulating material or a stacked semiconductor device that can cope with an increase in substrate area in productivity improvement and can be used in a high-density mounting technology such as a chip size package, a chip scale package (CSP), or three-dimensional stacking. Therefore, development of the manufacturing method is desired.
  • Patent Documents 1 and 2 show an example in which a semiconductor element is placed on a wiring board without using wire bonding, and a method of placing the semiconductor element on a board on which wiring is performed by three-dimensionally stacking the semiconductor elements.
  • Patent Document 1 shows an example of a method for manufacturing a semiconductor device having a semiconductor element such as a light receiving element or a light emitting element.
  • the semiconductor device 50 includes an Al through a through electrode 56.
  • the electrode pad 55 and the rewiring pattern 52 are connected, and the rewiring pattern 52 of the semiconductor device and the rewiring pattern 57 on the wiring board 53 are connected via the solder bumps 58.
  • a device formation layer 59 and a plurality of Al electrode pads 55 are formed on the upper surface of the semiconductor device.
  • a through hole 54 penetrating the semiconductor device is provided between the Al electrode pad 55 and the rewiring pattern 52 by dry etching, and a through electrode 56 is formed in the through hole 54 by Cu plating.
  • the device formation layer 59 is disposed on the upper surface of the semiconductor device and receives light or emits light. According to this method, the semiconductor element 51 and the wiring substrate 53 are not bonded by wire bonding, but rewiring must be performed on the semiconductor device and solder bumps must be disposed. In reality, it is difficult to achieve finer wiring and higher density solder bumps.
  • Patent Document 2 discloses a manufacturing method of a semiconductor device useful for three-dimensional stacking of a plurality of semiconductor elements.
  • a structure in which a semiconductor element 180 and a semiconductor element 280 are stacked is shown. Illustrated.
  • Each semiconductor element to be laminated includes solder bumps (170, 270) on a substrate (110, 210) having a core substrate (150, 250), through electrodes (140, 240), and wiring layers (157, 257).
  • the semiconductor element (180, 280) is bonded via the pad (182, 282) of the semiconductor element.
  • the wiring layers (157, 257) include mounting pads (165, 265), connection pads (164, 264), and wiring (266).
  • Patent Document 2 discloses a method of bonding and laminating substrates on which such semiconductor elements are bonded via solder bumps (174, 176).
  • Patent Document 2 since the semiconductor element is bonded to the wiring board by solder bumps, as in Patent Document 1, it is extremely important to increase the density of the solder bumps accompanying the downsizing of the semiconductor elements. You will face difficulties.
  • the formation of the through electrode provided on the second substrate 210 has a problem that the process is complicated and not easy.
  • Patent Document 3 shows an example of a semiconductor device mounted on a wiring board, a manufacturing method thereof, or a semiconductor device in which semiconductor elements are assembled in a laminated structure, and a manufacturing method thereof.
  • Patent Document 3 as shown in FIG. 27, an organic substrate 301, a through via 304 that penetrates the organic substrate 301 in the thickness direction, and an external portion that is provided on both surfaces of the organic substrate 301 and is electrically connected to the through via 304.
  • Patent Document 3 as shown in FIG. 28, a photosensitive resin layer 316 applied to the surface layer of a semiconductor element is patterned to form an opening 317, whereby a via portion 308 formed on the semiconductor element 302 is formed. And Further, the insulating material layer 306 formed around the semiconductor element is formed by spin coating or the like.
  • the resin since the resin has to be supplied twice, the process of applying the photosensitive resin layer 316 to the surface layer of the semiconductor element 302 and the process of forming the insulating material layer 306 around the semiconductor element 302, the process is complicated.
  • the height of the semiconductor element 302 is important, and when the height exceeds tens of ⁇ m, the semiconductor element is overcome and a void is generated. It is actually difficult to supply the insulating material layer 306.
  • the formation of the via portion 308 of the photosensitive resin layer 316 and the formation of the metal via 310 of the insulating material layer 306 are performed in separate processes, and an example in which the processing of the metal via 310 is performed by a laser or the like are shown. These processes are cumbersome and unreasonable.
  • the photosensitive resin layer 316 and the insulating material layer 306 can be simultaneously supplied to the peripheral portion of the semiconductor element 302 and the circuit formation surface, there is actually no specific method illustrated, and a gap is formed around the semiconductor element. It is difficult to supply these resin layers without generating them.
  • the via portion 308 of the photosensitive resin layer 316 and the metal via 310 of the insulating material layer 306 can be formed at the same time, a specific method is not described.
  • the present invention has been made in view of the above circumstances, and provides a semiconductor device that can be easily placed on a wiring board and stacked on a semiconductor device, and the warpage of the semiconductor device is suppressed even when the density of the metal wiring is large. With the goal. It is another object of the present invention to provide a method for manufacturing a semiconductor device, which can easily process a through electrode and an opening of an electrode pad portion when manufacturing such a semiconductor device. It is another object of the present invention to provide a stacked semiconductor device in which such semiconductor devices are stacked, a post-sealing stacked semiconductor device in which the semiconductor device is mounted on a wiring board and sealed, and a method for manufacturing the same.
  • the present invention has a semiconductor element, a metal pad on the semiconductor element and a metal wiring electrically connected to the semiconductor element, and the metal wiring is electrically connected to the through electrode and the solder bump.
  • the metal wiring is electrically connected to the semiconductor element through a metal pad on the semiconductor element on the upper surface of the second insulating layer, and penetrates the second insulating layer from the upper surface of the second insulating layer.
  • a semiconductor device electrically connected to the through electrode on the lower surface of a second insulating layer is provided.
  • the first insulating layer is formed by a photocurable dry film or a photocurable resist coating film
  • the second insulating layer is formed by the photocurable dry film
  • the third insulating layer is preferably formed of the photocurable dry film or the photocurable resist coating film.
  • the height of the semiconductor element is 20 to 100 ⁇ m
  • the thickness of the first insulating layer is 1 to 20 ⁇ m
  • the thickness of the second insulating layer is 5 to 100 ⁇ m
  • the insulating layer has a thickness of 5 to 100 ⁇ m
  • the semiconductor device has a thickness of 50 to 300 ⁇ m.
  • the photo-curable dry film is (A) a silicone skeleton-containing polymer compound having a repeating unit represented by the following general formula (1) and having a weight average molecular weight of 3,000 to 500,000, (Wherein R 1 to R 4 represent a monovalent hydrocarbon group having 1 to 8 carbon atoms which may be the same or different.
  • M is an integer of 1 to 100.
  • a, b, c and d are 0. Or, a positive number and a, b, c, and d are not simultaneously 0.
  • a + b + c + d 1
  • X is an organic group represented by the following general formula (2)
  • Y is the following general formula.
  • Z is A divalent organic group selected from any one of the following: n is 0 or 1; R 5 and R 6 are each an alkyl group or alkoxy group having 1 to 4 carbon atoms, and may be different or the same. k is 0, 1, or 2.
  • R 5 and R 6 are each an alkyl group or alkoxy group having 1 to 4 carbon atoms, and may be different or the same.
  • k is 0, 1, or 2.
  • R 7 and R 8 are each an alkyl group or alkoxy group having 1 to 4 carbon atoms, and may be different or the same.
  • h is 0, 1, or 2.
  • the present invention also provides a stacked semiconductor device in which a plurality of the above semiconductor devices are flip-chip stacked. Since the semiconductor device of the present invention can be easily stacked, it is suitable for such a stacked semiconductor device.
  • the present invention provides a post-sealing laminated semiconductor device in which the laminated semiconductor device is placed on a substrate having an electric circuit and sealed with an insulating sealing resin layer.
  • the semiconductor device of the present invention is suitable for such a post-sealing stacked semiconductor device because it is easy to mount the semiconductor device on a wiring board and to stack the semiconductor devices.
  • a method of manufacturing a semiconductor device (1) applying a temporary adhesive to the support substrate, and forming a first insulating layer having a thickness of 1 to 20 ⁇ m using the resist composition material as a photocurable resin layer on the temporary adhesive; (2) The step of patterning the first insulating layer by lithography through a mask to form a hole pattern to be a through electrode and then baking the first insulating layer by baking; (3) performing a seed layer formation by sputtering on the first insulating layer, then filling the hole pattern to be the through electrode by plating, and forming a metal wiring connected to the through electrode; (4) a step of die-bonding a semiconductor element having a height of 20 to 100 ⁇ m with an electrode pad exposed on the upper surface using a die-bonding agent on the cured first insulating layer; (5) A photocurable dry film having a structure in which a photocurable resin layer having a film thickness of 5 to 100 ⁇ m is sandwiched between a support film and
  • the second insulating layer is patterned by lithography through a mask, and the metal penetrates the second insulating layer over the opening on the electrode pad and the metal wiring connected to the through electrode.
  • a seed layer is formed by sputtering, and thereafter an opening on the electrode pad, an opening for forming a metal wiring penetrating the second insulating layer, and an opening for forming the through electrode Is embedded by plating to form a metal pad on the semiconductor element, a metal wiring penetrating the second insulating layer, and a through electrode, and the metal pad on the semiconductor element and the second insulation formed by the plating.
  • the third insulating layer is formed by laminating the photocurable resin layer of the photocurable dry film or spin-coating the resist composition material used for the photocurable dry film. And a process of (10) The third insulating layer is patterned by lithography through a mask, an opening is formed in the upper portion of the through electrode, and then the third insulating layer is cured by baking; (11) A step of forming a solder bump in the opening above the through electrode after curing, The manufacturing method of the semiconductor device which has this.
  • the photocurable dry film prepared in the step (5) contains (A) a silicone skeleton containing a repeating unit represented by the following general formula (1) and having a weight average molecular weight of 3,000 to 500,000.
  • M is an integer of 1 to 100.
  • X is an organic group represented by the following general formula (2), and Y is the following general formula.
  • Z is A divalent organic group selected from any one of the following: n is 0 or 1; R 5 and R 6 are each an alkyl group or alkoxy group having 1 to 4 carbon atoms, and may be different or the same. k is 0, 1, or 2.
  • R 5 and R 6 are each an alkyl group or alkoxy group having 1 to 4 carbon atoms, and may be different or the same.
  • k is 0, 1, or 2.
  • R 7 and R 8 are each an alkyl group or alkoxy group having 1 to 4 carbon atoms, and may be different or the same.
  • h is 0, 1, or 2.
  • the step (6) preferably includes a step of mechanically pressing the second insulating layer. Thereby, the thickness of the 2nd insulating layer on a semiconductor element can be made thin, it can equalize, and a 2nd insulating layer can be planarized.
  • the solder bump can be formed in the opening above the through electrode.
  • the step of plating with SnAg In the step (10), exposing the plated SnAg by patterning so as to form an opening above the through electrode; In the step (11), a step of forming a solder bump by raising the electrode in the opening above the through electrode by melting the plated SnAg, If it is the method which has this, a solder bump can be formed in the opening of the said penetration electrode more easily and rationally.
  • step (11) a step of removing the support substrate temporarily bonded to the first insulating layer in the step (1); After removing the substrate, the step of dicing into pieces, By performing the above, it is possible to manufacture an individual semiconductor device.
  • the following effects can be imparted. That is, when the periphery of the semiconductor element placed on the first insulating layer formed on the support substrate is embedded with a photocurable dry film using a resist composition material as a photocurable resin layer, a photocurable resin is used. Since the layer has a thickness of 5 to 100 ⁇ m, even when the height of the semiconductor element is several tens of ⁇ m, it becomes possible to embed a photocurable dry film without generating voids around the semiconductor element. Easy.
  • the light on the semiconductor device By mechanically pressing the curable resin layer (second insulating layer), it has the advantage that the film thickness can be adjusted and thinned, and the mechanical press is a photocurable resin laminated on the outer periphery of the semiconductor element. It has the advantage that the layer thickness can be made uniform and flat.
  • an opening on the electrode pad on the semiconductor element, an opening for forming a metal wiring penetrating the second insulating layer, and an opening to be a through electrode Can be simultaneously formed by patterning by lithography through a mask.
  • TMV Through Metal Via
  • the opening on the electrode pad on the semiconductor element, the opening for forming the metal wiring penetrating the second insulating layer, and the opening for forming the through electrode are filled by plating, and the metal pad on the semiconductor element and the second insulating layer By laminating a photo-curable dry film on the metal wiring that penetrates the metal element and the through electrode, and the metal wiring that penetrates the metal pad on the semiconductor element and the second insulating layer is metal-plated by plating.
  • the method of separating the support substrate after removing it is a method by which a semiconductor device can be easily manufactured.
  • a step of plating with SnAg is included, and a lamination is performed again by laminating a photo-curable dry film. After performing patterning to form an opening in the upper part, after exposing the SnAg plating, and after patterning and curing the film by baking, the SnAg filled by plating is melted to open the through electrode opening. Providing a way to raise.
  • the first insulating layer formed on the support substrate is bonded to the support substrate with a temporary adhesive, and then the support substrate is easily removed, and the support substrate is removed and then diced to remove the support substrate. It is easy and reasonable to manufacture an individual semiconductor device.
  • the upper part protrudes a solder ball or a solder bump which is a raised SnAg, and the lower part can easily expose the through electrode by removing the substrate. It is very rational because it can be easily electrically joined and stacked using solder bumps and exposed electrodes protruding from a plurality of separated semiconductor devices.
  • the warpage of the semiconductor device itself tends to increase as the wiring density increases.
  • metal wiring By forming metal wiring on both surfaces of the insulating layer, warpage of the semiconductor device itself can be suppressed even if the wiring density increases.
  • multilayer wiring will be required to cope with the increase in the number of signals in the semiconductor device. Therefore, it is important to minimize the warpage of the semiconductor device itself.
  • the semiconductor device of the present invention provided with wiring can be extremely reduced in warpage, and thus is suitable for multilayer wiring.
  • the chemically amplified negative resist composition material in the present invention is used for the photocurable resin layer, it is possible to reduce the warpage of the semiconductor device which is a concern when separated into individual pieces. It is suitable for mounting on a wiring board.
  • a fine electrode is formed on a semiconductor element, and a through electrode is provided outside the semiconductor element, so that the semiconductor device can be placed on a wiring board or stacked on the semiconductor device.
  • the semiconductor element is embedded without voids around the semiconductor element, and even when the density of the metal wiring is high, the semiconductor device can be prevented from warping.
  • a fine electrode is formed on a semiconductor element, and a through electrode is provided on the outside of the semiconductor element, so that mounting on a wiring board and stacking of semiconductor devices can be easily performed.
  • the semiconductor device of the present invention can be easily mounted on a wiring board and stacked on the wiring board, a stacked semiconductor device in which semiconductor devices are stacked and the semiconductor board mounted on the wiring board are mounted. It is possible to obtain a stacked semiconductor device after sealing which is placed and sealed.
  • a first insulating layer is formed using a resist composition material on a support substrate coated with a temporary adhesive, and the first insulating layer is patterned to form a hole pattern to be a through electrode.
  • a hole pattern to be a through electrode is filled by plating to form a metal wiring connected to the through electrode, and a semiconductor element is die-bonded on the first insulating layer.
  • the film is embedded without generating voids around the semiconductor element. (Formation of the second insulating layer).
  • an opening on the electrode pad, an opening for forming a metal wiring penetrating the second insulating layer, and a through electrode are formed. Since it was possible to form the openings simultaneously, it was found that they could be easily processed, and the present invention was achieved.
  • the opening on the electrode pad, the opening for forming the metal wiring penetrating the second insulating layer, and the opening for forming the through electrode are plated.
  • the metal pad on the semiconductor element, the metal wiring penetrating the second insulating layer, and the penetrating electrode are formed, and the metal pad penetrating the semiconductor element on the semiconductor element and the metal wiring penetrating the second insulating layer are formed by plating. Connected by metal wiring by plating.
  • a third insulating layer is formed from above, and patterning is performed on the third insulating layer to form an opening above the through electrode, and after curing, a solder bump is formed in this opening.
  • removing the support substrate that has been bonded with the temporary adhesive and dividing it into individual pieces by dicing is a very rational method for forming a semiconductor device and embodies the object of the present invention. .
  • the semiconductor device manufactured by the above manufacturing method can suppress warping of the semiconductor device itself even when the wiring density is increased by forming metal wiring on both surfaces of the second insulating layer.
  • the semiconductor device manufactured by the above manufacturing method has a solder bump that protrudes from the plurality of semiconductor devices because the solder bumps protrude from the upper part, and the through electrode can be easily exposed by removing the support substrate from the lower part.
  • the exposed electrodes the inventors have found that they can be easily electrically joined and stacked, and have found that the stacked semiconductor devices can be easily placed on a wiring board, thereby completing the present invention.
  • the present invention has a semiconductor device, a semiconductor device having a metal pad and a metal wiring on the semiconductor element electrically connected to the semiconductor element, and the metal wiring is electrically connected to the through electrode and the solder bump. Because A first insulating layer on which the semiconductor element is placed; a second insulating layer formed on the semiconductor element; and a third insulating layer formed on the second insulating layer; The metal wiring is electrically connected to the semiconductor element through a metal pad on the semiconductor element on the upper surface of the second insulating layer, and penetrates the second insulating layer from the upper surface of the second insulating layer. In the semiconductor device, the lower surface of the second insulating layer is electrically connected to the through electrode.
  • the semiconductor device 1 of the present invention includes a semiconductor element 2, a semiconductor element upper metal pad 3 and a metal wiring 4 electrically connected to the semiconductor element 2, and the metal wiring 4 is a through electrode. 5 and a solder bump 6, which are electrically connected to the semiconductor device 2, a first insulating layer 7 on which the semiconductor element 2 is placed, a second insulating layer 8 formed on the semiconductor element 2, and a second A third insulating layer 9 formed on the insulating layer 8;
  • the metal wiring 4 is electrically connected to the semiconductor element 2 via the metal pad 3 on the semiconductor element on the upper surface of the second insulating layer 8, and penetrates the second insulating layer 8 from the upper surface of the second insulating layer 8.
  • the semiconductor device is electrically connected to the through electrode 5 on the lower surface of the two insulating layers 8.
  • the metal wiring 4 is a metal wiring (upper surface metal wiring) 4 a connected to the semiconductor element upper metal pad 3 on the upper surface of the second insulating layer 8, and a metal connected to the through electrode 5 on the lower surface of the second insulating layer 8.
  • the wiring (bottom metal wiring) 4b and the metal wiring (through metal wiring) 4c that penetrates the second insulating layer 8 and connects the top metal wiring 4a and the bottom metal wiring 4b.
  • the semiconductor element 2 is die-bonded to the first insulating layer 7 with a die bonding agent 10.
  • the first insulating layer 7 is formed of a photocurable dry film or a photocurable resist coating film
  • the second insulating layer 8 is formed of a photocurable dry film. If the three insulating layers 9 are formed of a photocurable dry film or a photocurable resist coating film, even if the height of the semiconductor element 2 is several tens of ⁇ m, it is embedded without any voids around the semiconductor element. Therefore, it is preferable.
  • the height of the semiconductor element 2 is 20 to 100 ⁇ m
  • the thickness of the first insulating layer 7 is 1 to 20 ⁇ m
  • the thickness of the second insulating layer 8 is 5 to 100 ⁇ m
  • the thickness of the layer 9 is 5 to 100 ⁇ m
  • the thickness of the semiconductor device 1 is 50 to 300 ⁇ m, it is preferable that the semiconductor device 1 is embedded without voids around the semiconductor element and becomes a thin semiconductor device.
  • the photocurable dry film used for forming the first insulating layer 7, the second insulating layer 8, and the third insulating layer 9 suppresses warpage, reduces residual stress, reliability, and processing characteristics.
  • a photocurable dry film having a photocurable resin layer composed of a chemically amplified negative resist composition material containing the following components (A) to (D) is preferable.
  • other photosensitive resins can also be used.
  • the component (A) is a silicone skeleton-containing polymer compound having a repeating unit represented by the following general formula (1) and having a weight average molecular weight of 3,000 to 500,000.
  • R 1 to R 4 represent a monovalent hydrocarbon group having 1 to 8 carbon atoms which may be the same or different.
  • M is an integer of 1 to 100.
  • a, b, c and d are 0. Or, a positive number and a, b, c, and d are not simultaneously 0.
  • a + b + c + d 1
  • X is an organic group represented by the following general formula (2)
  • Y is the following general formula.
  • Z is A divalent organic group selected from any one of the following: n is 0 or 1; R 5 and R 6 are each an alkyl group or alkoxy group having 1 to 4 carbon atoms, and may be different or the same. k is 0, 1, or 2.
  • R 5 and R 6 are each an alkyl group or alkoxy group having 1 to 4 carbon atoms, and may be different or the same.
  • k is 0, 1, or 2.
  • R 7 and R 8 are each an alkyl group or alkoxy group having 1 to 4 carbon atoms, and may be different or the same.
  • h is 0, 1, or 2.
  • Component (B) is an amino condensate modified with formaldehyde or formaldehyde-alcohol, one or two or more selected from phenol compounds having an average of two or more methylol groups or alkoxymethylol groups in one molecule. It is a crosslinking agent.
  • Component (C) is a photoacid generator that decomposes with light having a wavelength of 190 to 500 nm to generate an acid.
  • a component is a solvent.
  • crosslinking agent for the component (B) known ones can be used.
  • 1 type (s) or 2 or more types chosen from the phenolic compound which has group can be used.
  • amino condensate modified with formaldehyde or formaldehyde-alcohol examples include melamine condensate modified with formaldehyde or formaldehyde-alcohol, or urea condensate modified with formaldehyde or formaldehyde-alcohol. These modified melamine condensates and modified urea condensates can be used alone or in combination.
  • phenol compound having an average of two or more methylol groups or alkoxymethylol groups in one molecule examples include (2-hydroxy-5-methyl) -1,3-benzenedimethanol, 2,2 ′, Examples include 6,6′-tetramethoxymethylbisphenol A.
  • these phenol compounds can be used 1 type or in mixture of 2 or more types.
  • an acid generator which generates an acid upon irradiation with light having a wavelength of 190 to 500 nm and becomes a curing catalyst can be used.
  • photoacid generators include onium salts, diazomethane derivatives, glyoxime derivatives, ⁇ -ketosulfone derivatives, disulfone derivatives, nitrobenzyl sulfonate derivatives, sulfonate ester derivatives, imido-yl-sulfonate derivatives, oxime sulfonate derivatives, iminosulfonates. Derivatives, triazine derivatives and the like.
  • a solvent in which (A) a silicone skeleton-containing polymer compound, (B) a crosslinking agent, and (C) a photoacid generator can be dissolved can be used.
  • solvents include ketones such as cyclohexanone, cyclopentanone, and methyl-2-n-amyl ketone; 3-methoxybutanol, 3-methyl-3-methoxybutanol, 1-methoxy-2-propanol, 1- Alcohols such as ethoxy-2-propanol; ethers such as propylene glycol monomethyl ether, ethylene glycol monomethyl ether, propylene glycol monoethyl ether, ethylene glycol monoethyl ether, propylene glycol dimethyl ether, diethylene glycol dimethyl ether; propylene glycol monomethyl ether acetate, propylene Glycol monoethyl ether acetate, ethyl lactate, ethyl
  • the first insulating layer 7 and the third insulating layer 9 are photo-curable resists obtained by applying a chemically amplified negative resist composition material containing the above components (A) to (D) by spin coating or the like. It may be a coating film or, of course, a photocurable resist coating film in which another photosensitive resin is applied by spin coating or the like.
  • the present invention provides a stacked semiconductor device in which a plurality of the above semiconductor devices are flip-chip stacked.
  • the stacked semiconductor device 11 of the present invention is a device in which the above-described semiconductor device 1 is flip-chiped and electrically joined by the through electrode 5 and the solder bump 6, and a plurality of stacked layers are stacked.
  • An insulating resin layer 12 may be sealed between the semiconductor devices.
  • the present invention provides a post-sealing laminated semiconductor device in which the laminated semiconductor device is placed on a substrate having an electric circuit and sealed with an insulating sealing resin layer.
  • the post-sealing laminated semiconductor device 13 of the present invention is mounted on the substrate (wiring substrate 14) having the electric circuit described above via the solder bumps 6 as shown in FIG. And sealed with an insulating sealing resin layer 15.
  • a method for manufacturing a semiconductor device of the present invention includes: (1) applying a temporary adhesive to the support substrate, and forming a first insulating layer having a thickness of 1 to 20 ⁇ m using the resist composition material as a photocurable resin layer on the temporary adhesive; (2) The step of patterning the first insulating layer by lithography through a mask to form a hole pattern to be a through electrode and then baking the first insulating layer by baking; (3) performing a seed layer formation by sputtering on the first insulating layer, then filling the hole pattern to be the through electrode by plating, and forming a metal wiring connected to the through electrode; (4) a step of die-bonding a semiconductor element having a height of 20 to 100 ⁇ m with an electrode pad exposed on the upper surface using a die-bonding agent on the cured first insulating layer; (5) A photocurable dry film having a structure in which a photocurable resin layer having
  • the second insulating layer is patterned by lithography through a mask, and the metal penetrates the second insulating layer over the opening on the electrode pad and the metal wiring connected to the through electrode.
  • a seed layer is formed by sputtering, and thereafter an opening on the electrode pad, an opening for forming a metal wiring penetrating the second insulating layer, and an opening for forming the through electrode Is embedded by plating to form a metal pad on the semiconductor element, a metal wiring penetrating the second insulating layer, and a through electrode, and the metal pad on the semiconductor element and the second insulation formed by the plating.
  • the third insulating layer is formed by laminating the photocurable resin layer of the photocurable dry film or spin-coating the resist composition material used for the photocurable dry film. And a process of (10) The third insulating layer is patterned by lithography through a mask, an opening is formed in the upper portion of the through electrode, and then the third insulating layer is cured by baking; (11) A step of forming a solder bump in the opening above the through electrode after curing, Have
  • step (1) as shown in FIG. 4, a temporary adhesive 17 is applied to the support substrate 16, and a resist composition material is used as a photocurable resin layer on the temporary adhesive 17 to obtain a film thickness of 1 to 1.
  • a 20 ⁇ m first insulating layer 7 is formed.
  • the support substrate 16 For example, a silicon wafer, a glass substrate, etc. can be used.
  • the temporary adhesive 17 is not particularly limited, but for example, a thermoplastic resin is preferable. Examples include olefin-based thermoplastic elastomers, polybutadiene-based thermoplastic elastomers, styrene-based thermoplastic elastomers, styrene-butadiene-based thermoplastic elastomers, and styrene-polyolefin-based thermoplastic elastomers. Is preferred.
  • the first insulating layer 7 is, for example, a photocurable dry layer having a photocurable resin layer made of a chemically amplified negative resist composition material containing the components (A) to (D). It can be formed by laminating using a film or by applying the resist composition material by spin coating or the like. Of course, other photosensitive resins can also be used.
  • the film thickness of the first insulating layer is 1 to 20 ⁇ m, preferably 5 to 10 ⁇ m. Such a film thickness is preferable because the semiconductor device to be manufactured can be thinned.
  • the first insulating layer 7 is patterned by lithography through a mask, and a hole pattern A to be a through electrode is formed as shown in FIG.
  • the insulating layer 7 is cured.
  • a pattern can be formed using a known lithography technique.
  • preheating may be performed as necessary.
  • Pre-baking can be performed, for example, at 40 to 140 ° C. for about 1 minute to 1 hour.
  • the film is exposed to light with a wavelength of 190 to 500 nm through a photomask and cured.
  • the photomask may be formed by cutting a desired pattern.
  • the material of the photomask is preferably a material that shields light having a wavelength of 190 to 500 nm.
  • chromium is preferably used, but is not limited thereto.
  • Examples of light having a wavelength of 190 to 500 nm include light of various wavelengths generated by a radiation generator, for example, ultraviolet light such as g-line and i-line, deep ultraviolet light (248 nm, 193 nm), and the like.
  • the wavelength is preferably 248 to 436 nm.
  • the exposure dose is preferably 10 to 3,000 mJ / cm 2 , for example.
  • PEB is performed to increase the development sensitivity.
  • PEB can be, for example, at 40 to 140 ° C. for 0.5 to 10 minutes.
  • a preferred developer includes an organic solvent such as IPA or PGMEA.
  • a preferred alkaline aqueous developer is, for example, a 2.38% tetramethylhydroxyammonium (TMAH) aqueous solution.
  • TMAH tetramethylhydroxyammonium
  • an organic solvent is preferably used as the developer. Development can be performed by a normal method, for example, by immersing a substrate on which a pattern is formed in a developer. Thereafter, washing, rinsing, drying, and the like are performed as necessary to obtain a film (first insulating layer) of the photocurable resin layer having a desired pattern.
  • the first insulating layer thus patterned is baked using an oven or a hot plate, preferably at a temperature of 100 to 250 ° C., more preferably 150 to 220 ° C., and even more preferably 170 to 190 ° C. And cured (post-curing). If the post-curing temperature is 100 to 250 ° C., the crosslink density of the first insulating layer can be increased and the remaining volatile components can be removed, which is preferable from the viewpoint of adhesion to the support substrate, heat resistance and strength, and electrical characteristics.
  • the post-curing time can be 10 minutes to 10 hours.
  • step (3) a seed layer is formed on the first insulating layer 7 by sputtering, and then the hole pattern A to be a through electrode is filled by plating, and the metal connected to the through electrode as shown in FIG. Wiring (lower surface metal wiring) 4b is formed.
  • the lower surface metal wiring 4b is formed. After forming the metal wiring, the seed layer is removed by etching, and the first insulating layer 7 is exposed.
  • the lower surface metal wiring 4b may be appropriately adjusted to have a desired wiring width, but is preferably formed on the first insulating layer so as to have a thickness of 0.1 to 10 ⁇ m.
  • step (4) as shown in FIG. 7, the semiconductor element 2 having a height of 20 to 100 ⁇ m with the electrode pad exposed on the upper surface is applied onto the cured first insulating layer 7 with the die bonding agent 10.
  • the die bonding agent 10 may be a known adhesive. Further, it is preferable that the height of the semiconductor element 2 is 20 to 100 ⁇ m because the semiconductor device to be manufactured can be thinned.
  • a photocurable resin layer having a film thickness of 5 to 100 ⁇ m has a structure sandwiched between a support film and a protective film, and the photocurable resin layer is a light comprising a resist composition material.
  • the photocurable resin layer is a light comprising a resist composition material.
  • the photocurable dry film used for this invention has a structure in which a photocurable resin layer having a thickness of 5 to 100 ⁇ m is sandwiched between a support film and a protective film. And the photocurable resin layer is made of a resist composition material.
  • the thickness of the photocurable resin layer of the photocurable dry film used for forming the second insulating layer is 5 to 100 ⁇ m. This is preferable because the semiconductor device to be manufactured can be thinned. In addition, what is necessary is just to prepare and use what made the film thickness of the photocurable resin layer arbitrary, when using a photocurable dry film for formation of a 1st insulating layer and a 3rd insulating layer.
  • each component of the composition of the photosensitive material is stirred and mixed, and then filtered through a filter or the like to prepare a resist composition material for forming a photocurable resin layer.
  • a resist composition material a chemically amplified negative resist composition material containing the above-described components (A) to (D) is suitable.
  • other photosensitive resins can also be used.
  • the support film used in the photocurable dry film used in the present invention may be a single film or a multilayer film in which a plurality of polymer films are laminated.
  • the dry film is a film sandwiched between a support film and a protective film.
  • the material of the support film include synthetic resin films such as polyethylene, polypropylene, polycarbonate, and polyethylene terephthalate, and polyethylene terephthalate having appropriate flexibility, mechanical strength, and heat resistance is preferable. Further, these films may be subjected to various treatments such as corona treatment or a release agent.
  • the protective film used in the photocurable dry film used in the present invention may be the same as the above-described support film, but polyethylene terephthalate and polyethylene having moderate flexibility are preferable. Commercially available products can be used. Examples of polyethylene terephthalate include those already exemplified, and examples of polyethylene include GF-8 (manufactured by Tamapoly Co., Ltd.) and PE film 0 type (manufactured by Nipper Co., Ltd.). .
  • the thicknesses of the support film and the protective film are preferably 5 to 100 ⁇ m from the viewpoints of the stability of photocurable dry film production and curling against the winding core, so-called curling prevention.
  • a film coater for producing a pressure-sensitive adhesive product can be used as the photocurable dry film production apparatus.
  • the film coater include a comma coater, a comma reverse coater, a multi coater, a die coater, a lip coater, a lip reverse coater, a direct gravure coater, an offset gravure coater, a three bottom reverse coater, and a four bottom reverse coater. It is done.
  • a resist composition material is applied with a predetermined thickness on the support film to form a photocurable resin layer
  • a photocurable resin layer that has been passed through a hot-air circulating oven at a predetermined temperature and a predetermined time and dried on a support film is laminated at a predetermined pressure together with a protective film that has been unwound from another unwinding shaft of the film coater.
  • the film is manufactured by passing the roll and pasting it with the photocurable resin layer on the support film, and then winding it on the winding shaft of the film coater.
  • the temperature of the hot air circulating oven is preferably 25 to 150 ° C.
  • the passage time is preferably 1 to 100 minutes
  • the pressure of the laminate roll is preferably 0.01 to 5 MPa.
  • a photocurable dry film can be produced by the above-described method, and by using such a photocurable dry film, a semiconductor element placed on the first insulating layer on the support substrate is embedded. It has excellent characteristics and can relieve stress that occurs when the support substrate is removed after the semiconductor device is formed or when the semiconductor device is separated. It is suitable for stacking or mounting on a substrate provided with wiring.
  • step (6) the protective film is peeled off from the photocurable dry film prepared as described above, and the semiconductor die-bonded onto the first insulating layer 7 as shown in FIG. 8 (a).
  • a second insulating layer 8 is formed by laminating a photocurable resin layer of a photocurable dry film so as to cover the element 2.
  • a vacuum laminator is preferable as an apparatus for attaching the photocurable dry film. Attach a photocurable dry film to the device, peel off the protective film of the photocurable dry film and expose the exposed photocurable resin layer in a vacuum chamber with a predetermined degree of vacuum, using an adhesive roll with a predetermined pressure, The substrate is brought into close contact with the substrate at a predetermined temperature.
  • the temperature is preferably 60 to 120 ° C.
  • the pressure is preferably 0 to 5.0 MPa
  • the vacuum is preferably 50 to 500 Pa. It is preferable to perform vacuum laminating without generating voids around the semiconductor element.
  • the film thickness of the second insulating layer 8 on the semiconductor element 2 may gradually decrease as the distance from the semiconductor element 2 increases.
  • a method of flattening by mechanically pressing the change in the film thickness and reducing the film thickness on the semiconductor element as shown in FIG. 8A can be preferably used.
  • step (7) as shown in FIG. 9, the second insulating layer 8 is patterned by lithography through a mask, and the metal connected to the opening B on the electrode pad and the through electrode is formed. Baking after simultaneously forming an opening C for forming a metal wiring (through metal wiring) penetrating the second insulating layer and an opening D for forming a through electrode on the wiring (lower surface metal wiring) 4b. Then, the second insulating layer 8 is cured.
  • a pattern can be formed using a known lithography technique and may be performed by the same method as the patterning of the first insulating layer.
  • the opening B on the electrode pad, the opening C for forming the through metal wiring, and the opening D for forming the through electrode are simultaneously formed by collective exposure. Is.
  • step (8) as shown in FIG. 10, after the second insulating layer 8 is cured, a seed layer is formed by sputtering, and then the opening B on the electrode pad and the metal penetrating the second insulating layer are formed.
  • the opening C for forming the wiring (through metal wiring) and the opening D for forming the through electrode are filled by plating, and the metal wiring (through metal) penetrating the semiconductor element upper metal pad 3 and the second insulating layer.
  • (Wiring) 4c and through electrode 5 are formed, and metal wiring (through metal wiring) 4c penetrating through the metal pad 3 on the semiconductor element and the second insulating layer formed by plating and metal wiring (upper surface metal wiring) by plating is formed. ) Connect with 4a.
  • step (3) When performing plating, as in the above-described step (3), for example, after forming a seed layer by sputtering, patterning of a plating resist is performed, followed by electrolytic plating, The through metal wiring 4c and the through electrode 5 are formed, and the upper surface metal wiring 4a is formed to connect the semiconductor element upper metal pad 3 and the through metal wiring 4c.
  • the upper surface metal wiring 4a may be appropriately adjusted so as to have a desired wiring width, but is preferably formed on the second insulating layer so as to have a thickness of 0.1 to 10 ⁇ m.
  • the through electrode 5 may be separately subjected to electrolytic plating, and the through electrode 5 may be filled with the metal plating 18. Further, in order to satisfy the plating of the through metal wiring 4c, the through metal wiring 4c may be separately subjected to electrolytic plating again.
  • step (9) after forming the metal wiring, the photocurable resin layer of the photocurable dry film is laminated, or the resist composition material used for the photocurable dry film is spin-coated. As shown in FIG. 12, the third insulating layer 9 is formed.
  • the formation of the third insulating layer 9 is similar to the formation of the first insulating layer described above, for example, a photocurable resin made of a chemically amplified negative resist composition material containing components (A) to (D). Lamination can be performed using a photocurable dry film having a layer, or the resist composition material can be applied by spin coating or the like. Of course, other photosensitive resins can also be used. A thickness of the third insulating layer of 5 to 100 ⁇ m is preferable because the semiconductor device to be manufactured can be thinned.
  • step (10) the third insulating layer 9 is patterned by lithography through a mask to form an opening E above the through electrode 5 and then baked.
  • the third insulating layer 9 is cured.
  • a pattern can be formed using a known lithography technique and may be performed by the same method as the patterning of the first insulating layer.
  • a solder bump is formed in the opening E above the through electrode.
  • a method for forming a solder bump for example, as shown in FIG. 14, a metal pad 19 on the through electrode is formed in the opening E above the through electrode by plating.
  • a solder ball 20 can be formed on the through electrode upper metal pad 19 and used as a solder bump.
  • step (8) a separate plating for satisfying the plating of the through electrode 5 is performed with SnAg and the SnAg plating 21 is performed, and in the subsequent step (9), the same as the above In step (10), the third insulating layer 9 is formed, and the SnAg plating 21 is exposed by patterning so as to form the opening E above the through electrode in step (10), followed by curing by baking, as step (11).
  • the electrode By melting the SnAg plating 21, the electrode can be raised to the opening E above the through electrode as shown in FIG. 16, and the solder bump of the electrode 22 with the raised SnAg can be formed.
  • the solder ball 20 of the through electrode 5 is removed. Can be exposed, the exposed seed layer is removed by etching, and the metal plating portion is exposed, whereby the upper and lower portions of the through electrode 5 can be electrically connected. it can. Further, the semiconductor device 23 can be obtained by dicing into individual pieces.
  • the support substrate 16 is removed as shown in FIG.
  • the metal wiring 4b) can be exposed, the exposed seed layer is removed by etching, and the metal plating portion is exposed, whereby the upper and lower portions of the through electrode 5 can be electrically connected. Furthermore, after that, the semiconductor device 24 separated into pieces can be obtained by dicing into pieces.
  • the manufacturing method of the present invention as described above is particularly suitable for downsizing and thinning, and a thin and compact semiconductor device having a thickness of 50 to 300 ⁇ m, more preferably 70 to 150 ⁇ m as a semiconductor device. Can be obtained.
  • the above-described individual semiconductor device 23 or individual semiconductor device 24 is electrically joined by solder bumps with the insulating resin layer 12 interposed therebetween.
  • a stacked semiconductor device can be obtained by stacking.
  • the stacked semiconductor devices can be mounted on a substrate (wiring substrate 14) having an electric circuit.
  • 19, 20, 21, and 22 are examples of flip-chip bonding of individual semiconductor devices 23 or 24.
  • Type semiconductor device can be manufactured.
  • the resin used for the insulating resin layer 12 and the insulating sealing resin layer 15 can be used, and for example, epoxy resins, silicone resins, and hybrid resins thereof can be used. .
  • the semiconductor device, stacked semiconductor device, and post-sealing stacked semiconductor device of the present invention manufactured as described above are suitable for fan-out wiring and WCSP (wafer level chip size package) applied to a semiconductor chip. Can be used.
  • WCSP wafer level chip size package
  • a fine electrode is formed on a semiconductor element, and a through electrode is provided outside the semiconductor element, so that the semiconductor device can be placed on a wiring board or stacked on the semiconductor device.
  • the semiconductor element is embedded without voids around the semiconductor element, and even when the density of the metal wiring is high, the semiconductor device can be prevented from warping.
  • a fine electrode is formed on a semiconductor element, and a through electrode is provided on the outside of the semiconductor element, so that mounting on a wiring board and stacking of semiconductor devices can be easily performed.
  • the semiconductor device of the present invention can be easily mounted on a wiring board and stacked on the wiring board, a stacked semiconductor device in which semiconductor devices are stacked and the semiconductor board mounted on the wiring board are mounted. It is possible to obtain a stacked semiconductor device after sealing which is placed and sealed.
  • the present invention is not limited to the above embodiment.
  • the above-described embodiment is an exemplification, and the present invention has any configuration that has substantially the same configuration as the technical idea described in the claims of the present invention and that exhibits the same effects. Are included in the technical scope.

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PCT/JP2015/001433 2014-03-31 2015-03-16 半導体装置、積層型半導体装置、封止後積層型半導体装置、及びこれらの製造方法 Ceased WO2015151426A1 (ja)

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CN201580018117.5A CN106415823B (zh) 2014-03-31 2015-03-16 半导体装置、积层型半导体装置、密封后积层型半导体装置以及这些装置的制造方法
US15/126,116 US10141272B2 (en) 2014-03-31 2015-03-16 Semiconductor apparatus, stacked semiconductor apparatus and encapsulated stacked-semiconductor apparatus each having photo-curable resin layer
EP15772875.9A EP3128548B1 (en) 2014-03-31 2015-03-16 Semiconductor apparatus, stacked semiconductor apparatus; encapsulated stacked-semiconductor, and method for manufacturing same
KR1020167027165A KR102263433B1 (ko) 2014-03-31 2015-03-16 반도체장치, 적층형 반도체장치, 봉지후 적층형 반도체장치, 및 이들의 제조방법

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CN106415823A (zh) 2017-02-15
TWI648438B (zh) 2019-01-21
US20170077043A1 (en) 2017-03-16
EP3128548A4 (en) 2017-12-13
TW201600651A (zh) 2016-01-01
JP2015195238A (ja) 2015-11-05
KR20160138082A (ko) 2016-12-02
US10141272B2 (en) 2018-11-27
JP6031059B2 (ja) 2016-11-24
KR102263433B1 (ko) 2021-06-11
CN106415823B (zh) 2019-03-05
EP3128548A1 (en) 2017-02-08

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