TWI648438B - Semiconductor device, laminated semiconductor device, packaged laminated semiconductor device, and manufacturing method therefor - Google Patents

Semiconductor device, laminated semiconductor device, packaged laminated semiconductor device, and manufacturing method therefor Download PDF

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Publication number
TWI648438B
TWI648438B TW104110257A TW104110257A TWI648438B TW I648438 B TWI648438 B TW I648438B TW 104110257 A TW104110257 A TW 104110257A TW 104110257 A TW104110257 A TW 104110257A TW I648438 B TWI648438 B TW I648438B
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Taiwan
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insulating layer
semiconductor device
electrode
semiconductor element
forming
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TW104110257A
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English (en)
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TW201600651A (zh
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竹村勝也
曽我恭子
淺井聡
近藤和紀
菅生道博
加藤英人
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日商信越化學工業股份有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/562—Protection against mechanical damage
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • C—CHEMISTRY; METALLURGY
    • C08—ORGANIC MACROMOLECULAR COMPOUNDS; THEIR PREPARATION OR CHEMICAL WORKING-UP; COMPOSITIONS BASED THEREON
    • C08L—COMPOSITIONS OF MACROMOLECULAR COMPOUNDS
    • C08L83/00—Compositions of macromolecular compounds obtained by reactions forming in the main chain of the macromolecule a linkage containing silicon with or without sulfur, nitrogen, oxygen or carbon only; Compositions of derivatives of such polymers
    • C08L83/14—Compositions of macromolecular compounds obtained by reactions forming in the main chain of the macromolecule a linkage containing silicon with or without sulfur, nitrogen, oxygen or carbon only; Compositions of derivatives of such polymers in which at least two but not all the silicon atoms are connected by linkages other than oxygen atoms
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    • C09D163/00—Coating compositions based on epoxy resins; Coating compositions based on derivatives of epoxy resins
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    • C09D183/00—Coating compositions based on macromolecular compounds obtained by reactions forming in the main chain of the macromolecule a linkage containing silicon, with or without sulfur, nitrogen, oxygen, or carbon only; Coating compositions based on derivatives of such polymers
    • C09D183/14—Coating compositions based on macromolecular compounds obtained by reactions forming in the main chain of the macromolecule a linkage containing silicon, with or without sulfur, nitrogen, oxygen, or carbon only; Coating compositions based on derivatives of such polymers in which at least two but not all the silicon atoms are connected by linkages other than oxygen atoms
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    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
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    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
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    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
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    • G—PHYSICS
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    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
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    • G03F7/004—Photosensitive materials
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Abstract

本發明之課題為提供一種對於配線基板之載置或半導體裝置之層合為容易，且即使於金屬配線之密度大的情況中半導體裝置之翹曲亦受到抑制的半導體裝置。
本發明之解決手段為一種半導體裝置，其係具有半導體元件、與電連接於半導體元件的半導體元件上金屬墊及金屬配線，金屬配線係電連接於貫穿電極及焊錫凸塊，且具有：載置有半導體元件之第一絕緣層、形成於半導體元件上之第二絕緣層、以及形成於第二絕緣層上之第三絕緣層，金屬配線係在第二絕緣層的上面經由半導體元件上金屬墊而電連接於半導體元件，且從第二絕緣層的上面貫穿第二絕緣層而在第二絕緣層的下面電連接於貫穿電極。

Description

半導體裝置、層合型半導體裝置、封裝後層合型半導體裝置及此等之製造方法
本發明係關於半導體裝置、層合型半導體裝置、封裝後層合型半導體裝置、及此等之製造方法。
伴隨著個人電腦、數位相機、行動電話等各種的電子機器之小型化或高性能化，對於半導體元件之更加小型化、薄型化及高密度化的要求亦急速高漲。因此，期望開發可對應於生產性提昇之基板面積的增大，且在晶片尺寸封裝或晶片規模封裝(CSP)或者立體層合之高密度安裝技術中能夠對應的感光性絕緣材料或加以層合之半導體裝置、其製造方法。
以往，作為將形成於半導體元件上之電極與基板上形成的配線圖型連接所得之半導體裝置的製造方法，係可列舉以線結合所致之半導體元件與基板之接合為例。然而，於以線結合所致之半導體元件與基板之接合中，係必須於半導體元件上配置將金屬線拉出的空間，因此裝置會變大，而難以謀求小型化。
另一方面，於專利文獻1、2中揭示出不使用線結合而將半導體元件載置於配線基板的例子，或將半導體元件載置於立體層合並施以配線之基板的方法。
於專利文獻1中係揭示出具有如受光元件或發光元件般之半導體元件的半導體裝置之製造方法的例子，如第25圖所示般，半導體裝置50係經由貫穿電極56來將Al電極墊55與再配線圖型52進行連接，並將半導體裝置之再配線圖型52與配線基板53上之再配線圖型57經由焊錫凸塊58進行連接的例子。
於半導體裝置的上面係形成有裝置形成層59與複數個Al電極墊55。於Al電極墊55與再配線圖型52之間係藉由乾蝕刻而設置有貫穿半導體裝置之貫穿孔54，於貫穿孔54的內部係藉由Cu鍍敷而形成有貫穿電極56。裝置形成層59係配置於半導體裝置的上面，進行受光或發光。
依據此方法，雖可進行以線結合所致之半導體元件51與配線基板53的接合，但必須於半導體裝置上實施再配線，且配置焊錫凸塊，使伴隨著半導體裝置之小型化的再配線之微細化、焊錫凸塊之高密度化成為必要，而在實際面上遭遇困難。
另一方面，於專利文獻2中係揭示出可用於複數個半導體元件之立體層合的半導體裝置之製造方法，如第26圖所示般，例示將半導體元件180與半導體元件280進行層合的結構。
加以層合的各半導體元件，係於具有芯基材(150、250)、貫穿電極(140、240)與配線層(157、257)的基板(110、210)上，經由焊錫凸塊(170、270)與半導體元件之墊(182、282)而接合有半導體元件(180、280)者。又，配線層(157、257)係具有安裝墊(165、265)、連接墊(164、264)、以及配線(266)。再者，於基板(110、210)之最表面與半導體元件(180、280)之間係填充有底部填充材(184、284)。於專利文獻2中揭示出將如此之接合有半導體元件的基板經由焊錫凸塊(174、176)來進行接合並層合的方法。
然而，於專利文獻2中，由於是將半導體元件藉由焊錫凸塊來接合於配線基板，因此與專利文獻1相同地，使伴隨著半導體元件之小型化的焊錫凸塊之高密度化成為極重要的一環，而實際上亦遭遇困難。又，設置於第2基板210之貫穿電極的形成係存在有其步驟煩雜且並非容易的問題點。
又，於專利文獻3係揭示出將載置於配線基板的半導體裝置或其製造方法或者將半導體元件組裝於層合結構的半導體裝置或其製造方法的例子。於專利文獻3中係如第27圖所示般，揭示出一種半導體裝置，或將此半導體裝置載置於配線基板的半導體裝置、將複數個半導體元件進行層合的半導體裝置之製造方法，該半導體裝置係包含：有機基板301、在厚度方向貫穿有機基板301之貫穿孔304、設置於有機基板301之兩面，且電連接於貫 穿孔304之外部電極305b及內部電極305a、經由接著層303以元件電路面為上來搭載於有機基板301之其中一方的主面上之半導體元件302、將半導體元件302及其周邊進行封裝之絕緣材料層306、設置於絕緣材料層306內，且其一部分露出於外部表面之金屬薄膜配線層307、電連接於金屬薄膜配線層307之金屬孔310、配線保護膜311、與形成於金屬薄膜配線層307上之外部電極309，且金屬薄膜配線層307係具有將配置於半導體元件302之元件電路面的電極、內部電極305a、金屬孔310、與形成於金屬薄膜配線層307上的外部電極309電連接的結構。依據專利文獻3，無須於半導體元件上形成多數個焊錫凸塊，可於半導體元件上形成多數個電極，而成為能夠與高密度化相對應地進行半導體裝置之小型化。
然而，不可否認於上述專利文獻3所記載之半導體裝置的結構體中，對於配線基板之貫穿孔304的形成係有加工困難的情形。雖可例示使用了微細鑽孔之加工或雷射加工，但在期望更進一步之半導體裝置的微細化之際，並不能說是理想的加工技術。
又，於專利文獻3中，係如第28圖所示般，將塗佈於半導體元件表層的感光性樹脂層316進行圖型化，形成開口317，藉此製成形成於半導體元件302上之孔部308。進而，形成於半導體元件之周邊的絕緣材料層306係使用旋轉塗佈等來形成。然而，實際上由於將感光性樹脂層316塗佈於半導體元件302表層的步驟、與於半 導體元件302周邊形成絕緣材料層306的步驟，2次都必須供給樹脂，因此步驟煩雜，又，在以旋轉塗佈進行絕緣材料層306之供給的情況中，半導體元件302的高度係為重要，在如超過數十μm般之高度時，要越過半導體元件而不產生間隙地供給絕緣材料層306實際上係有困難。再者，雖例示出藉由另外的步驟來進行感光性樹脂層316之孔部308的形成與絕緣材料層306之金屬孔310的形成之例子，或藉由雷射等來進行金屬孔310的加工之例子，但此等之步驟係為煩雜，且並不合理。進而，雖可將感光性樹脂層316與絕緣材料層306同時供給至半導體元件302周邊部及電路形成面，但實際上並無具體的方法之例示，於半導體元件周邊不產生間隙地供給此等之樹脂層一事係有困難。又，雖亦有同時進行感光性樹脂層316之孔部308與絕緣材料層306之金屬孔310的形成，但針對具體的方法並無記載。
[先前技術文獻] [專利文獻]
[專利文獻1]日本特開2007-67016號公報
[專利文獻2]日本特開2010-245509號公報
[專利文獻3]日本特開2013-30593號公報
本發明係鑑於上述情事而完成者，其目的為提供一種對於配線基板之載置或半導體裝置之層合為容易，且即使於金屬配線之密度大的情況中半導體裝置之翹曲亦受到抑制的半導體裝置。
又，其目的為提供一種在製造如此之半導體裝置時，能夠容易進行貫穿電極、電極墊部之開口等的加工之半導體裝置之製造方法。
進而，其目的為提供將如此之半導體裝置進行層合之層合型半導體裝置、將其載置於配線基板上並予以封裝的封裝後層合型半導體裝置、及此等之製造方法。
為了解決上述課題，於本發明中係提供一種半導體裝置，其係具有半導體元件、與電連接於該半導體元件之半導體元件上金屬墊及金屬配線，且該金屬配線係電連接於貫穿電極及焊錫凸塊，具有：載置前述半導體元件之第一絕緣層、形成於前述半導體元件上之第二絕緣層、以及形成於該第二絕緣層上之第三絕緣層，前述金屬配線係在前述第二絕緣層的上面經由前述半導體元件上金屬墊而電連接於前述半導體元件，且從前述第二絕緣層的上面貫穿前述第二絕緣層而在前述第二絕緣層的下面電連接於前述貫穿電極。
若為如此之半導體裝置，則藉由於半導體元 件上實施微細的電極形成，並於半導體元件外部形成貫穿電極，而使對於配線基板之載置或半導體裝置之層合為容易，又，藉由於第二絕緣層的兩面形成金屬配線，而成為即使在金屬配線的密度為大之情況中半導體裝置之翹曲亦受到抑制的半導體裝置。
又，此時，較佳為前述第一絕緣層係藉由光硬化性乾膜或光硬化性阻劑塗佈膜所形成者，前述第二絕緣層係藉由前述光硬化性乾膜所形成者，前述第三絕緣層係藉由前述光硬化性乾膜或光硬化性阻劑塗佈膜所形成者。
藉此，成為即使半導體元件之高度為數十μm亦可無空隙等地埋填於半導體元件周邊的半導體裝置。
又，此時，較佳為前述半導體元件的高度為20~100μm，前述第一絕緣層的膜厚為1~20μm，前述第二絕緣層的膜厚為5~100μm，前述第三絕緣層的膜厚為5~100μm，前述半導體裝置的厚度為50~300μm。
藉此，可無空隙等地埋填於半導體元件的周邊，且成為薄型之半導體裝置。
又，此時，較佳為前述光硬化性乾膜係具有由化學增幅型負型阻劑組成物材料所構成的光硬化性樹脂層之光硬化性乾膜，該化學增幅型負型阻劑組成物材料係含有：(A)具有以下述一般式(1)所示之重複單元的重量平均分子量為3,000~500,000之含矽酮骨架之高分子化合物、 (式中，R1~R4係表示可相同或相異之碳數1~8的1價烴基；m為1~100之整數；a、b、c、d為0或正數，且a、b、c、d不同時為0；但，a+b+c+d=1；再者，X係以下述一般式(2)所示之有機基，Y係以下述一般式(3)所示之有機基) (式中，Z係由 中任一者所選出的2價之有機基，n為0或1；R5及R6係各自為碳數1~4之烷基或烷氧基，且可彼此相異或相同；k為0、1、2中之任一者) (式中，V係由 中任一者所選出的2價之有機基，p為0或1；R7及R8係各自為碳數1~4之烷基或烷氧基，且可彼此相異或相同；h為0、1、2中之任一者)(B)由藉由甲醛或甲醛-醇改質而成的胺基縮合物、1分子中平均具有2個以上之羥甲基或烷氧基羥甲基的酚化合物所選出之1種或2種以上之交聯劑、(C)藉由波長190~500nm之光進行分解，而產生酸之光酸產生劑、以及(D)溶劑。
藉此，成為可進一步抑制翹曲的半導體裝置。
又，於本發明中係提供一種將上述半導體裝置倒裝晶片化並複數層合而成的層合型半導體裝置。
若為本發明之半導體裝置，則由於半導體裝置之層合為容易，因此適於如此之層合型半導體裝置。
又，於本發明中係提供一種封裝後層合型半導體裝置，其係將上述之層合型半導體裝置載置於具有電路的基板上，並以絕緣封裝樹脂層加以封裝而成。
若為本發明之半導體裝置，則由於對於半導體裝置的配線基板之載置或半導體裝置之層合為容易，因此適於如此之封裝後層合型半導體裝置。
進而，於本發明中係提供一種半導體裝置之製造方法，其係具有以下步驟：(1)於支撐基板上塗佈暫時性接著劑，於該暫時性接著劑上形成使用阻劑組成物材料作為光硬化性樹脂層之膜厚1~20μm的第一絕緣層之步驟；(2)在對於前述第一絕緣層，藉由隔著遮罩之微影技術進行圖型化而形成成為貫穿電極的通孔圖型之後，進行烘烤，藉此使前述第一絕緣層硬化之步驟；(3)於前述第一絕緣層進行以濺鍍所致之種晶層形成，其後，將前述成為貫穿電極之通孔圖型，藉由鍍敷來填埋，而形成與貫穿電極連接的金屬配線之步驟；(4)使用晶片黏合劑將電極墊露出於上部表面之高度20~100μm的半導體元件晶片黏合於前述硬化後的第一絕緣層上之步驟；(5)準備具有膜厚5~100μm之光硬化性樹脂層為被支撐薄膜與保護薄膜包夾的結構，且該光硬化性樹脂層為由阻劑組成物材料所構成的光硬化性乾膜之步驟；(6)藉由以覆蓋被晶片黏合於前述第一絕緣層上之半 導體元件的方式將前述光硬化性乾膜之光硬化性樹脂層進行疊層，而形成第二絕緣層之步驟；(7)對於前述第二絕緣層，藉由隔著遮罩之微影技術進行圖型化，而同時形成前述電極墊上之開口、以及用以在與前述貫穿電極連接的金屬配線上形成貫穿前述第二絕緣層的金屬配線之開口、以及用以形成前述貫穿電極之開口，之後，進行烘烤，藉此使前述第二絕緣層硬化之步驟；(8)在硬化後，進行以濺鍍所致之種晶層形成，其後，將前述電極墊上之開口、用以形成貫穿前述第二絕緣層的金屬配線之開口、以及用以形成前述貫穿電極之開口，藉由鍍敷來填埋，而形成半導體元件上金屬墊、貫穿前述第二絕緣層之金屬配線、以及貫穿電極，並且將藉由前述鍍敷所形成的前述半導體元件上金屬墊與貫穿前述第二絕緣層的金屬配線藉由以鍍敷所得之金屬配線相連結之步驟；(9)金屬配線形成後，將前述光硬化性乾膜之光硬化性樹脂層進行疊層或者將使用於前述光硬化性乾膜之阻劑組成物材料進行旋轉塗佈，藉此形成第三絕緣層之步驟；(10)在對於前述第三絕緣層，藉由隔著遮罩之微影技術進行圖型化而於前述貫穿電極上部形成開口之後，進行烘烤，藉此使前述第三絕緣層硬化之步驟；(11)硬化後，於前述貫穿電極上部之開口形成焊錫凸塊之步驟。
若為如此之半導體裝置之製造方法，則藉由於半導體元件上實施微細的電極形成，並於半導體元件外部形成貫穿電極，而可容易進行對於配線基板之載置或半導體裝置之層合，又可容易進行貫穿電極、電極墊部之開口等的加工。又，藉由使用光硬化性乾膜，而可成為即使半導體元件之高度為數十μm，亦可無空隙等地埋填於半導體元件周邊的半導體裝置。進而，藉由於第二絕緣層的兩面形成金屬配線，即使在金屬配線的密度為大之情況中亦可抑制半導體裝置之翹曲。
又，此時，較佳為將在前述步驟(5)所準備的光硬化性乾膜設為具有由化學增幅型負型阻劑組成物材料所構成的光硬化性樹脂層之光硬化性乾膜，該化學增幅型負型阻劑組成物材料係含有：(A)具有以下述一般式(1)所示之重複單元的重量平均分子量為3,000~500,000之含矽酮骨架之高分子化合物、 (式中，R1~R4係表示可相同或相異之碳數1~8的1價烴基；m為1~100之整數；a、b、c、d為0或正數，且a、 b、c、d不同時為0；但，a+b+c+d=1；再者，X係以下述一般式(2)所示之有機基，Y係以下述一般式(3)所示之有機基) (式中，Z係由 中任一者所選出的2價之有機基，n為0或1；R5及R6係各自為碳數1~4之烷基或烷氧基，且可彼此相異或相同；k為0、1、2中之任一者) (式中，V係由 中任一者所選出的2價之有機基，p為0或1；R7及R8係各自為碳數1~4之烷基或烷氧基，且可彼此相異或相同；h為0、1、2中之任一者)(B)由藉由甲醛或甲醛-醇改質而成的胺基縮合物、1分子中平均具有2個以上之羥甲基或烷氧基羥甲基的酚化合物所選出之1種或2種以上之交聯劑、(C)藉由波長190~500nm之光進行分解，而產生酸之光酸產生劑、以及(D)溶劑。
藉此，由於可減輕在個片化後所擔憂之半導體裝置的翹曲，因此使個片化後的半導體裝置之層合或對於配線基板之載置變得更容易。
又，較佳為於前述步驟(6)中，包含對前述第二絕緣層進行機械性加壓的步驟。
藉此，可使半導體元件上之第二絕緣層的厚度減薄，或予以均勻化，又可使第二絕緣層平坦化。
又，此時，藉由於前述步驟(11)中，具有：於前述貫穿電極上部之開口藉由鍍敷形成貫穿電極上金屬墊之步驟、以及 於前述貫穿電極上金屬墊上形成焊錫球，製成焊錫凸塊之步驟的方法，而可於貫穿電極上部之開口形成焊錫凸塊。
又，若為於前述步驟(8)之以鍍敷所致之前述 貫穿電極的形成中，包含進行以SnAg所致之鍍敷之步驟，並且具有：於前述步驟(10)中，以於前述貫穿電極上部形成開口的方式進行圖型化，藉此使前述鍍敷後的SnAg露出之步驟、以及於前述步驟(11)中，藉由將前述鍍敷後的SnAg進行熔融而於前述貫穿電極上部之開口處使電極隆起而形成焊錫凸塊之步驟的方法，則可進一步容易且合理地於前述貫穿電極上部之開口形成焊錫凸塊。
又，藉由在前述步驟(11)之後，進行：將在前述步驟(1)與第一絕緣層暫時接著的支撐基板去除之步驟、以及在將前述基板去除後，進行切割，藉此予以個片化之步驟，而可製造經個片化的半導體裝置。
又，可製造將以上述之製造方法來藉由切割而個片化的複數個半導體裝置，包夾絕緣樹脂層，並藉由前述焊錫凸塊電接合而進行層合的層合型半導體裝置。
進而，藉由具有：將以上述之製造方法所製造的層合型半導體裝置載置於具有電路的基板之步驟、以及將載置於前述基板之層合型半導體裝置以絕緣封裝樹脂層進行封裝之步驟的方法而可製造封裝後層合型半導體裝置。
依據本發明之半導體裝置及其製造方法，可賦予如以下所示般的效果。
亦即，由於在將載置於形成在支撐基板上的第一絕緣層上之半導體元件周邊藉由將阻劑組成物材料使用於光硬化性樹脂層的光硬化性乾膜進行填埋時，光硬化性樹脂層為膜厚5~100μm，因此即使於半導體元件的高度為數十μm之情況中也能夠於半導體元件周邊不產生空隙等地將光硬化性乾膜進行填埋，且更加容易。
具有藉由在將載置於形成在支撐基板上的第一絕緣層上之半導體元件周邊藉由將阻劑組成物材料使用於光硬化性樹脂層的光硬化性乾膜進行疊層之後，對半導體元件上之光硬化性樹脂層(第二絕緣層)進行機械性加壓，而能夠進行膜厚之調整、薄膜化的優點，且機械性加壓係具有能夠使半導體元件外周之經疊層的光硬化性樹脂層的膜厚均勻化、平坦化的優點。
於經疊層的光硬化性乾膜(第二絕緣層)中，可將位於半導體元件上之電極墊上的開口、用以形成貫穿第二絕緣層之金屬配線的開口、以及成為貫穿電極的開口之形成藉由隔著遮罩的微影技術所致之圖型化來整批、同時地進行。
在將具有半導體元件之結構體進行立體層合，或載置於配線基板上時成為電極之貫穿電極孔 (TMV=Through Metal Via)，係可藉由使用周知廣泛使用的隔著遮罩之微影技術而容易地進行。
將半導體元件上之電極墊上的開口、用以形成貫穿第二絕緣層之金屬配線的開口、以及貫穿電極形成用的開口，藉由鍍敷進行填埋，形成半導體元件上金屬墊、貫穿第二絕緣層之金屬配線、以及貫穿電極，將半導體元件上金屬墊與貫穿第二絕緣層之金屬配線藉由鍍敷往經金屬配線的配線上疊層光硬化性乾膜，藉此再度進行層合，並進行於配置在半導體元件之外部的貫穿電極(TMV)上部形成開口的圖型化，於形成在貫穿電極上部之開口的貫穿電極上金屬墊之上形成焊錫球，藉此而在將支撐基板移除之後進行個片化，此方法係為可容易地製造半導體裝置的方法。
作為更容易且合理地製造半導體裝置的方法係提供以下方法：於貫穿電極(TMV)之鍍敷埋填中，包含進行以SnAg所致之鍍敷的步驟，藉由將光硬化性乾膜進行疊層而再度進行層合，在進行於貫穿電極上部形成開口的圖型化之後，經過使SnAg之鍍敷露出的步驟、與圖型化後，藉由烘烤使薄膜硬化的步驟之後，將藉由鍍敷所填充的SnAg熔融，藉此使其朝向貫穿電極開口部隆起。
藉由暫時性接著劑來進行形成在支撐基板上的第一絕緣層與支撐基板之接著，接著，在容易地去除支撐基板的步驟，與將支撐基板移除後藉由切割而進行個片化者係對於製造經個片化的半導體裝置而言為容易且合 理。
以上述製造方法所得之經個片化的半導體裝置，上部係焊錫球或作為隆起後的SnAg之焊錫凸塊會突出，且下部係脫離基板，藉此可使貫穿電極容易露出，因此，使用突出的焊錫凸塊與露出的電極，可將複數個經個片化的半導體裝置容易地進行電接合，而可進行層合，故非常合理。
又，於以往之僅在半導體元件上金屬墊側施以金屬配線的單面配線圖型中，若配線密度過大，則有半導體裝置本身的翹曲變大之傾向，但本發明之半導體裝置係藉由於第二絕緣層的兩面形成金屬配線，即使配線密度變大亦可抑制半導體裝置本身的翹曲。又，今後將來，由於為了對應於半導體裝置之訊號數量的增加亦會要求多層配線，因此將半導體裝置本身的翹曲極度縮小一事係為重要，但於第二絕緣層的兩面施以金屬配線之本發明之半導體裝置係由於能夠將翹曲極度縮小，因此亦適於多層配線。
又，於將本發明之化學增幅型負型阻劑組成物材料使用於光硬化性樹脂層的情況中，由於能夠減輕在個片化時所顧慮之半導體裝置的翹曲，因此適於層合或對於配線基板之載置。
如以上所述般，若為本發明之半導體裝置，則藉由於半導體元件上實施微細的電極形成，並於半導體元件外部施以貫穿電極，而使對於配線基板之載置或半導 體裝置之層合為容易，進而，成為即使半導體元件的高度為數十μm亦可於半導體元件周邊無空隙等地進行填埋，即使在金屬配線的密度為大之情況中半導體裝置之翹曲亦受到抑制的半導體裝置。
又，若為本發明之半導體裝置之製造方法，則藉由於半導體元件上實施微細的電極形成，並於半導體元件外部施以貫穿電極，而可容易進行對於配線基板之載置或半導體裝置之層合，又可容易進行貫穿電極、電極墊部之開口等的加工。
進而，以如此方式所得到的本發明之半導體裝置係由於對於配線基板之載置或半導體裝置之層合為容易，因此可製成將半導體裝置進行層合之層合型半導體裝置或將其載置於配線基板並加以封裝之封裝後層合型半導體裝置。
1‧‧‧半導體裝置
2‧‧‧半導體元件
3‧‧‧半導體元件上金屬墊
4‧‧‧金屬配線
4a‧‧‧上面金屬配線
4b‧‧‧下面金屬配線
4c‧‧‧貫穿金屬配線
5‧‧‧貫穿電極
6‧‧‧焊錫凸塊
7‧‧‧第一絕緣層
8‧‧‧第二絕緣層
9‧‧‧第三絕緣層
10‧‧‧晶片黏合劑
11‧‧‧層合型半導體裝置
12‧‧‧絕緣樹脂層
13‧‧‧封裝後層合型半導體裝置
14‧‧‧配線基板
15‧‧‧絕緣封裝樹脂層
16‧‧‧支撐基板
17‧‧‧暫時性接著劑
18‧‧‧金屬鍍敷
19‧‧‧貫穿電極上金屬墊
20‧‧‧焊錫球
21‧‧‧SnAg鍍敷
22‧‧‧使SnAg隆起的電極
23、24‧‧‧經個片化之半導體裝置
A‧‧‧成為貫穿電極之通孔圖型
B‧‧‧電極墊上之開口
C‧‧‧用以形成貫穿金屬配線之開口
D‧‧‧用以形成貫穿電極之開口
E‧‧‧貫穿電極上部之開口
[第1圖]係顯示本發明之半導體裝置的一例子之概略剖面圖。
[第2圖]係顯示本發明之層合型半導體裝置的一例子之概略剖面圖。
[第3圖]係顯示本發明之封裝後層合型半導體裝置的一例子之概略剖面圖。
[第4圖]係用以說明本發明之半導體裝置之製造方法的一例子之步驟(1)之概略剖面圖。
[第5圖]係用以說明本發明之半導體裝置之製造方法的一例子之步驟(2)之概略剖面圖。
[第6圖]係用以說明本發明之半導體裝置之製造方法的一例子之步驟(3)之概略剖面圖。
[第7圖]係用以說明本發明之半導體裝置之製造方法的一例子之步驟(4)之概略剖面圖。
[第8圖]係用以說明本發明之半導體裝置之製造方法的一例子之步驟(6)之概略剖面圖。
[第9圖]係用以說明本發明之半導體裝置之製造方法的一例子之步驟(7)之概略剖面圖。
[第10圖]係用以說明本發明之半導體裝置之製造方法的一例子之步驟(8)之概略剖面圖。
[第11圖]係用以說明本發明之半導體裝置之製造方法的一例子之步驟(8)之概略剖面圖。
[第12圖]係用以說明本發明之半導體裝置之製造方法的一例子之步驟(9)之概略剖面圖。
[第13圖]係用以說明本發明之半導體裝置之製造方法的一例子之步驟(10)之概略剖面圖。
[第14圖]係用以說明本發明之半導體裝置之製造方法的一例子之步驟(11)之概略剖面圖。
[第15圖]係用以說明本發明之半導體裝置之製造方法的另外一例之步驟(8)之概略剖面圖。
[第16圖]係用以說明本發明之半導體裝置之製造方法的另外一例之步驟(11)之概略剖面圖。
[第17圖]係顯示於本發明之半導體裝置之製造方法中經個片化之半導體裝置的一例子之概略剖面圖。
[第18圖]係顯示於本發明之半導體裝置之製造方法中經個片化之半導體裝置的另外一例之概略剖面圖。
[第19圖]係用以說明本發明之層合型半導體裝置之製造方法的一例子之概略剖面圖。
[第20圖]係用以說明本發明之層合型半導體裝置之製造方法的另外一例之概略剖面圖。
[第21圖]係顯示載置於配線基板上的本發明之層合型半導體裝置的一例子之概略剖面圖。
[第22圖]係顯示載置於配線基板上的本發明之層合型半導體裝置的另外一例之概略剖面圖。
[第23圖]係用以說明本發明之封裝後層合型半導體裝置之製造方法的一例子之概略剖面圖。
[第24圖]係用以說明本發明之封裝後層合型半導體裝置之製造方法的另外一例之概略剖面圖。
[第25圖]係顯示以往之半導體裝置之製造方法之說明圖。
[第26圖]係顯示以往之半導體裝置之製造方法之說明圖。
[第27圖]係顯示以往之半導體裝置之製造方法之說明圖。
[第28圖]係顯示以往之半導體裝置之製造方法之說明圖。
如上述般地，於半導體裝置中，對於更加小型化、薄型化及高密度化的要求急速高漲，而要求開發對於配線基板之載置或半導體裝置之層合為容易的半導體裝置及其製造方法。又，今後將來，由於為了對應於半導體裝置之訊號數量的增加亦會要求多層配線，因此要求開發即使於多層配線等金屬配線的密度為大的情況中亦能夠抑制半導體裝置本身之翹曲的半導體裝置及其製造方法。
本發明者們係為了達成上述目的屢經努力探討的結果，發現藉由進行下述所示之步驟來克服課題，而可容易地製造半導體裝置及層合型半導體裝置，因而完成本發明。
首先，於塗佈有暫時性接著劑的支撐基板上，使用阻劑組成物材料來形成第一絕緣層，對於此第一絕緣層進行圖型化，而形成成為貫穿電極的通孔圖型。在以烘烤所致之硬化後，將成為貫穿電極之通孔圖型藉由鍍敷進行埋填，形成與貫穿電極連接的金屬配線，將半導體元件晶片黏合於第一絕緣層上。接著，將經晶片黏合的半導體元件周邊，藉由將阻劑組成物材料使用於光硬化性樹脂層的光硬化性乾膜進行疊層，藉此可於半導體元件周邊不產生間隙等地將薄膜進行埋填(第二絕緣層之形成)。得知：由於是對於此第二絕緣層，藉由隔著遮罩之微影技術進行圖型化，藉此可同時形成電極墊上之開口、用以形成 貫穿第二絕緣層的金屬配線之開口、以及用以形成貫穿電極之開口，因此可容易地進行加工，因而完成本發明。
進而，在藉由烘烤使第二絕緣層硬化後，將電極墊上之開口、用以形成貫穿第二絕緣層的金屬配線之開口、以及用以形成貫穿電極之開口，藉由鍍敷來填埋，而形成半導體元件上金屬墊、貫穿第二絕緣層之金屬配線、以及貫穿電極，並且將藉由鍍敷所形成的半導體元件上金屬墊與貫穿第二絕緣層的金屬配線藉由以鍍敷所得之金屬配線相連結。其後，於其上形成第三絕緣層，對於第三絕緣層進行圖型化而於貫穿電極上部形成開口，使其硬化後，於此開口形成焊錫凸塊。進而，將以暫時性接著劑所接著的支撐基板去除，並藉由切割而進行個片化，此係能夠非常合理地形成半導體裝置的方法，而將本發明之目的予以具體呈現。
又，發現若為以上述製造方法所製造的半導體裝置，則藉由於第二絕緣層的兩面形成金屬配線，即使配線密度變大亦可抑制半導體裝置本身的翹曲。
進而，得知以下見解：以上述製造方法所製造之半導體裝置，上部係焊錫凸塊會突出，且下部係藉由去除支撐基板而可使貫穿電極容易露出，因此，使用突出的焊錫凸塊與露出的電極，可將複數個半導體裝置容易地進行電接合，而可進行層合，又，得知以下見解：可將經層合的半導體裝置容易地載置於配線基板，因而完成本發明。
亦即，本發明係一種半導體裝置，其係具有半導體元件、與電連接於該半導體元件之半導體元件上金屬墊及金屬配線，且該金屬配線係電連接於貫穿電極及焊錫凸塊，具有：載置有前述半導體元件之第一絕緣層、形成於前述半導體元件上之第二絕緣層、以及形成於該第二絕緣層上之第三絕緣層，前述金屬配線係在前述第二絕緣層的上面經由前述半導體元件上金屬墊而電連接於前述半導體元件，且從前述第二絕緣層的上面貫穿前述第二絕緣層而在前述第二絕緣層的下面電連接於前述貫穿電極者。
以下，雖一邊參照附圖一邊針對本發明進行詳細地說明，但本發明並不限定於此等。
本發明之半導體裝置1，係如第1圖所示般，具有半導體元件2、與電連接於半導體元件2的半導體元件上金屬墊3及金屬配線4，且金屬配線4電連接於貫穿電極5及焊錫凸塊6的半導體裝置，且具有：載置有半導體元件2的第一絕緣層7、形成於半導體元件2上的第二絕緣層8、以及形成於第二絕緣層8上的第三絕緣層9，金屬配線4係在第二絕緣層8的上面經由半導體元件上金屬墊3而電連接於半導體元件2，且從第二絕緣層8的上面貫穿第二絕緣層8而在第二絕緣層8的下面電連接於貫穿電極5之半導體裝置。
另外，金屬配線4係由在第二絕緣層8的上 面與半導體元件上金屬墊3連接之金屬配線(上面金屬配線)4a、在第二絕緣層8的下面與貫穿電極5連接之金屬配線(下面金屬配線)4b、以及貫穿第二絕緣層8，並將上面金屬配線4a與下面金屬配線4b進行連接之金屬配線(貫穿金屬配線)4c所構成。
又，於第1圖之半導體裝置1中，半導體元件2係藉由晶片黏合劑10而晶片黏合於第一絕緣層7。
若為如此之半導體裝置，則藉由於半導體元件上實施微細的電極形成，並於半導體元件外部施以貫穿電極，而容易進行對於配線基板之載置或半導體裝置之層合，又，藉由於第二絕緣層的兩面形成金屬配線，而成為即使在金屬配線的密度為大之情況中半導體裝置之翹曲亦受到抑制的半導體裝置。
又，此時，若為藉由光硬化性乾膜或者光硬化性阻劑塗佈膜而形成第一絕緣層7者，藉由光硬化性乾膜而形成第二絕緣層8者，藉由光硬化性乾膜或者光硬化性阻劑塗佈膜而形成第三絕緣層9者，則成為即使半導體元件2之高度為數十μm亦於半導體元件周邊無空隙等地進行填埋的半導體裝置，故為佳。
又，此時，若為半導體元件2的高度為20~100μm，第一絕緣層7的膜厚為1~20μm，第二絕緣層8的膜厚為5~100μm，第三絕緣層9的膜厚為5~100μm，半導體裝置1的厚度為50~300μm，則成為於半導體元件 周邊無空隙等地進行填埋，且薄型的半導體裝置，故為佳。
又此時，使用於上述之第一絕緣層7、第二絕緣層8、及第三絕緣層9之形成的光硬化性乾膜，就翹曲之抑制、殘留應力之減低、可靠性或加工特性之提昇等的觀點而言，較佳為具有由含有以下之(A)~(D)成分而成的化學增幅型負型阻劑組成物材料所構成之光硬化性樹脂層的光硬化性乾膜。
另外，當然亦可使用其他的感光性樹脂。
(A)成分係具有以下述一般式(1)所示之重複單元的重量平均分子量為3,000~500,000之含矽酮骨架之高分子化合物。
(式中，R1~R4係表示可相同或相異之碳數1~8的1價烴基；m為1~100之整數；a、b、c、d為0或正數，且a、b、c、d不同時為0；但，a+b+c+d=1；再者，X係以下述一般式(2)所示之有機基，Y係以下述一般式(3)所示之有機基) (式中，Z係由 中任一者所選出的2價之有機基，n為0或1；R5及R6係各自為碳數1~4之烷基或烷氧基，且可彼此相異或相同；k為0、1、2中之任一者) (式中，V係由 中任一者所選出的2價之有機基，p為0或1；R7及R8係各自為碳數1~4之烷基或烷氧基，且可彼此相異或相同； h為0、1、2中之任一者)。
(B)成分係由藉由甲醛或甲醛-醇改質而成的胺基縮合物、1分子中平均具有2個以上之羥甲基或烷氧基羥甲基的酚化合物所選出之1種或2種以上之交聯劑。
(C)成分係藉由波長190~500nm之光進行分解，而產生酸之光酸產生劑。
(D)成分為溶劑。
作為(B)成分之交聯劑雖可使用周知者，但可使用由藉由甲醛或甲醛-醇改質而成的胺基縮合物及1分子中平均具有2個以上之羥甲基或烷氧基羥甲基的酚化合物所選出之1種或2種以上。
作為如此之藉由甲醛或甲醛-醇改質而成的胺基縮合物係可列舉例如：藉由甲醛或甲醛-醇改質而成的三聚氰胺縮合物，或者藉由甲醛或甲醛-醇改質而成的脲縮合物。
另外，此等改質三聚氰胺縮合物及改質脲縮合物係可1種或將2種以上進行混合而使用。
又，作為1分子中平均具有2個以上之羥甲基或烷氧基羥甲基的酚化合物係可列舉例如：(2-羥基-5-甲基)-1,3-苯二甲醇、2,2’,6,6’-四甲氧基甲基雙酚A等。
另外，此等酚化合物係可1種或將2種以上進行混合而使用。
作為(C)成分之酸產生劑係可使用藉由波長190~500nm之光照射產生酸，而使其成為硬化觸媒者。
作為如此之光酸產生劑係可列舉：鎓鹽、重氮甲烷衍生物、乙二醛二肟(glyoxime)衍生物、β-酮碸(ketosulphone)衍生物、二碸衍生物、硝苄基磺酸酯衍生物、磺酸酯衍生物、醯亞胺-基-磺酸酯衍生物、肟磺酸酯衍生物、亞胺基磺酸酯衍生物、三嗪衍生物等。
作為(D)成分之溶劑係可使用能夠溶解(A)含有矽酮骨架之高分子化合物、(B)交聯劑、及(C)光酸產生劑者。
作為如此之溶劑係可列舉例如：環己酮、環戊酮、甲基-2-n-戊基酮等之酮類；3-甲氧基丁醇、3-甲基-3-甲氧基丁醇、1-甲氧基-2-丙醇、1-乙氧基-2-丙醇等之醇類；丙二醇單甲基醚、乙二醇單甲基醚、丙二醇單乙基醚、乙二醇單乙基醚、丙二醇二甲基醚、二乙二醇二甲基醚等之醚類；丙二醇單甲基醚乙酸酯、丙二醇單乙基醚乙酸酯、乳酸乙酯、丙酮酸乙酯、乙酸丁酯、3-甲氧基丙酸甲酯、3-乙氧基丙酸乙酯、乙酸tert-丁酯、丙酸tert-丁酯、丙二醇-單-tert-丁基醚乙酸酯、γ-丁內酯等之酯類等。
又，第一絕緣層7與第三絕緣層9係可為藉由旋轉塗佈等塗佈有含有上述之(A)~(D)成分而成之化學增幅型負型阻劑組成物材料的光硬化性阻劑塗佈膜，當然，亦可為藉由旋轉塗佈等塗佈有其他之感光性樹脂的光硬化性阻劑塗佈膜。
進而，於本發明中，係提供將上述之半導體裝置倒裝晶片化並複數層合而成的層合型半導體裝置。
本發明之層合型半導體裝置11，如第2圖所示般，係將上述之半導體裝置1倒裝晶片化並藉由貫穿電極5與焊錫凸塊6電接合並複數層合而成者，於各半導體裝置間亦可封入有絕緣樹脂層12。
又，於本發明中係提供一種封裝後層合型半導體裝置，其係將上述之層合型半導體裝置載置於具有電路的基板上，並以絕緣封裝樹脂層加以封裝而成。
本發明之封裝後層合型半導體裝置13，係如第3圖所示般，將上述之層合型半導體裝置11經由焊錫凸塊6而載置於具有電路之基板(配線基板14)上，並以絕緣封裝樹脂層15加以封裝而成者。
如上述般之半導體裝置係可藉由以下所示之本發明的半導體裝置之製造方法進行製造。本發明之半導體裝置之製造方法係具有以下步驟：(1)於支撐基板上塗佈暫時性接著劑，於該暫時性接著劑上形成使用阻劑組成物材料作為光硬化性樹脂層之膜厚1~20μm的第一絕緣層之步驟；(2)在對於前述第一絕緣層，藉由隔著遮罩之微影技術進行圖型化而形成成為貫穿電極的通孔圖型之後，進行烘烤，藉此使前述第一絕緣層硬化之步驟；(3)於前述第一絕緣層進行以濺鍍所致之種晶層形成，其後，將前述成為貫穿電極之通孔圖型，藉由鍍敷來填埋，而形成與貫穿電極連接的金屬配線之步驟；(4)使用晶片黏合劑將電極墊露出於上部表面之高度 20~100μm的半導體元件晶片黏合於前述硬化後的第一絕緣層上之步驟；(5)準備具有膜厚5~100μm之光硬化性樹脂層為被支撐薄膜與保護薄膜包夾的結構，且該光硬化性樹脂層為由阻劑組成物材料所構成的光硬化性乾膜之步驟；(6)藉由以覆蓋被晶片黏合於前述第一絕緣層上之半導體元件的方式將前述光硬化性乾膜之光硬化性樹脂層進行疊層，而形成第二絕緣層之步驟；(7)對於前述第二絕緣層，藉由隔著遮罩之微影技術進行圖型化，而同時形成前述電極墊上之開口、以及用以在與前述貫穿電極連接的金屬配線上形成貫穿前述第二絕緣層的金屬配線之開口、以及用以形成前述貫穿電極之開口，之後，進行烘烤，藉此使前述第二絕緣層硬化之步驟；(8)在硬化後，進行以濺鍍所致之種晶層形成，其後，將前述電極墊上之開口、用以形成貫穿前述第二絕緣層的金屬配線之開口、以及用以形成前述貫穿電極之開口，藉由鍍敷來填埋，而形成半導體元件上金屬墊、貫穿前述第二絕緣層之金屬配線、以及貫穿電極，並且將藉由前述鍍敷所形成的前述半導體元件上金屬墊與貫穿前述第二絕緣層的金屬配線藉由以鍍敷所得之金屬配線相連結之步驟；(9)金屬配線形成後，將前述光硬化性乾膜之光硬化性樹脂層進行疊層或者將使用於前述光硬化性乾膜之阻劑 組成物材料進行旋轉塗佈，藉此形成第三絕緣層之步驟；(10)在對於前述第三絕緣層，藉由隔著遮罩之微影技術進行圖型化而於前述貫穿電極上部形成開口之後，進行烘烤，藉此使前述第三絕緣層硬化之步驟；(11)硬化後，於前述貫穿電極上部之開口形成焊錫凸塊之步驟。
以下，針對各步驟進行詳細地說明。
首先，於步驟(1)中，如第4圖所示般，於支撐基板16上塗佈暫時性接著劑17，於暫時性接著劑17上形成使用阻劑組成物材料作為光硬化性樹脂層之膜厚1~20μm的第一絕緣層7。
作為支撐基板16雖無特別限定，但可使用例如矽晶圓或玻璃基板等。
又，作為暫時性接著劑17雖無特別限定，但較佳為例如熱塑性樹脂。
可列舉：烯烴系熱塑性彈性體、聚丁二烯系熱塑性彈性體、苯乙烯系熱塑性彈性體、苯乙烯/丁二烯系熱塑性彈性體、苯乙烯/聚烯烴系熱塑性彈性體等，尤其以耐熱性優異之氫化聚苯乙烯系彈性體較為理想。具體而言係可列舉：Tuftec(Asahi Kasei Chemicals製)、ESPOLEX SB系列(住友化學製)、RABALON(三菱化學製)、Septon(KURARAY製)、DYNARON(JSR製)等。又，可列舉以ZEONEX(日本ZEON製)為代表之環烯烴聚合物及以TOPAS(日本Polyplastics製)為代表之環狀烯烴共聚物。 又，亦可使用矽酮系熱塑性樹脂。較佳可使用例如二甲基矽酮、苯基矽酮、烷基改質矽酮、矽酮樹脂。具體而言係可列舉KF96、KF54、X-40-9800(皆為信越化學製)。
又，第一絕緣層7，係如上述般地，可藉由使用具有由含有例如(A)~(D)成分所成之化學增幅型負型阻劑組成物材料所構成的光硬化性樹脂層的光硬化性乾膜來進行疊層，或者將此阻劑組成物材料藉由旋轉塗佈等進行塗佈而形成。當然，亦可使用其他的感光性樹脂。
第一絕緣層的膜厚係1~20μm，較佳為5~10μm，若為如此之膜厚則可將所製造之半導體裝置予以薄型化，故為佳。
接著，於步驟(2)中，在對於第一絕緣層7，藉由隔著遮罩之微影技術進行圖型化，如第5圖所示般地形成成為貫穿電極的通孔圖型A之後，進行烘烤，藉此使第一絕緣層7硬化。
於此圖型化中，係在形成第一絕緣層7之後，進行曝光、曝光後加熱處理(曝光後烘烤；PEB)，予以顯像，進而因應需要而進行後硬化來形成圖型。亦即，可使用周知之微影技術來進行圖型之形成。
在此，亦可在為了有效率地進行第一絕緣層之光硬化反應或提昇第一絕緣層7與支撐基板16之密著性，或者提昇密著後之第一絕緣層7的平坦性之目的下，因應需要而進行預備加熱(預烘烤)。預烘烤例如可以40~140℃進行1分鐘~1小時左右。
接著，隔著光罩以波長190~500nm之光進行曝光，並使其硬化。光罩亦可為例如挖鑿出所期望之圖型者。另外，光罩的材質係較佳為將波長190~500nm之光遮蔽者，雖較佳可使用例如鉻等，但並不限定於此。
作為波長190~500nm之光係藉由例如敏輻射線產生裝置所產生之各種波長的光，可列舉例如：g線、i線等之紫外線光、遠紫外線光(248nm、193nm)等。且，波長係較佳為248~436nm。曝光量係較佳為例如10~3,000mJ/cm2。藉由如此般地進行曝光，將曝光部分進行交聯而形成不溶於顯像液的圖型。
進而，為了提高顯像感度而進行PEB。PEB，例如可設為以40~140℃進行0.5~10分鐘。
其後，以顯像液進行顯像。作為較佳之顯像液係可列舉IPA或PGMEA之有機溶劑。又，較佳之作為鹼水溶液的顯像液係為例如2.38%之氫氧化四甲基銨(TMAH)水溶液。於本發明之半導體裝置之製造方法中，作為顯像液係較佳可使用有機溶劑。
顯像係可藉由通常之方法，例如將形成有圖型之基板浸漬於顯像液中等而進行。其後，因應需要進行洗淨、清洗、乾燥等，而得到具有期望之圖型的光硬化性樹脂層之被膜(第一絕緣層)。
接著，如此般地將形成有圖型之第一絕緣層使用烘箱或加熱板，以較佳為溫度100~250℃，更佳為150~220℃，再更佳為170~190℃進行烘烤，使其硬化(後 硬化)。只要後硬化溫度為100~250℃，則可提昇第一絕緣層之交聯密度，並將殘留的揮發性成分去除，就對於支撐基板之密著力、耐熱性或強度，進而電特性之觀點而言為佳。且，後硬化時間係可設為10分鐘~10小時。
接著，於步驟(3)中，於第一絕緣層7進行以濺鍍所致之種晶層形成，其後，將成為貫穿電極之通孔圖型A，藉由鍍敷來填埋，而如第6圖所示般地形成與貫穿電極連接的金屬配線(下面金屬配線)4b。
在進行鍍敷時，例如，於第一絕緣層7上藉由濺鍍而形成種晶層之後，進行鍍敷阻劑之圖型化，其後，進行電鍍等，於成為貫穿電極之通孔圖型A進行金屬鍍敷之填埋與下面金屬配線4b之形成。在形成金屬配線之後，藉由蝕刻去除種晶層，使第一絕緣層7露出。
另外，下面金屬配線4b雖只要如同成為所期望之配線寬度般地進行適當調整即可，但尤其以成為0.1~10μm之厚度的方式形成於第一絕緣層上為佳。
接著，於步驟(4)中，如第7圖所示般，使用晶片黏合劑10將電極墊露出於上部表面之高度20~100μm的半導體元件2晶片黏合於硬化後的第一絕緣層7上。
另外，晶片黏合劑10係可為周知之接著劑。
又，只要半導體元件2的高度為20~100μm，則可將所製造之半導體裝置進行薄型化，故為佳。
接著，於步驟(5)中，準備具有膜厚5~100μm之光硬化性樹脂層為被支撐薄膜與保護薄膜包夾的結構， 且該光硬化性樹脂層為由阻劑組成物材料所構成的光硬化性乾膜。
以下，針對於本發明所使用之光硬化性乾膜與其製造方法進行詳細地說明。
於本發明之半導體裝置之製造方法中，於第二絕緣層之形成所使用的光硬化性乾膜，係具有膜厚5~100μm之光硬化性樹脂層為被支撐薄膜與保護薄膜包夾的結構，且光硬化性樹脂層為由阻劑組成物材料所構成者。
於本發明之半導體裝置之製造方法中，於第二絕緣層之形成所使用的光硬化性乾膜之光硬化性樹脂層的膜厚為5~100μm，若為如此之膜厚則可將所製造之半導體裝置進行薄型化，故為佳。
另外，於在第一絕緣層及第三絕緣層之形成使用光硬化性乾膜的情況中，只要準備使光硬化性樹脂層之膜厚成為任意的厚度者來進行使用即可。
於本發明所使用之光硬化性乾膜中，係藉由將感光性材料之組成物的各成分進行攪拌混合，其後，藉由過濾器等進行過濾，而可調製用來形成光硬化性樹脂層之阻劑組成物材料。
在此，作為阻劑組成物材料係以含有上述之(A)~(D)成分而成之化學增幅型負型阻劑組成物材料較為理想。
另外，當然亦可使用其他的感光性樹脂。
於本發明所使用之光硬化性乾膜中所使用的支撐薄膜係可為單一，亦可為將複數之聚合物薄膜進行層 合而成的多層薄膜。另外，乾膜係被支撐薄膜及保護薄膜所包夾之薄膜。
作為支撐薄膜的材質係可列舉：聚乙烯、聚丙烯、聚碳酸酯、聚對苯二甲酸乙二酯等之合成樹脂薄膜等，較佳為具有適度之可撓性、機械性強度及耐熱性之聚對苯二甲酸乙二酯。又，針對此等之薄膜亦可為進行了如電暈處理或塗佈有剝離劑般之各種處理者。
此等係可使用市售品，可列舉例如：Cerapeel WZ(RX)、Cerapeel BX8(R)(以上，Toray Films加工(股)製)、E7302、E7304(以上，東洋紡績(股)製)、PUREX G31、PUREX G71T1(以上，Teijin DuPont Films(股)製)、PET38×1-A3、PET38×1-V8、PET38×1-X08(以上，NIPPA(股)製)等。
於本發明所使用之光硬化性乾膜中所使用的保護薄膜雖可使用與上述之支撐薄膜相同者，但較佳為具有適度的可撓性之聚對苯二甲酸乙二酯及聚乙烯。此等係可使用市售品，作為聚對苯二甲酸乙二酯係已例示者，作為聚乙烯係可列舉例如GF-8(TAMAPOLY(股)製)、PE薄膜0型(NIPPA(股)製)。
上述之支撐薄膜及保護薄膜的厚度，就光硬化性乾膜製造之安定性及對於捲芯之捲翹，所謂的防止捲曲之觀點而言，任一者皆較佳為5~100μm。
接著，針對於本發明所使用之光硬化性乾膜之製造方法進行說明。上述光硬化性乾膜之製造裝置係可 使用一般用以製造黏著劑製品的薄膜塗佈機。作為上述薄膜塗佈機係可列舉例如：點塗佈機、反轉逗點塗佈機(Comma Reverse Coater)、多層塗佈機(Multi Coater)、模具塗佈機、唇口塗佈機、唇式反轉塗佈機(Lip reverse Coater)、直接槽輥塗佈機(direct gravure coater)、補償槽輥塗佈機(offset gravure coater)、三輥式底層反轉塗佈機、四輥式底層反轉塗佈機等。
將支撐薄膜從薄膜塗佈機之捲出軸放出，通過薄膜塗佈機之塗佈頭時，於支撐薄膜上以特定的厚度塗佈阻劑組成物材料來形成光硬化性樹脂層，之後，以特定的溫度與特定的時間通過熱風循環烘箱，將在支撐薄膜上乾燥後的光硬化性樹脂層與從薄膜塗佈機之其他的捲出軸放出之保護薄膜一起以特定的壓力通過疊層輥來與支撐薄膜上之光硬化性樹脂層貼合後，捲取於薄膜塗佈機之捲取軸，藉此而製造。於此情況中，作為熱風循環烘箱之溫度係較佳為25~150℃，作為通過時間係較佳為1~100分鐘，作為疊層輥之壓力係較佳為0.01~5MPa。
可利用上述般的方法製作光硬化性乾膜，藉由使用如此之光硬化性乾膜，將載置於支撐基板上之第一絕緣層上的半導體元件進行填埋的特性優異，又可緩和在形成半導體裝置後將支撐基板去除時，或進行個片化時所產生的應力，因此，作為目的之半導體裝置並不會翹曲，而適於將半導體裝置進行層合，或載置於實施了配線之基板。
接著，於步驟(6)中，將保護薄膜從以上述方式準備好的光硬化性乾膜剝離，如第8圖(a)所示般，以覆蓋晶片黏合於第一絕緣層7上之半導體元件2的方式來將光硬化性乾膜之光硬化性樹脂層進行疊層，藉此而形成第二絕緣層8。
作為貼附光硬化性乾膜的裝置係較佳為真空疊層機。將光硬化性乾膜安裝於裝置上，在特定真空度之真空腔內，使用特定壓力之貼附輥，在特定之溫度的工作台上，使光硬化性乾膜之保護膜剝離而露出後的光硬化性樹脂層密著於基板。另外，作為上述溫度係較佳為60~120℃，作為上述壓力係較佳為0~5.0MPa，作為上述真空度係較佳為50~500Pa。藉由進行真空疊層，而不會於半導體元件周邊發生空隙，故為佳。
又，此時，如第8圖(b)所示般，在於半導體元件2上將光硬化性乾膜進行疊層而形成第二絕緣層8時，有時半導體元件2上之第二絕緣層8的膜厚會變厚，或隨著從半導體元件2往周邊偏離而使膜厚漸漸變薄。可較佳地使用藉由機械性地加壓而使此膜厚的變化平坦化，如第8圖(a)所示般，使半導體元件上之膜厚減薄的方法。
接著，於步驟(7)中，如第9圖所示般，對於第二絕緣層8，藉由隔著遮罩之微影技術進行圖型化，而同時形成電極墊上之開口B、用以在與貫穿電極連接的金屬配線(下面金屬配線)4b上形成貫穿第二絕緣層的金屬配線(貫穿金屬配線)之開口C、以及用以形成貫穿電極之開 口D，之後，進行烘烤，藉此使第二絕緣層8硬化。
於此圖型化中，係在形成第二絕緣層8之後，進行曝光、曝光後加熱處理(曝光後烘烤；PEB)，予以顯像，進而因應需要而進行後硬化來形成圖型。亦即，可使用周知之微影技術來進行圖型之形成，只要以與上述之第一絕緣層之圖型化相同的方法進行即可。
於本發明之半導體裝置之製造方法中，由於是藉由將電極墊上之開口B、用以形成貫穿金屬配線之開口C、以及用以形成貫穿電極之開口D進行整批曝光而同時形成，因此為合理。
進而，於步驟(8)中，如第10圖所示般，在第二絕緣層8之硬化後，進行以濺鍍所致之種晶層形成，其後，將電極墊上之開口B、用以形成貫穿第二絕緣層的金屬配線(貫穿金屬配線)之開口C、以及用以形成貫穿電極之開口D，藉由鍍敷來填埋，而形成半導體元件上金屬墊3、貫穿第二絕緣層之金屬配線(貫穿金屬配線)4c、以及貫穿電極5，並且將藉由鍍敷所形成的半導體元件上金屬墊3與貫穿第二絕緣層的金屬配線(貫穿金屬配線)4c藉由以鍍敷所得之金屬配線(上面金屬配線)4a相連結。
在進行鍍敷時，係與上述之步驟(3)相同地，例如，在藉由濺鍍而形成種晶層之後，進行鍍敷阻劑之圖型化，其後，進行電鍍等，形成半導體元件上金屬墊3、貫穿金屬配線4c、以及貫穿電極5，並且形成上面金屬配線4a而使半導體元件上金屬墊3與貫穿金屬配線4c相連 結。
另外，上面金屬配線4a雖只要如同成為所期望之配線寬度般地進行適當調整即可，但尤其以成為0.1~10μm之厚度的方式形成於第二絕緣層上為佳。
又，為了使貫穿電極5之鍍敷充足，如第11圖所示般，亦可另外再對貫穿電極5實施電鍍，並以金屬鍍敷18將貫穿電極5進行填埋。
又，為了使貫穿金屬配線4c之鍍敷充足，亦可另外再對貫穿金屬配線4c實施電鍍。
接著，於步驟(9)中，金屬配線之形成後，將光硬化性乾膜之光硬化性樹脂層進行疊層或者將使用於光硬化性乾膜之阻劑組成物材料進行旋轉塗佈，藉此如第12圖所示般地形成第三絕緣層9。
第三絕緣層9之形成，係與上述之第一絕緣層之形成相同地，可藉由使用具有由含有例如(A)~(D)成分所成之化學增幅型負型阻劑組成物材料所構成的光硬化性樹脂層的光硬化性乾膜來進行疊層，或者將此阻劑組成物材料藉由旋轉塗佈等進行塗佈而形成。當然，亦可使用其他的感光性樹脂。
又，若第三絕緣層之膜厚為5~100μm，則可將所製造之半導體裝置進行薄型化，故為佳。
接著，於步驟(10)中，如第13圖所示般，在對於第三絕緣層9，藉由隔著遮罩之微影技術進行圖型化而於貫穿電極5上部形成開口E之後，進行烘烤，藉此使 第三絕緣層9硬化。
於此圖型化中，係在形成第三絕緣層9之 後，進行曝光、曝光後加熱處理(曝光後烘烤；PEB)，予以顯像，進而因應需要而進行後硬化來形成圖型。亦即，可使用周知之微影技術來進行圖型之形成，只要以與上述之第一絕緣層之圖型化相同的方法進行即可。
接著，於步驟(11)中，係在第三絕緣層之硬化後，於貫穿電極上部之開口E形成焊錫凸塊。
作為焊錫凸塊之形成方法，例如，如第14圖所示般，於貫穿電極上部之開口E藉由鍍敷來形成貫穿電極上金屬墊19。接著，可於貫穿電極上金屬墊19上形成焊錫球20，將此製成焊錫凸塊。
又，可於上述步驟(8)中，如第15圖所示般，為了使貫穿電極5之鍍敷充足，而以SnAg進行另外實施的鍍敷來施以SnAg鍍敷21，其後，於步驟(9)中，係與上述相同地形成第三絕緣層9，於步驟(10)中以於貫穿電極上部形成開口E的方式進行圖型化，藉此而使SnAg鍍敷21露出，之後，藉由烘烤使其硬化，作為步驟(11)係藉由使SnAg鍍敷21熔融而如第16圖所示般地使電極朝貫穿電極上部之開口E隆起，而形成使SnAg隆起後的電極22之焊錫凸塊。
進而，於上述之步驟(11)之後，如第17圖所示般，將於上述之步驟(1)中與第一絕緣層7暫時接著的支撐基板16去除，藉此而可使貫穿電極5之焊錫球20的 相反側(下面金屬配線4b)露出，將露出後的種晶層藉由蝕刻去除，而使金屬鍍敷部露出，藉此可使貫穿電極5之上部與下部電導通。進而，其後，藉由進行切割而予以個片化，可得到經個片化的半導體裝置23。
於形成有使SnAg隆起後的電極22之焊錫凸塊的情況中亦相同地，如第18圖所示般，藉由將支撐基板16去除，而可使貫穿電極5之SnAg隆起後的電極22的相反側(下面金屬配線4b)露出，將露出後的種晶層藉由蝕刻去除，而使金屬鍍敷部露出，藉此可使貫穿電極5之上部與下部電導通。進而，其後，藉由進行切割而予以個片化，可得到經個片化的半導體裝置24。
另外，如上述般之本發明之製造方法係特別適於小型化、薄型化者，且可得到作為半導體裝置之厚度為50~300μm，較佳為70~150μm之薄的小型化之半導體裝置。
上述之經個片化的半導體裝置23或者經個片化之半導體裝置24，係如第19圖、第20圖所示般，分別將複數個，包夾絕緣樹脂層12，並藉由焊錫凸塊而電接合，進行層合而可製成層合型半導體裝置。又，如第21圖、第22圖所示般，亦可將層合後的半導體裝置載置於具有電路的基板(配線基板14)。另外，第19圖、第20圖、第21圖、第22圖係分別將經個片化的半導體裝置23或24進行倒裝晶片黏合的例子。
又，如第23圖、第24圖所示般，在將以上 述方式所製造的層合型半導體裝置載置於配線基板14之後，以絕緣封裝樹脂層15進行封裝，藉此而可製造封裝後層合型半導體裝置。
在此，作為絕緣樹脂層12或絕緣封裝樹脂層15所使用之樹脂係可使用一般於該用途中所使用者，可使用例如環氧樹脂或矽酮樹脂或此等之複合樹脂。
以上述方式所製造的本發明之半導體裝置、層合型半導體裝置、及封裝後層合型半導體裝置係可適合使用於對半導體晶片所實施之扇出配線(fan-out wiring)或WCSP(晶圓級晶片尺寸封裝)用。
如以上所述般，若為本發明之半導體裝置，則藉由於半導體元件上實施微細的電極形成，並於半導體元件外部施以貫穿電極，而使對於配線基板之載置或半導體裝置之層合為容易，進而，成為即使半導體元件的高度為數十μm亦可於半導體元件周邊無空隙等地進行填埋，即使在金屬配線的密度為大之情況中半導體裝置之翹曲亦受到抑制的半導體裝置。
又，若為本發明之半導體裝置之製造方法，則藉由於半導體元件上實施微細的電極形成，並於半導體元件外部施以貫穿電極，而可容易進行對於配線基板之載置或半導體裝置之層合，又可容易進行貫穿電極、電極墊部之開口等的加工。
進而，以如此方式所得到的本發明之半導體裝置係由於對於配線基板之載置或半導體裝置之層合為容易，因此 可製成將半導體裝置進行層合之層合型半導體裝置或將其載置於配線基板並加以封裝之封裝後層合型半導體裝置。
另外，本發明並不限定於上述實施形態。上述實施形態係為例示，具有與本發明之申請專利範圍所記載之技術思想實質上相同的構造，且發揮相同的作用效果者係任一者皆包含於本發明之技術範圍內。

Claims (14)

  1. 一種半導體裝置，其係具有半導體元件、與電連接於該半導體元件之半導體元件上金屬墊及金屬配線，且該金屬配線係電連接於貫穿電極及焊錫凸塊，其特徵為，具有：載置有前述半導體元件之第一絕緣層、形成於前述半導體元件上之第二絕緣層、以及形成於該第二絕緣層上之第三絕緣層，前述金屬配線係在前述第二絕緣層的上面經由前述半導體元件上金屬墊而電連接於前述半導體元件，且從前述第二絕緣層的上面貫穿前述第二絕緣層而在前述第二絕緣層的下面電連接於前述貫穿電極者。
  2. 如請求項1之半導體裝置，其中，前述第一絕緣層係藉由光硬化性乾膜或光硬化性阻劑塗佈膜所形成者，前述第二絕緣層係藉由前述光硬化性乾膜所形成者，前述第三絕緣層係藉由前述光硬化性乾膜或光硬化性阻劑塗佈膜所形成者。
  3. 如請求項1或2之半導體裝置，其中，前述半導體元件的高度為20~100μm，前述第一絕緣層的膜厚為1~20μm，前述第二絕緣層的膜厚為5~100μm，前述第三絕緣層的膜厚為5~100μm，前述半導體裝置的厚度為50~300μm。
  4. 如請求項1或2之半導體裝置，其中，前述光硬化性乾膜係具有由化學增幅型負型阻劑組成物材料所構成的光硬化性樹脂層之光硬化性乾膜，該化學增幅型負型阻 劑組成物材料係含有：(A)具有以下述一般式(1)所示之重複單元的重量平均分子量為3,000~500,000之含矽酮骨架之高分子化合物、 (式中，R1~R4係表示可相同或相異之碳數1~8的1價烴基；m為1~100之整數；a、b、c、d為0或正數，且a、b、c、d不同時為0；但，a+b+c+d=1；再者，X係以下述一般式(2)所示之有機基；Y係以下述一般式(3)所示之有機基) (式中，Z係由 中任一者所選出的2價之有機基，n為0或1；R5及R6係 各自為碳數1~4之烷基或烷氧基，且可彼此相異或相同；k為0、1、2中之任一者) (式中，V係由 中任一者所選出的2價之有機基，p為0或1；R7及R8係各自為碳數1~4之烷基或烷氧基，且可彼此相異或相同；h為0、1、2中之任一者)(B)由藉由甲醛或甲醛-醇改質而成的胺基縮合物、1分子中平均具有2個以上之羥甲基或烷氧基羥甲基的酚化合物所選出之1種或2種以上之交聯劑、(C)藉由波長190~500nm之光進行分解，而產生酸之光酸產生劑、以及(D)溶劑。
  5. 一種層合型半導體裝置，其特徵為，將如請求項1至4中任一項之半導體裝置倒裝晶片化並複數層合而成者。
  6. 一種封裝後層合型半導體裝置，其特徵為，將如請求項5之層合型半導體裝置載置於具有電路的基板上，並以絕緣封裝樹脂層加以封裝而成者。
  7. 一種半導體裝置之製造方法，其特徵為，具有以下步驟：(1)於支撐基板上塗佈暫時性接著劑，於該暫時性接著劑上形成使用阻劑組成物材料作為光硬化性樹脂層之膜厚1~20μm的第一絕緣層之步驟；(2)在對於前述第一絕緣層，藉由隔著遮罩之微影技術進行圖型化而形成成為貫穿電極的通孔圖型之後，進行烘烤，藉此使前述第一絕緣層硬化之步驟；(3)於前述第一絕緣層進行以濺鍍所致之種晶層形成，其後，將前述成為貫穿電極之通孔圖型，藉由鍍敷來填埋，而形成與貫穿電極連接的金屬配線之步驟；(4)使用晶片黏合劑將電極墊露出於上部表面之高度20~100μm的半導體元件晶片黏合於前述硬化後的第一絕緣層上之步驟；(5)準備具有膜厚5~100μm之光硬化性樹脂層為被支撐薄膜與保護薄膜包夾的結構，且該光硬化性樹脂層為由阻劑組成物材料所構成的光硬化性乾膜之步驟；(6)藉由以覆蓋被晶片黏合於前述第一絕緣層上之半導體元件的方式將前述光硬化性乾膜之光硬化性樹脂層進行疊層，而形成第二絕緣層之步驟；(7)對於前述第二絕緣層，藉由隔著遮罩之微影技術 進行圖型化，而同時形成前述電極墊上之開口、用以在與前述貫穿電極連接的金屬配線上形成貫穿前述第二絕緣層的金屬配線之開口、以及用以形成前述貫穿電極之開口，之後，進行烘烤，藉此使前述第二絕緣層硬化之步驟；(8)在硬化後，進行以濺鍍所致之種晶層形成，其後，將前述電極墊上之開口、用以形成貫穿前述第二絕緣層的金屬配線之開口、以及用以形成前述貫穿電極之開口，藉由鍍敷來填埋，而形成半導體元件上金屬墊、貫穿前述第二絕緣層之金屬配線、以及貫穿電極，並且將藉由前述鍍敷所形成的前述半導體元件上金屬墊與貫穿前述第二絕緣層的金屬配線藉由以鍍敷所得之金屬配線相連結之步驟；(9)金屬配線形成後，將前述光硬化性乾膜之光硬化性樹脂層進行疊層或者將使用於前述光硬化性乾膜之阻劑組成物材料進行旋轉塗佈，藉此形成第三絕緣層之步驟；(10)在對於前述第三絕緣層，藉由隔著遮罩之微影技術進行圖型化而於前述貫穿電極上部形成開口之後，進行烘烤，藉此使前述第三絕緣層硬化之步驟；(11)硬化後，於前述貫穿電極上部之開口形成焊錫凸塊之步驟。
  8. 如請求項7之半導體裝置之製造方法，其中，將在前述步驟(5)所準備的光硬化性乾膜設為具有由化學增幅型負型阻劑組成物材料所構成的光硬化性樹脂層之光硬化性乾膜，該化學增幅型負型阻劑組成物材料係含有： (A)具有以下述一般式(1)所示之重複單元的重量平均分子量為3,000~500,000之含矽酮骨架之高分子化合物、 (式中，R1~R4係表示可相同或相異之碳數1~8的1價烴基；m為1~100之整數；a、b、c、d為0或正數，且a、b、c、d不同時為0；但，a+b+c+d=1；再者，X係以下述一般式(2)所示之有機基，Y係以下述一般式(3)所示之有機基) (式中，Z係由 中任一者所選出的2價之有機基，n為0或1；R5及R6係 各自為碳數1~4之烷基或烷氧基，且可彼此相異或相同；k為0、1、2中之任一者) (式中，V係由 中任一者所選出的2價之有機基，p為0或1；R7及R8係各自為碳數1~4之烷基或烷氧基，且可彼此相異或相同；h為0、1、2中之任一者)(B)由藉由甲醛或甲醛-醇改質而成的胺基縮合物、1分子中平均具有2個以上之羥甲基或烷氧基羥甲基的酚化合物所選出之1種或2種以上之交聯劑、(C)藉由波長190~500nm之光進行分解，而產生酸之光酸產生劑、以及(D)溶劑。
  9. 如請求項7或8之半導體裝置之製造方法，其中，於前述步驟(6)中，包含對前述第二絕緣層進行機械性加壓之步驟。
  10. 如請求項7或8之半導體裝置之製造方法，其中，於前述步驟(11)中，具有：於前述貫穿電極上部之開口藉由鍍敷形成貫穿電極上金屬墊之步驟、以及於前述貫穿電極上金屬墊上形成焊錫球，製成焊錫凸塊之步驟。
  11. 如請求項7或8之半導體裝置之製造方法，其中，於前述步驟(8)之以鍍敷所致之前述貫穿電極的形成中，包含進行以SnAg所致之鍍敷之步驟，並且具有：於前述步驟(10)中，以於前述貫穿電極上部形成開口的方式進行圖型化，藉此使前述鍍敷後的SnAg露出之步驟、以及於前述步驟(11)中，藉由將前述鍍敷後的SnAg進行熔融而於前述貫穿電極上部之開口處使電極隆起而形成焊錫凸塊之步驟。
  12. 如請求項7或8之半導體裝置之製造方法，其中在前述步驟(11)之後，具有：將在前述步驟(1)與第一絕緣層暫時接著的支撐基板去除之步驟、以及在將前述基板去除後，進行切割，藉此予以個片化之步驟。
  13. 一種層合型半導體裝置之製造方法，其特徵為，將以如請求項12之製造方法來藉由切割而個片化的複數個半導體裝置，包夾絕緣樹脂層，並藉由前述焊錫凸塊電接合而進行層合。
  14. 一種封裝後層合型半導體裝置之製造方法，其特 徵為，具有：將以如請求項13之製造方法所製造的層合型半導體裝置載置於具有電路的基板之步驟、以及將載置於前述基板之層合型半導體裝置以絕緣封裝樹脂層進行封裝之步驟。
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