JP6028852B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP6028852B2 JP6028852B2 JP2015508373A JP2015508373A JP6028852B2 JP 6028852 B2 JP6028852 B2 JP 6028852B2 JP 2015508373 A JP2015508373 A JP 2015508373A JP 2015508373 A JP2015508373 A JP 2015508373A JP 6028852 B2 JP6028852 B2 JP 6028852B2
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/36—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the concentration or distribution of impurities in the bulk material
Description
実施の形態1にかかる半導体装置の構造について説明する。図1は、実施の形態1にかかる半導体装置の構造を示す断面図である。図2は、図1の切断線A−A'における不純物濃度分布を示す特性図である。図2において、横軸は基板裏面(n+カソード層4とカソード電極7との界面)から基板深さ方向の距離であり、縦軸には基板裏面側の領域を深さ方向に横切る切断線A−A'における不純物濃度を示す(図9,13においても同様)。図1に示すように、実施の形態1にかかる半導体装置は、n-ドリフト領域(第1半導体領域)1となるn-半導体基板に、活性領域10と、活性領域10を囲むエッジ終端構造部(エッジ部)11とを備える。活性領域10は、オン状態のときに電流が流れる領域である。エッジ終端構造部11は、基板おもて面側の電界を緩和し耐圧を保持する機能を有する。
次に、実施の形態2にかかる半導体装置の製造方法について説明する。図6は、実施の形態2にかかる半導体装置の製造方法の概要を示すフローチャートである。実施の形態2にかかる半導体装置の製造方法が実施の形態1にかかる半導体装置の製造方法と異なる点は、電子線照射によるライフタイム制御後にn+カソード層4を形成し、レーザーアニールによりn+カソード層4を活性化させる点である。
次に、実施の形態3にかかる半導体装置の製造方法について説明する。図7は、実施の形態3にかかる半導体装置の製造方法の概要を示すフローチャートである。実施の形態3にかかる半導体装置の製造方法が実施の形態2にかかる半導体装置の製造方法と異なる点は、n-半導体基板の裏面を研削してn-半導体基板の厚さを薄くする前に、n-半導体基板のおもて面にアノード電極3を形成する点である。
次に、実施の形態4にかかる半導体装置の構造について説明する。図8は、実施の形態4にかかる半導体装置の構造を示す断面図である。図9は、図8のB−B'切断線における不純物濃度分布を示す特性図である。実施の形態4にかかる半導体装置が実施の形態1にかかる半導体装置と異なる点は、基板裏面からプロトンの多段照射により形成されてなる、基板裏面からの深さが異なる複数のnバッファ層15を設けている点である。例えば、プロトンの3段照射によりnバッファ層15が形成されている場合、n-ドリフト領域1となるn-半導体基板の裏面から最も深い位置にnバッファ層15aが配置される。
次に、実施の形態5にかかる半導体装置の構造について説明する。図11は、実施の形態5にかかる半導体装置の構造を示す断面図である。図11の切断線A−A'における不純物濃度分布は、図2に示す不純物濃度分布と同様である。実施の形態5にかかる半導体装置が実施の形態1にかかる半導体装置と異なる点は、n+カソード層14の端部14aをn-半導体基板の側面1aよりも内側(FWDセルの中央部側)に位置させる点である。すなわち、実施の形態5においては、エッジ終端構造部11における基板裏面には、n+カソード層14は設けられておらず、カソード電極7とnバッファ層5とのショットキー接合が形成されている。
次に、実施の形態6にかかる半導体装置の構造について説明する。図12は、実施の形態6にかかる半導体装置の構造を示す断面図である。図13は、図12の切断線C−C'における不純物濃度分布を示す特性図である。図12の切断線A−A'における不純物濃度分布は、図2に示す不純物濃度分布と同様である。実施の形態6にかかる半導体装置が実施の形態5にかかる半導体装置と異なる点は、エッジ終端構造部11におけるnバッファ層5の内部にカソード電極7に接するp-領域(第6半導体領域)16を設けることで、p-領域16とカソード電極7とのショットキー接合を形成した点である。p-領域16の外周端部16aは、n-半導体基板の側面1aにまで延在されている。p-領域16の不純物濃度は、埋め込みp層6の不純物濃度と等しくてもよい。
次に、実施の形態7にかかる半導体装置の構造について説明する。図14は、実施の形態7にかかる半導体装置の構造を示す断面図である。図15〜17は、実施の形態7にかかる半導体装置の埋め込みp層の平面パターンの一例を示す平面図である。図15〜17には、基板裏面のn+カソード層4に基板おもて面側から投射したアノードコンタクトの端部3aの位置を点線で示す(図21,22においても同様)。実施の形態7にかかる半導体装置が実施の形態1にかかる半導体装置と異なる点は、埋め込みp層26を選択的に設けることにより、アノードコンタクトの端部3aよりも内側の部分の表面積A10に対する、埋め込みp層26の表面積の占有面積A11の面積比率(=A11/A10)を所定範囲に設定している点である。
次に、実施の形態8にかかる半導体装置の構造について説明する。図19は、実施の形態8にかかる半導体装置の構造を示す断面図である。実施の形態8にかかる半導体装置が実施の形態7にかかる半導体装置と異なる点は、基板裏面からプロトンの多段照射により形成されてなる、基板裏面からの深さが異なる複数のnバッファ層15を設けている点である。nバッファ層15の構成は実施の形態4と同様である。すなわち、例えばプロトンの3段照射によりnバッファ層15を形成する場合、nバッファ層15は、n-半導体基板の裏面から深い側から浅い側へ順にnバッファ層15a〜15cが配置されてなる。
次に、実施の形態9にかかる半導体装置の構造について説明する。図20は、実施の形態9にかかる半導体装置の構造を示す断面図である。図21は、図20の埋め込みp層の平面パターンの一例を示す平面図である。図21には、埋め込みp層(以下、第1,2埋め込みp層とする)26,36を所定間隔で規則的に並べたマトリクス状に配置した一例を示す。実施の形態9にかかる半導体装置が実施の形態7にかかる半導体装置と異なる点は、エッジ終端構造部11にも第2埋め込みp層36を選択的に設け、アノードコンタクトの端部3aよりも外側の部分の表面積A20に対する、エッジ終端構造部11の第2埋め込みp層36の表面積の占有面積A21の面積比率(=A21/A20)を所定範囲に設定している点である。
次に、実施の形態10にかかる半導体装置の構造について説明する。図22は、実施の形態10にかかる半導体装置の構造を示す平面図である。図22には、埋め込みp層の平面パターンの一例を示す。実施の形態10にかかる半導体装置が実施の形態1にかかる半導体装置と異なる点は、矩形状のアノードコンタクトの端部3aの4つのコーナー部に、それぞれ、アノードコンタクトの端部3aとエッジ終端構造部11との境界付近を跨ぐように第2埋め込みp層46を配置した点である。第2埋め込みp層46は、アノードコンタクトの端部3aの内側の埋め込みp層(以下、第1埋め込みp層とする)6に接する。
次に、過渡VF(オン電圧)および逆回復時のサージ電圧と埋め込みp層の面積比率との関係について検証した。図23は、実施例1にかかる半導体装置の過渡的な順方向電圧および逆回復時のサージ電圧と埋め込みp層の面積比率との関係を示す特性図である。上述した実施の形態7にかかる半導体装置の製造方法にしたがい、埋め込みp層の面積比率を種々変更したFWD(以下、実施例1とする)を作製し、過渡VF(オン電圧)および逆回復時のサージ電圧を測定した結果を図23に示す。実施例1は、耐圧を1200Vとし、定格電流を100Aとし、電源電圧Vccを900Vとし、ジャンクション(pn接合部)温度Tjを室温(例えば25℃)とした。
次に、実施の形態11にかかる半導体装置の製造方法について説明する。図24は、実施の形態11にかかる半導体装置の製造方法の概要を示すフローチャートである。実施の形態11にかかる半導体装置の製造方法が実施の形態4にかかる半導体装置の製造方法と異なる点は、おもて面保護膜の形成後に、基板裏面側に行う各プロセス(以下、裏面形成プロセスとする)を行う点である。
次に、実施の形態12にかかる半導体装置の製造方法について説明する。図25は、実施の形態12にかかる半導体装置の製造方法の概要を示すフローチャートである。実施の形態12にかかる半導体装置の製造方法が実施の形態11にかかる半導体装置の製造方法と異なる点は、n+カソード層4および埋め込みp層6を活性化させるためのレーザーアニール後に、炉アニールによりnバッファ層15a〜15cを活性化させる点である。
次に、実施の形態13にかかる半導体装置の製造方法について説明する。図26は、実施の形態13にかかる半導体装置の製造方法の概要を示すフローチャートである。実施の形態13にかかる半導体装置の製造方法が実施の形態11にかかる半導体装置の製造方法と異なる点は、n+カソード層4および埋め込みp層6を活性化させるためのレーザーアニール後に、プロトン照射によりnバッファ層15a〜15cを形成し、その後炉アニールによりnバッファ層15a〜15cを活性化させる点である。
次に、実施の形態14にかかる半導体装置の製造方法について説明する。図27は、実施の形態14にかかる半導体装置の製造方法の概要を示すフローチャートである。実施の形態14にかかる半導体装置の製造方法が実施の形態13にかかる半導体装置の製造方法と異なる点は、埋め込みp層6を形成した後に、n+カソード層4を形成する点である。
1a n-半導体基板の側面
2 p+アノード層
3 アノード電極
3a アノードコンタクトの端部
4,14 n+カソード層
5,15,15a〜15c nバッファ層
6 埋め込みp層
6a 埋め込みp層の端部
7 カソード電極
9 層間絶縁膜
10 活性領域
11 エッジ終端構造部
14a n+カソード層の端部
16 p-領域
16a p-領域の外周端部
16b p-領域の内周端部
Claims (24)
- 第1導電型の第1半導体領域と、
前記第1半導体領域の一方の面の表面層に選択的に設けられた第2導電型の第2半導体領域と、
前記第2半導体領域に接する第1電極と、
前記第1半導体領域の他方の面の表面層に設けられた、前記第1半導体領域よりも不純物濃度が高い第1導電型の第3半導体領域と、
前記第1半導体領域の内部の、前記他方の面から前記第3半導体領域よりも深い位置に設けられた第2導電型の第4半導体領域と、
前記第3半導体領域に接する第2電極と、
を備え、
前記第4半導体領域の、前記第1電極と前記第2半導体領域とが接触する領域の接触端部よりも内周側の部分の外周側の端部のうち最も前記接触端部に近い端部は、前記接触端部よりも少なくとも少数キャリアの拡散長分内側に位置することを特徴とする半導体装置。 - 前記第4半導体領域は、前記他方の面に平行な方向に互いに離して複数配置されていることを特徴とする請求項1に記載の半導体装置。
- 前記第1半導体領域の内部の、前記他方の面から前記第3半導体領域よりも深い位置に設けられた、前記第1半導体領域よりも不純物濃度が高く、かつ前記第3半導体領域よりも不純物濃度が低い第1導電型の第5半導体領域をさらに備えることを特徴とする請求項1または2に記載の半導体装置。
- 前記第3半導体領域の端部は、前記第1半導体領域の側面よりも内側に位置し、
前記第3半導体領域の外側で、前記第5半導体領域と前記第2電極とが接していることを特徴とする請求項3に記載の半導体装置。 - 前記第3半導体領域の外側の前記第5半導体領域の内部に、前記第3半導体領域および前記第4半導体領域と離して設けられた第2導電型の第6半導体領域をさらに備えることを特徴とする請求項3または4に記載の半導体装置。
- 前記第5半導体領域は、複数回のプロトン照射により形成されてなる領域であり、前記他方の面から異なる深さで複数配置されていることを特徴とする請求項3〜5のいずれか一つに記載の半導体装置。
- 前記第5半導体領域は、前記他方の面から前記第4半導体領域よりも深い位置に、前記第4半導体領域と離して設けられていることを特徴とする請求項6に記載の半導体装置。
- 主電流が流れる活性領域の表面積に対する、前記第4半導体領域の表面積の占有面積比率は、90%以上98%以下であることを特徴とする請求項1〜7のいずれか一つに記載の半導体装置。
- 前記接触端部を、前記一方の面側から前記他方の面に投射した接触端部位置よりも外周側の、前記他方の面の表面積をA20とし、
前記第4半導体領域の、前記接触端部位置よりも外周側の部分の前記他方の面に平行な面の総表面積をA21とし、
前記接触端部位置よりも内周側の、前記他方の面の表面積をA10とし、
前記第4半導体領域の、前記接触端部位置よりも内周側の部分の前記他方の面に平行な面の総表面積をA11としたときに、
A21/A20<A11/A10を満たすことを特徴とする請求項1〜8のいずれか一つに記載の半導体装置。 - 前記第4半導体領域の、前記接触端部を前記一方の面側から前記他方の面に投射した接触端部位置よりも内周側の部分の前記他方の面に水平な方向の長さは250μm以上であることを特徴とする請求項1〜8のいずれか一つに記載の半導体装置。
- 前記第4半導体領域の、前記接触端部を前記一方の面側から前記他方の面に投射した接触端部位置よりも内周側の部分の前記他方の面に水平な方向の長さL1は、活性領域に流れる主電流の電流密度J、電荷素量q、正孔移動度μ、前記第4半導体領域の深さ方向の厚さd、前記第4半導体領域の不純物濃度Np、前記第4半導体領域と前記第3半導体領域との間のpn接合の内蔵電位Vbiとして、
L1≧{(q・μ・d・Np・Vbi)/J} 1/2
を満たすことを特徴とする請求項1〜7のいずれか一つに記載の半導体装置。 - 前記第4半導体領域の、前記接触端部を前記一方の面側から前記他方の面に投射した接触端部位置よりも内周側の部分の外周側の端部のうち最も前記接触端部位置に近い端部と、前記接触端部位置と、とが離間する離間部の間隔は2000μm以下であることを特徴とする請求項1〜8のいずれか一つに記載の半導体装置。
- 前記第4半導体領域は、矩形状の平面形状を有する前記第1半導体領域の、頂点を共有する2辺にそれぞれ平行な2辺を少なくとも有し、かつ当該2辺の連結部を当該2辺の交点よりも内側に位置させた平面形状を有することを特徴とする請求項1〜12のいずれか一つに記載の半導体装置。
- 主電流が流れる活性領域の周囲を囲み、耐圧を保持する終端構造部、
をさらに備え、
前記第4半導体領域は、前記活性領域に設けられており、
前記活性領域のアバランシェ耐圧は、前記終端構造部のアバランシェ耐圧よりも低いことを特徴とする請求項1〜7のいずれか一つに記載の半導体装置。 - 前記活性領域の周囲を囲み、耐圧を保持する終端構造部、
をさらに備え、
前記第4半導体領域は、前記活性領域に設けられており、
前記活性領域のアバランシェ耐圧は、前記終端構造部のアバランシェ耐圧よりも低いことを特徴とする請求項8または11に記載の半導体装置。 - 前記第4半導体領域の端部は、前記第3半導体領域の端部よりも内側に位置することを特徴とする請求項3〜7のいずれか一つに記載の半導体装置。
- 前記第5半導体領域と前記第2電極との接触がショットキー接合であることを特徴とする請求項3〜7、16のいずれか一つに記載の半導体装置。
- 前記第1半導体領域の前記他方の面に設けられた、前記第1半導体領域と他部材とを接合する半田層をさらに備え、
前記半田層は、前記他方の面から前記第1半導体領域の側面に達していることを特徴とする請求項1〜17のいずれか一つに記載の半導体装置。 - 第1導電型の第1半導体領域となる半導体基板の一方の主面の表面層に、第2導電型の第2半導体領域を選択的に形成する第1工程と、
前記第2半導体領域に接する第1電極を形成する第2工程と、
前記半導体基板の他方の主面の表面層に、前記第1半導体領域よりも不純物濃度が高い第1導電型の第3半導体領域を形成する第3工程と、
前記半導体基板の他方の主面から前記第3半導体領域よりも深い位置に、第2導電型の第4半導体領域を形成する第4工程と、
レーザーアニールにより、前記第3半導体領域および前記第4半導体領域を活性化させる第5工程と、
複数回のプロトン照射により、前記半導体基板の他方の主面から前記第4半導体領域よりも深い位置に異なる深さで、前記第1半導体領域よりも不純物濃度が高く、かつ前記第3半導体領域よりも不純物濃度が低い第1導電型の複数の第5半導体領域を形成する第6工程と、
炉アニールにより前記第5半導体領域を活性化させる第7工程と、
前記第3半導体領域に接する第2電極を形成する第8工程と、
を含み、
前記第4工程では、前記第4半導体領域の、前記第1電極と前記第2半導体領域とが接触する領域の接触端部よりも内周側の部分の外周側の端部のうち最も前記接触端部に近い端部が前記接触端部よりも少なくとも少数キャリアの拡散長分内側に位置するように、前記第4半導体領域を形成することを特徴とする半導体装置の製造方法。 - 前記第7工程の後に、キャリアのライフタイムを制御する照射工程と、該照射工程の後にライフタイムアニール工程と、を含むことを特徴とする請求項19に記載の半導体装置の製造方法。
- 前記第2工程の後に、前記半導体基板の他方の主面を研削して前記半導体基板の厚さを薄くする研削工程を含むことを特徴とする請求項19または20に記載の半導体装置の製造方法。
- 第1導電型の第1半導体領域となる半導体基板の一方の主面の表面層に、第2導電型の第2半導体領域を選択的に形成する第1工程と、
前記第2半導体領域に接する第1電極を形成する第2工程と、
前記半導体基板の他方の主面の表面層に、第2導電型の第4半導体領域を形成する第3工程と、
前記半導体基板の他方の主面から前記第4半導体領域よりも浅い位置に、前記第1半導体領域よりも不純物濃度が高い第1導電型の第3半導体領域を形成する第4工程と、
レーザーアニールにより、前記第3半導体領域および前記第4半導体領域を活性化させる第5工程と、
複数回のプロトン照射により、前記半導体基板の他方の主面から前記第4半導体領域よりも深い位置に異なる深さで、前記第1半導体領域よりも不純物濃度が高く、かつ前記第3半導体領域よりも不純物濃度が低い第1導電型の複数の第5半導体領域を形成する第6工程と、
炉アニールにより前記第5半導体領域を活性化させる第7工程と、
前記第3半導体領域に接する第2電極を形成する第8工程と、
を含み、
前記第3工程では、前記第4半導体領域の、前記第1電極と前記第2半導体領域とが接触する領域の接触端部よりも内周側の部分の外周側の端部のうち最も前記接触端部に近い端部が前記接触端部よりも少なくとも少数キャリアの拡散長分内側に位置するように、前記第4半導体領域を形成することを特徴とする半導体装置の製造方法。 - 前記第7工程の後に、キャリアのライフタイムを制御する照射工程と、該照射工程の後にライフタイムアニール工程と、を含むことを特徴とする請求項22に記載の半導体装置の製造方法。
- 前記第2工程の後に、前記半導体基板の他方の主面を研削して前記半導体基板の厚さを薄くする研削工程を含むことを特徴とする請求項22または23に記載の半導体装置の製造方法。
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