JP6023825B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims description 26
- 230000005533 two-dimensional electron gas Effects 0.000 description 28
- 238000000034 method Methods 0.000 description 15
- 229910004298 SiO 2 Inorganic materials 0.000 description 10
- 238000005530 etching Methods 0.000 description 8
- 150000002500 ions Chemical class 0.000 description 8
- 229910002704 AlGaN Inorganic materials 0.000 description 6
- 229910052782 aluminium Inorganic materials 0.000 description 6
- 230000000694 effects Effects 0.000 description 6
- 150000004767 nitrides Chemical class 0.000 description 6
- 229910052738 indium Inorganic materials 0.000 description 5
- 230000007423 decrease Effects 0.000 description 4
- 229910052733 gallium Inorganic materials 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 3
- 238000002230 thermal chemical vapour deposition Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 229910002601 GaN Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229910001415 sodium ion Inorganic materials 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
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Description
本明細書では、上記技術でノーマリオフの特性に調整した半導体装置のオン抵抗を低下させる技術を開示する。
この場合、耐圧を維持しながら、オン抵抗を低下させることができる。
この場合は、耐圧を維持しながら、オン抵抗を低下させることができる。
(特徴1) 電子走行層はGaNで形成されており、電子走行層はAlGaNで形成されている。
(特徴2) 絶縁層はSiO2層で形成されている。SiO2層は電子走行層を形成するAlGaNのGaがSiO2層中に移動する温度領域で形成する。
(特徴3) ソース電極とp型層間の距離<ドレイン電極とp型層間の距離であり、ソース電極とp型層の間の絶縁層は全域で正に帯電しており、ドレイン電極とp型層の間の絶縁層は、ドレイン電極側では正に帯電し、p型層側では正に帯電していない。
(特徴4)電子走行層にGaNを用い、電子供給層にInとAlの少なくとも一方とGaを含む窒化物半導体であってGaNより大きなバンドギャップを持つ窒化物半導体を用いる。すなわち、電子走行層にInx1Aly1Ga1−x1−y1N(0≦x1<1,0≦y1<1,0<1−x1−y1<1)を用いる。
(特徴5)電子走行層にGaNを用い、電子供給層にAlとGaを含む窒化物半導体であってGaNより大きなバンドギャップを持つ窒化物半導体を用いる。すなわち、電子走行層にInx1Aly1Ga1−x1−y1N(0≦x1<1,0<y1<1,0<1−x1−y1<1)を用いる。
絶縁層12,18が正に帯電しているために、絶縁層12,18に対向する範囲のヘテロ接合界面に電子が吸引され、絶縁層12,18に対向する範囲のヘテロ接合界面に生じている2次元電子ガスの濃度が高い。そのために、ヘテロ接合界面のソース電極10とp型層16間の抵抗が低く、ヘテロ接合界面のドレイン電極20とp型層16間の抵抗が低い。ゲート電極に正電圧を印加したときのソース電極10とドレイン電極20間の抵抗(オン抵抗)が低い。
図1に示すp型層16とソース電極10の間、ならびに、図1に示すp型層16とドレイン電極20の間でp型広域層をエッチングすると、図1に示すp型層16とソース電極10の間、ならびに、図1に示すp型層16とドレイン電極20の間で露出する電子供給層8の表面にエッチングダメージが加えられる。そのエッチングダメージは、ヘテロ接合界面に生じる2次元電子ガスの濃度を減少させてしまう。図1の半導体装置では、エッチングダメージによる2次元電子ガス濃度の減少効果を、正に帯電した絶縁層12,18による2次元電子ガス濃度の上昇効果によって補償することができ、オン抵抗を低下させることが可能となる。
図1の半導体装置は、正に帯電した絶縁層12,18によって2次元電子ガスの濃度を上昇させる効果と、電子が走行する電子走行層6がi型であることが相まって、オン抵抗が非常に低い。
図2に示すように、ドレイン電極20とp型層16の間に露出する電子供給層8の一部の領域を正に帯電した絶縁層18bで被覆し、他の領域は、正に帯電しない絶縁層18aで被覆してもよい。この場合は、ドレイン電極20側を正電荷が固定された絶縁層18bで被覆し、p型層16側を正電荷が固定されていない絶縁層18aで被覆する。
この場合、正に帯電した絶縁層18bで被覆されているドレイン電極20側ではオン抵抗が低下する。それに対し、ゲート電極14の近傍では、オフ時にゲート電極14側からドレイン電極20側に向かって伸びる空乏層中の電界が大きく緩和され、高耐圧と低抵抗を実現する。
図2では、ソース電極10とp型層16の距離<ドレイン電極20とp型層16の距離の関係にあり、ドレイン電極側でのみ、一部領域を正に帯電した絶縁層で被覆する技術を適用する。この技術をソース電極側に利用することもできる。
図3に示すように、電子供給層8aを形成するAlGaNのAl濃度を薄くすることによって閾値電圧を高く設定することができる。誤作動防止に有用である。
その反面、Al濃度を薄くすると、例えばAly1Ga1−y1Nのy1を0.1以下にすると、ヘテロ接合界面に生じる2次元電子ガスの濃度が低下し、オン抵抗が上昇する。本実施例は、この問題に対処するものであり、正に帯電した絶縁層12,18でオン抵抗を下げる。本技術は、電子供給層8aを形成するAlGaNのAl濃度を薄くして閾値電圧を高く設定する場合に特に有用である。
図4は第4実施例を示し、絶縁層12c,18cに、Gaイオンが分散して混入しているSiO2層を用いる。Gaイオンは正電荷を帯びており、絶縁層12c,18cは正に帯電している。このSiO2層は、電子供給層8の表面に熱CVD法によってSiO2を堆積することで形成される。熱CVD法の実施温度を高めていくと、電子供給層8に含まれていたGaがSiO2内に移動する量が増えていく。必要な電荷量に相当するGaが移動する温度で熱CVD法を実施することで、正に帯電した絶縁層12c,18cを形成することができる。プラズマCVD法によっても、Gaイオンが分散して存在しているSiO2層を形成することができる。正イオンを含まない絶縁層に、例えばNa正イオンあるいはGa正イオンを注入してもよい。NaイオンやGaイオン等は、絶縁層中で移動しづらく、正電荷が固定されている絶縁層となる。
4:バッファ層
6:電子走行層
8:電子供給層
10:ソース電極
12:絶縁層
14:ゲート電極
16:p型層
18:絶縁層
20:ドレイン電極
Claims (2)
- GaNで形成されている電子走行層とInx1Aly1Ga1−x1−y1N(0≦x1≦1,0≦y1≦1,0≦1−x1−y1<1)で形成されている電子供給層のヘテロ接合構造を備えており、
前記電子供給層の表面上の相互に離れた位置に、ソース電極とドレイン電極が形成されており、
前記ソース電極と前記ドレイン電極の間に位置する前記電子供給層の表面上に、Inx2Aly2Ga1−x2−y2N(0≦x2≦1,0≦y2≦1,0≦1−x2−y2≦1)のp型層が形成されており、
前記p型層の表面上に、ゲート電極が形成されており、
前記ソース電極と前記p型層の間に露出する前記電子供給層の表面および/または前記ドレイン電極と前記p型層の間に露出する前記電子供給層の表面が、正電荷が固定されている絶縁層で被覆されており、
前記絶縁層中にGaが分散して存在していることを特徴とする半導体装置。 - 前記ドレイン電極と前記p型層の間に露出する前記電子供給層の表面を被覆する前記絶縁層の前記ドレイン電極側には正電荷が固定され、前記絶縁層の前記p型層側には正電荷が固定されていないことを特徴とする請求項1に記載の半導体装置。
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Application Number | Priority Date | Filing Date | Title |
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JP2015004733A JP6023825B2 (ja) | 2015-01-14 | 2015-01-14 | 半導体装置 |
US14/965,463 US20160204254A1 (en) | 2015-01-14 | 2015-12-10 | Semiconductor device |
DE102016100116.3A DE102016100116B4 (de) | 2015-01-14 | 2016-01-05 | Halbleitereinrichtung und Verfahren zu deren Herstellung |
KR1020160001520A KR101756580B1 (ko) | 2015-01-14 | 2016-01-06 | 반도체 장치 |
CN201610021314.9A CN105789297B (zh) | 2015-01-14 | 2016-01-13 | 半导体装置 |
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CN115938939B (zh) * | 2022-10-14 | 2023-07-07 | 北京镓纳光电科技有限公司 | 一种提高氮化镓基高电子迁移率晶体管的二维电子气浓度的方法 |
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JP2533135B2 (ja) * | 1987-09-18 | 1996-09-11 | 富士通株式会社 | 微粒子トランジスタ |
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WO2007006001A2 (en) * | 2005-07-06 | 2007-01-11 | International Rectifier Corporation | Iii-nitride enhancement mode devices |
JP2008034438A (ja) * | 2006-07-26 | 2008-02-14 | Sanken Electric Co Ltd | 半導体装置 |
JP2009111204A (ja) * | 2007-10-31 | 2009-05-21 | Panasonic Corp | 電界効果トランジスタ及びその製造方法 |
US20110210377A1 (en) * | 2010-02-26 | 2011-09-01 | Infineon Technologies Austria Ag | Nitride semiconductor device |
US20110248283A1 (en) * | 2010-04-07 | 2011-10-13 | Jianjun Cao | Via structure of a semiconductor device and method for fabricating the same |
JP5179611B2 (ja) * | 2011-03-04 | 2013-04-10 | シャープ株式会社 | ノーマリオフ型ヘテロ接合電界効果トランジスタ |
CN102184943A (zh) * | 2011-04-18 | 2011-09-14 | 电子科技大学 | 一种增强型AlGaN/GaN HEMT器件及其制备方法 |
JP2013080794A (ja) * | 2011-10-03 | 2013-05-02 | Sharp Corp | 高電子移動度トランジスタ |
JP2014045174A (ja) * | 2012-08-01 | 2014-03-13 | Sharp Corp | 窒化物半導体装置 |
US8933461B2 (en) * | 2012-08-09 | 2015-01-13 | Texas Instruments Incorporated | III-nitride enhancement mode transistors with tunable and high gate-source voltage rating |
US20140335666A1 (en) * | 2013-05-13 | 2014-11-13 | The Government Of The United States Of America, As Represented By The Secretary Of The Navy | Growth of High-Performance III-Nitride Transistor Passivation Layer for GaN Electronics |
JP6223010B2 (ja) | 2013-06-19 | 2017-11-01 | オリンパス株式会社 | 顕微鏡システム |
US9590048B2 (en) * | 2013-10-31 | 2017-03-07 | Infineon Technologies Austria Ag | Electronic device |
JP2015177069A (ja) * | 2014-03-14 | 2015-10-05 | 株式会社東芝 | 半導体装置 |
CN104009076B (zh) * | 2014-05-29 | 2017-04-12 | 西安电子科技大学 | 一种AlGaN/GaN异质结场效应晶体管 |
JP6223938B2 (ja) * | 2014-09-19 | 2017-11-01 | 株式会社東芝 | ゲート制御装置、半導体装置、及び半導体装置の制御方法 |
US11289593B2 (en) * | 2015-07-31 | 2022-03-29 | Infineon Technologies Austria Ag | Breakdown resistant HEMT substrate and device |
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KR20160087752A (ko) | 2016-07-22 |
CN105789297A (zh) | 2016-07-20 |
CN105789297B (zh) | 2020-09-15 |
DE102016100116A1 (de) | 2016-07-14 |
KR101756580B1 (ko) | 2017-07-10 |
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US20160204254A1 (en) | 2016-07-14 |
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