JP6017141B2 - チップパッケージ及びその形成方法 - Google Patents

チップパッケージ及びその形成方法 Download PDF

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JP6017141B2
JP6017141B2 JP2012007478A JP2012007478A JP6017141B2 JP 6017141 B2 JP6017141 B2 JP 6017141B2 JP 2012007478 A JP2012007478 A JP 2012007478A JP 2012007478 A JP2012007478 A JP 2012007478A JP 6017141 B2 JP6017141 B2 JP 6017141B2
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conductive pad
chip package
conductive
layer
package according
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JP2012151475A (ja
JP2012151475A5 (enExample
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百堯 樓
百堯 樓
滄宇 劉
滄宇 劉
佳昇 林
佳昇 林
子翔 洪
子翔 洪
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精材科技股▲ふん▼有限公司
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0234—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising etching via holes that stop on pads or on electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0238—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising etching via holes through pads or through electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0242—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising etching via holes from the back sides of the chips, wafers or substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H10W20/211—Through-semiconductor vias, e.g. TSVs
    • H10W20/216—Through-semiconductor vias, e.g. TSVs characterised by dielectric material at least partially filling the via holes, e.g. covering the through-semiconductor vias in the via holes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H10W70/635—Through-vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/114—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
    • H10W74/117—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W76/00—Containers; Fillings or auxiliary members therefor; Seals
    • H10W76/10—Containers or parts thereof
    • H10W76/12—Containers or parts thereof characterised by their shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/019—Manufacture or treatment of bond pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H10W72/242—Dispositions, e.g. layouts relative to the surface, e.g. recessed, protruding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H10W72/244—Dispositions, e.g. layouts relative to underlying supporting features, e.g. bond pads, RDLs or vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/29—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/59—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/853—On the same surface
    • H10W72/856—Bump connectors and die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/922—Bond pads being integral with underlying chip-level interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/923—Bond pads having multiple stacked layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/9415—Dispositions of bond pads relative to the surface, e.g. recessed, protruding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/942—Dispositions of bond pads relative to underlying supporting features, e.g. bond pads, RDLs or vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/944—Dispositions of multiple bond pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/951—Materials of bond pads
    • H10W72/952—Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/951—Materials of bond pads
    • H10W72/953—Materials of bond pads not comprising solid metals or solid metalloids, e.g. polymers, ceramics or liquids
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
JP2012007478A 2011-01-17 2012-01-17 チップパッケージ及びその形成方法 Active JP6017141B2 (ja)

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US201161433379P 2011-01-17 2011-01-17
US61/433,379 2011-01-17

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JP2012151475A JP2012151475A (ja) 2012-08-09
JP2012151475A5 JP2012151475A5 (enExample) 2015-03-05
JP6017141B2 true JP6017141B2 (ja) 2016-10-26

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US (2) US8742564B2 (enExample)
JP (1) JP6017141B2 (enExample)
CN (1) CN102593094B (enExample)
TW (1) TWI581390B (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20160124999A (ko) * 2015-04-20 2016-10-31 주식회사 아이센스 유체 밀봉 저장백

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8742564B2 (en) * 2011-01-17 2014-06-03 Bai-Yao Lou Chip package and method for forming the same
US9711403B2 (en) * 2011-01-17 2017-07-18 Xintec Inc. Method for forming chip package
JP5958732B2 (ja) * 2011-03-11 2016-08-02 ソニー株式会社 半導体装置、製造方法、および電子機器
JP5754239B2 (ja) 2011-05-24 2015-07-29 ソニー株式会社 半導体装置
TWI485818B (zh) * 2011-06-16 2015-05-21 精材科技股份有限公司 晶片封裝體及其形成方法
US9006896B2 (en) * 2012-05-07 2015-04-14 Xintec Inc. Chip package and method for forming the same
US8975739B2 (en) * 2013-01-11 2015-03-10 Xintec Inc. Package structure and method for manufacturing thereof
TWI553841B (zh) * 2013-01-31 2016-10-11 原相科技股份有限公司 晶片封裝及其製造方法
TWI525673B (zh) 2013-10-08 2016-03-11 精材科技股份有限公司 晶圓級晶片封裝體的製造方法
TWI550794B (zh) * 2014-12-17 2016-09-21 精材科技股份有限公司 晶片封裝體及其製造方法
CN104576564A (zh) * 2015-01-26 2015-04-29 华天科技（昆山）电子有限公司 晶圆级芯片尺寸封装结构及其制作工艺
CN106098662B (zh) * 2015-04-27 2019-02-19 精材科技股份有限公司 半导体电镀系统
US10373883B2 (en) * 2017-10-26 2019-08-06 Advanced Semiconductor Engineering, Inc. Semiconductor package device and method of manufacturing the same
JP2020098849A (ja) * 2018-12-18 2020-06-25 ソニーセミコンダクタソリューションズ株式会社 半導体装置
CN110620055B (zh) * 2019-09-23 2021-06-25 九江市海纳电讯技术有限公司 一种rf射频装置的键合方法
CN112735964B (zh) * 2020-12-23 2023-12-22 武汉新芯集成电路制造有限公司 晶圆表面缺陷检测及表面修复方法

Family Cites Families (41)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2849346B1 (fr) * 2002-12-20 2006-12-08 Thales Sa Boitier hyperfrequence a montage de surface et montage correspondant avec un circuit multicouche.
JP4248928B2 (ja) * 2003-05-13 2009-04-02 ローム株式会社 半導体チップの製造方法、半導体装置の製造方法、半導体チップ、および半導体装置
JP2005109221A (ja) * 2003-09-30 2005-04-21 Toshiba Corp ウェーハレベルパッケージ及びその製造方法
US7091124B2 (en) * 2003-11-13 2006-08-15 Micron Technology, Inc. Methods for forming vias in microelectronic devices, and methods for packaging microelectronic devices
JP2006210438A (ja) * 2005-01-25 2006-08-10 Nec Electronics Corp 半導体装置およびその製造方法
JP4311376B2 (ja) * 2005-06-08 2009-08-12 セイコーエプソン株式会社 半導体装置、半導体装置の製造方法、電子部品、回路基板及び電子機器
JP4745007B2 (ja) * 2005-09-29 2011-08-10 三洋電機株式会社 半導体装置及びその製造方法
JP5117698B2 (ja) * 2006-09-27 2013-01-16 ルネサスエレクトロニクス株式会社 半導体装置
TWI370515B (en) * 2006-09-29 2012-08-11 Megica Corp Circuit component
US20080284041A1 (en) * 2007-05-18 2008-11-20 Samsung Electronics Co., Ltd. Semiconductor package with through silicon via and related method of fabrication
JP2009147218A (ja) * 2007-12-17 2009-07-02 Toshiba Corp 半導体装置とその製造方法
CN101465299B (zh) 2007-12-20 2011-06-15 南茂科技股份有限公司 芯片重新配置的封装结构中使用研磨的制造方法
JP5259197B2 (ja) * 2008-01-09 2013-08-07 ソニー株式会社 半導体装置及びその製造方法
US20090189296A1 (en) * 2008-01-30 2009-07-30 Chipmos Technologies Inc. Flip chip quad flat non-leaded package structure and manufacturing method thereof and chip package structure
JP5007250B2 (ja) 2008-02-14 2012-08-22 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP2009283503A (ja) * 2008-05-19 2009-12-03 Panasonic Corp 半導体装置及びその製造方法
US7968460B2 (en) * 2008-06-19 2011-06-28 Micron Technology, Inc. Semiconductor with through-substrate interconnect
JP5356742B2 (ja) * 2008-07-10 2013-12-04 ラピスセミコンダクタ株式会社 半導体装置、半導体装置の製造方法および半導体パッケージの製造方法
TWI373109B (en) * 2008-08-06 2012-09-21 Unimicron Technology Corp Package structure
US8017515B2 (en) * 2008-12-10 2011-09-13 Stats Chippac, Ltd. Semiconductor device and method of forming compliant polymer layer between UBM and conformal dielectric layer/RDL for stress relief
JP5330863B2 (ja) * 2009-03-04 2013-10-30 パナソニック株式会社 半導体装置の製造方法
JP5172751B2 (ja) * 2009-03-19 2013-03-27 株式会社東芝 三次元積層型半導体集積回路の製造方法
JP5136515B2 (ja) * 2009-05-27 2013-02-06 ソニー株式会社 固体撮像装置
DE102009035437B4 (de) * 2009-07-31 2012-09-27 Globalfoundries Dresden Module One Llc & Co. Kg Halbleiterbauelement mit einem Verspannungspuffermaterial, das über einem Metallisierungssystem mit kleinem ε gebildet ist
TW201106453A (en) * 2009-08-10 2011-02-16 Unimicron Technology Corp Package substrate having embedded semiconductor chip
DE102010038933A1 (de) * 2009-08-18 2011-02-24 Denso Corporation, Kariya-City Halbleitervorrichtung mit Halbleiterchip und Metallplatte und Verfahren zu deren Fertigung
TWI405321B (zh) * 2009-09-08 2013-08-11 財團法人工業技術研究院 三維多層堆疊半導體結構及其製造方法
TW201110285A (en) * 2009-09-08 2011-03-16 Unimicron Technology Corp Package structure having embedded semiconductor element and method of forming the same
JP2011082450A (ja) * 2009-10-09 2011-04-21 Elpida Memory Inc 半導体装置及びこれを備える情報処理システム
JP5532394B2 (ja) * 2009-10-15 2014-06-25 セイコーエプソン株式会社 半導体装置及び回路基板並びに電子機器
TWI436463B (zh) * 2009-12-31 2014-05-01 日月光半導體製造股份有限公司 半導體封裝結構及其製造方法
TWI412114B (zh) * 2009-12-31 2013-10-11 日月光半導體製造股份有限公司 半導體封裝結構及其製造方法
TWI525758B (zh) * 2010-01-21 2016-03-11 精材科技股份有限公司 晶片封裝體及其製造方法
US8294261B2 (en) * 2010-01-29 2012-10-23 Texas Instruments Incorporated Protruding TSV tips for enhanced heat dissipation for IC devices
US8692382B2 (en) * 2010-03-11 2014-04-08 Yu-Lin Yen Chip package
TWI505428B (zh) * 2010-03-11 2015-10-21 精材科技股份有限公司 晶片封裝體及其形成方法
US8507940B2 (en) * 2010-04-05 2013-08-13 Taiwan Semiconductor Manufacturing Company, Ltd. Heat dissipation by through silicon plugs
US8338939B2 (en) * 2010-07-12 2012-12-25 Taiwan Semiconductor Manufacturing Company, Ltd. TSV formation processes using TSV-last approach
US8643070B2 (en) * 2010-12-08 2014-02-04 Shu-Ming Chang Chip package and method for forming the same
US20120168935A1 (en) * 2011-01-03 2012-07-05 Nanya Technology Corp. Integrated circuit device and method for preparing the same
US8742564B2 (en) * 2011-01-17 2014-06-03 Bai-Yao Lou Chip package and method for forming the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20160124999A (ko) * 2015-04-20 2016-10-31 주식회사 아이센스 유체 밀봉 저장백
KR101714735B1 (ko) * 2015-04-20 2017-03-10 주식회사 아이센스 유체 밀봉 저장백

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CN102593094A (zh) 2012-07-18
US8742564B2 (en) 2014-06-03
US9293394B2 (en) 2016-03-22
CN102593094B (zh) 2015-09-23
TWI581390B (zh) 2017-05-01
TW201232727A (en) 2012-08-01
US20120181672A1 (en) 2012-07-19
US20140231966A1 (en) 2014-08-21

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