TW201232727A - Chip package and method for forming the same - Google Patents

Chip package and method for forming the same Download PDF

Info

Publication number
TW201232727A
TW201232727A TW101101674A TW101101674A TW201232727A TW 201232727 A TW201232727 A TW 201232727A TW 101101674 A TW101101674 A TW 101101674A TW 101101674 A TW101101674 A TW 101101674A TW 201232727 A TW201232727 A TW 201232727A
Authority
TW
Taiwan
Prior art keywords
conductive
layer
forming
chip package
hole
Prior art date
Application number
TW101101674A
Other languages
Chinese (zh)
Other versions
TWI581390B (en
Inventor
Bai-Yao Lou
Tsang-Yu Liu
Chia-Sheng Lin
Tzu-Hsiang Hung
Original Assignee
Xintec Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Xintec Inc filed Critical Xintec Inc
Publication of TW201232727A publication Critical patent/TW201232727A/en
Application granted granted Critical
Publication of TWI581390B publication Critical patent/TWI581390B/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02371—Disposition of the redistribution layers connecting the bonding area on a surface of the semiconductor or solid-state body with another surface of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02372—Disposition of the redistribution layers connecting to a via connection in the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/039—Methods of manufacturing bonding areas involving a specific sequence of method steps
    • H01L2224/0392—Methods of manufacturing bonding areas involving a specific sequence of method steps specifically adapted to include a probing step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04026—Bonding areas specifically adapted for layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05025—Disposition the internal layer being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05541—Structure
    • H01L2224/05548—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/05686—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2224/05687—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/0569—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/06181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13022—Disposition the bump connector being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13024—Disposition the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/731—Location prior to the connecting process
    • H01L2224/73151—Location prior to the connecting process on different surfaces
    • H01L2224/73153—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00013—Fully indexed content
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/146—Mixed devices
    • H01L2924/1461—MEMS

Abstract

An embodiment of the invention provides a chip package which includes a substrate having a first surface and a second surface; a conducting pad structure located on the first surface; a dielectric layer located on the first surface of the substrate, wherein the dielectric layer has an opening exposing a portion of the conducting pad structure; and a cap layer located on the dielectric layer and extends into the opening.

Description

201232727 六、發明說明： 【發明所屬之技術領域】 本發明係有關於晶片封裝體，且特別是有關於具穿基 底導電結構之晶片封裝體。 【先前技術】 晶片封裝製程是形成電子產品過程中之一重要步驟。 晶片封裝體除了將晶片保護於其中，使免受外界環境污染 外，還提供晶片内部電子元件與外界之電性連接通路。 晶片在封裝之前，需進行針測步驟以確保品質。然而， 針測步驟可能造成後續封裝製程上的困難，且容易於晶片 封裝體中留下或產生缺陷。 提高晶片封裝體之可靠度與結構穩定性已成為重要課 題。 【發明内容】 本發明一實施例提供一種晶片封裝體，包括：一基底， 具有一第一表面及一第二表面；一導電墊結構’位於該基 底之該第一表面上；一介電層，位於該基底之該第一表面 與該導電墊結構之上，其中該介電層具有一開口，露出部 分的該導電墊結構；以及一覆蓋層，位於該介電層之上， 且填入該開口。 本發明一實施例提供一種晶片封裝體的形成方法，包 括：提供一基底，具有一第一表面及一第二表面，其中該 第一表面上設置有一導電墊結構及一介電層，該介電層位201232727 VI. Description of the Invention: [Technical Field] The present invention relates to a chip package, and more particularly to a chip package having a substrate conductive structure. [Prior Art] The wafer packaging process is an important step in the process of forming an electronic product. In addition to protecting the wafer from the external environment, the chip package also provides an electrical connection path between the electronic components inside the wafer and the outside. Before the wafer is packaged, a needle test step is required to ensure quality. However, the pinning step may cause difficulties in subsequent packaging processes and may be prone to defects or defects in the wafer package. Improving the reliability and structural stability of chip packages has become an important issue. SUMMARY OF THE INVENTION An embodiment of the present invention provides a chip package including: a substrate having a first surface and a second surface; a conductive pad structure 'on the first surface of the substrate; a dielectric layer Located on the first surface of the substrate and the conductive pad structure, wherein the dielectric layer has an opening to expose a portion of the conductive pad structure; and a cover layer over the dielectric layer and filled in The opening. An embodiment of the invention provides a method for forming a chip package, comprising: providing a substrate having a first surface and a second surface, wherein the first surface is provided with a conductive pad structure and a dielectric layer, Electrical layer

S 3 Χ11Ό01 9002^A35856TWF/chlaulln 201232727 於該導電墊結構之上，且具有一開口，露出部分的該導電 墊結構；以及於該介電層上形成一覆蓋層，其中該覆蓋層 填入該開口。 【實施方式】 以下將詳細忒明本發明實施例之製作與使用方式。然 應注意的是，本發明提供許多可供應用的發明概念，其可 以多種特定型式貫施。文中所舉例討論之特定實施例僅為 製造與使用本發明之特定方式，非用以限制本發明之範 圍。此外，在不同實施例中可能使用重複的標號或標示。 這些重複僅為了簡單清楚地敘述本發明，不代表所討論之 不同實施例及/或結構之間必然具有任何關連性。再者，當 述及一第一材料層位於一第二材料層上或之上時，包括第 一材料層與第二材料層直接接觸或間隔有一或更多其他材 料層之情形。 本發明一實施例之晶片封裝體可用以封裝各種晶片。 例如，其可用於封裝各種包含主動元件或被動元件（active or passive elements)、數位電路或類比電路（digital or analog circuits)等積體電路的電子元件（electronic components)，例 如是有關於光電元件（opto electronic devices)、微機電系統 (Micro Electro Mechanical System; MEMS)、微流體系統 (micro fluidic systems)、或利用熱、光線及壓力等物理量變 化來測量的物理感測器（Physical Sensor)。特別是可選擇使 用晶圓級封裝（wafer scale package; WSP)製程對影像感測 元件、發光二極體（light-emitting diodes; LEDs)、太陽能電 Χ11Ό01_90〇2Ά35 856TWF/chiaulin 201232727 池（solar cells)、射頻元件（RF circuits)、加速計 (accelerators)、陀螺儀（gyroscopes)、微制動器（micro actuators)、表面聲波元件（surface acoustic wave devices)、 壓力感測器（process sensors)喷墨頭（ink printer heads)、或功 率晶片（powerIC)等半導體晶片進行封裝。 其中上述晶圓級封裝製程主要係指在晶圓階段完成封 裝步驟後，再予以切割成獨立的封裝體，然而，在一特定 實施例中，例如將已分離之半導體晶片重新分布在一承載 晶圓上，再進行封裝製程，亦可稱之為晶圓級封裝製程。 另外，上述晶圓級封裝製程亦適用於藉堆疊（stack)方式安 排具有積體電路之多片晶圓，以形成多層積體電路 (multi-layer integrated circuit devices)之晶片封裝體。 ^圖顯示本案發明人所知之―晶片㈣體的剖面 圖。基底U)上設置有介電層12及導電塾結構14。導電塾 結構Η電性連接基底1G中之4件(未顯示）。導電塾結 構14可包括複數個$ ^ $ 使广1Λ7, 隹且電墊，例如14a、14b、及14。 基底1〇例如是梦晶圓，其在 前，通常需進行針測。通當，^後、，切㈣封裝製程之 、 紂』通$需移除部分的介電声12以带 成開口 13 ’而使導電墊結構14 曰 y 接著，可以探針接觸露出的導 層導電塾14a露出。 性量測。探針通常會損壞部 :，亚進行所需之電 刻痕叩，造成導電塾14a之強度⑽留下凹陷（或 在針測步驟之後，可針對二降。 封裝製程。例如，可自基底1〇 k針測之部分進行後續的 10以形成朝表面10b延伸之=表面10&移除部分的基底 /同16。在後續製程中，可於 a：S3 Χ11Ό01 9002^A35856TWF/chlaulln 201232727 is above the conductive pad structure and has an opening to expose a portion of the conductive pad structure; and forming a cover layer on the dielectric layer, wherein the cover layer fills the opening . [Embodiment] Hereinafter, the production and use of the embodiments of the present invention will be described in detail. It should be noted, however, that the present invention provides many inventive concepts that can be applied in a variety of specific forms. The specific embodiments discussed herein are merely illustrative of specific ways of making and using the invention, and are not intended to limit the scope of the invention. Moreover, repeated numbers or labels may be used in different embodiments. These repetitions are only for the purpose of simplicity and clarity of the invention and are not necessarily to be construed as a limitation of the various embodiments and/or structures discussed. Furthermore, when a first material layer is on or above a second material layer, it includes the case where the first material layer is in direct contact with or separated from the second material layer by one or more other material layers. The chip package of one embodiment of the present invention can be used to package various wafers. For example, it can be used to package various electronic components including integrated circuits such as active or passive elements, digital circuits or digital circuits, for example, related to photovoltaic elements ( Opto electronic devices), Micro Electro Mechanical Systems (MEMS), micro fluidic systems, or physical sensors that measure physical quantities such as heat, light, and pressure. In particular, you can choose wafer-level package (WSP) process for image sensing components, light-emitting diodes (LEDs), solar cells 11Ό01_90〇2Ά35 856TWF/chiaulin 201232727 pool (solar cells) , RF circuits, accelerators, gyroscopes, micro actuators, surface acoustic wave devices, process sensors, inkjet heads A semiconductor wafer such as a printer heads or a power chip is packaged. The above wafer level packaging process mainly refers to cutting into a separate package after the packaging step is completed in the wafer stage. However, in a specific embodiment, for example, the separated semiconductor wafer is redistributed in a supporting crystal. On the circle, the encapsulation process can also be called a wafer level packaging process. In addition, the above wafer level packaging process is also suitable for stacking a plurality of wafers having integrated circuits by stacking to form a chip package of multi-layer integrated circuit devices. The figure shows a cross-sectional view of the wafer (four) body known to the inventors of the present invention. A dielectric layer 12 and a conductive germanium structure 14 are disposed on the substrate U). The conductive 塾 structure is electrically connected to four of the substrates 1G (not shown). Conductive germanium structure 14 can include a plurality of $^$ to make a wide array of pads, such as 14a, 14b, and 14. The substrate 1 is, for example, a dream wafer, which is usually preceded by a needle test. Passing, ^,,, cutting (4) packaging process, 需 通 $ need to remove part of the dielectric sound 12 to bring into the opening 13 ' and make the conductive pad structure 14 曰 y, then the probe can contact the exposed conductive layer The conductive crucible 14a is exposed. Sex measurement. The probe usually damages the part: the sub-decision of the desired electrical nick, causing the strength (10) of the conductive crucible 14a to leave a recess (or after the pinning step, the second drop can be made. The encapsulation process. For example, from the substrate 1 The portion of the 〇k needle is subjected to the subsequent 10 to form the surface 10 & the portion of the removed portion that extends toward the surface 10b. In the subsequent process, a:

XllO〇]_9〇〇2-A35856TV\T/chiaulin 201232727 孔洞16中形成與導電墊結構14電性連接之穿基底導電結 構。然而，由於導電塾結構14已受破壞，且其厚度較薄， 容易於後續製程中（例如’孔洞16的形成過程中）破裂而造 成晶片失效。此外’介電層12與導電墊結構η之間的階 梯結構容易使後續接合製程中產生氣泡17，影響晶片封裝 體之可靠度。 為了改善上述發明人所發現之問題，提出實施例如 下。第2圖顯示根據本發明一實施例之晶片封裝體的剖面 圖，用以敘述晶片封裝體的形成過程。在一實施例中，提 供基底100 ’其具有表面l〇〇a及表面l〇〇b。基底1〇〇包括 半導體基底，如矽晶圓。在基底1〇〇之表面l〇〇a上設置有 導電墊結構104及介電層1〇2。介電層1〇2位於導電墊結 構104之上，且具有開口 1〇3。開口 1〇3露出部分的導電 塾結構104。基底100中可形成有元件區（未顯示），其電性 連接導電墊結構104。在一實施例中，導電墊結構1〇4可 包括堆疊的複數個導電墊，例如包括（但不限於）最上層導 電墊104a、最下層導電墊l〇4c、及導電墊104a與104c之 間的中間導電墊l〇4b。 接著，可選擇性對基底100進行針測。例如，可以探 針（未顯示）接觸露出的導電墊104a，並進行所需之電性量 測。探針通常會損壞部分的導電墊104a而留下凹陷（或刻 痕）105 。 在進行後續形成穿基底導電結構之製程之前，於介電 層上形成覆蓋層107。覆蓋層107進一步填入介電層 丄〇2之開口 1〇3中。在一實施例中，覆蓋層1〇7可大抵填 6 Xll-001_9002-A35856TWF/chiaulln 201232727 滿開口 103’可避免後續接合步驟中產生氣泡。在一實施 例中’覆蓋層106直接接觸導電墊結構1〇4。例如，在第2 圖實施例中，覆蓋層106直接接觸導電墊i〇4c之下表面。 此外，覆蓋層1〇7還可支撐導電墊結構1〇4，確保導電塾 結構104不於後續晶片封裝製程中或晶片封裝體成品的使 用過程中破裂。 在—實施例中，覆蓋層107之厚度可大於導電墊結構 104中任—導電墊(例如，導電墊104a、104b、及i〇4c其 中之一）之厚度。在一實施例中，覆蓋層1〇7之材質不同二 導電墊結構1〇4。在一實施例中，覆蓋層1〇7之材質包括 一金屬材料、一陶瓷材料、一高分子材料、或前述之組合。 接著，可選擇性於基底100之表面1〇〇b上接合承載基 板114,其與基底100之間可選擇性夾有間隔層丨^。由ς 已預先形成有覆蓋層1G7，因此接合承载基板114的步驟 中，大抵不會形成氣泡，可提升晶片封裴體的可靠度。 接著’可選擇性以承載基板114為支撐，對基^ 1〇〇 之表面100a進行薄化製程。接著，可利如透過(但不限於) 微影及触刻製程自基底1GG之表面1QGa移除部分的基底 100以形成朝表面100b延伸之孔洞106。 接著’可於孔洞106之側壁上形成絕緣層1〇8。所形 成絕緣層108通常會覆蓋位於孔洞106底部上之導電墊么士 構1〇4。因此，可進一步移除孔洞106底部上之絕緣層1〇°8 以使部分的導電塾結構H)4露出。例如，使導電墊购露 出。由於已預先形成覆蓋層1〇7,因此在孔洞1〇6的形成 過程中’導電墊結構Π)4可獲充分的切而確保大抵不受X11O〇]_9〇〇2-A35856TV\T/chiaulin 201232727 The hole 16 is formed with a through-substrate conductive structure electrically connected to the conductive pad structure 14. However, since the conductive germanium structure 14 has been damaged and its thickness is thin, it is easy to break in subsequent processes (e.g., during the formation of the holes 16) to cause wafer failure. In addition, the step structure between the dielectric layer 12 and the conductive pad structure η easily causes the bubbles 17 to be generated in the subsequent bonding process, which affects the reliability of the chip package. In order to improve the problems discovered by the inventors mentioned above, it is proposed to implement the following. Fig. 2 is a cross-sectional view showing a wafer package according to an embodiment of the present invention for describing a process of forming a chip package. In one embodiment, substrate 100' is provided having a surface 10a and a surface 10b. The substrate 1 includes a semiconductor substrate such as a germanium wafer. A conductive pad structure 104 and a dielectric layer 1〇2 are disposed on the surface 10a of the substrate. The dielectric layer 1〇2 is located above the conductive pad structure 104 and has an opening 1〇3. The opening 1 〇 3 exposes a portion of the conductive raft structure 104. An element region (not shown) may be formed in the substrate 100 electrically connected to the conductive pad structure 104. In an embodiment, the conductive pad structure 1 4 may include a plurality of stacked conductive pads, including, but not limited to, an uppermost conductive pad 104a, a lowermost conductive pad 104c, and conductive pads 104a and 104c. The middle conductive pad l〇4b. Next, the substrate 100 can be selectively needled. For example, a probe (not shown) can be contacted with the exposed conductive pad 104a and the desired electrical measurement can be made. The probe typically damages a portion of the conductive pad 104a leaving a recess (or score) 105. A cap layer 107 is formed on the dielectric layer prior to the subsequent process of forming the through-substrate conductive structure. The cover layer 107 is further filled in the opening 1〇3 of the dielectric layer 丄〇2. In one embodiment, the cover layer 1〇7 can be overfilled with 6 Xll-001_9002-A35856TWF/chiaulln 201232727 full opening 103' to avoid air bubbles in subsequent bonding steps. In one embodiment, the cover layer 106 directly contacts the conductive pad structure 1〇4. For example, in the embodiment of Figure 2, the cover layer 106 directly contacts the lower surface of the conductive pad i〇4c. In addition, the cap layer 1〇7 can also support the conductive pad structure 1〇4 to ensure that the conductive germanium structure 104 is not broken during subsequent wafer packaging processes or during use of the finished wafer package. In an embodiment, the thickness of the cap layer 107 can be greater than the thickness of any of the conductive pads (e.g., one of the conductive pads 104a, 104b, and i〇4c) in the conductive pad structure 104. In one embodiment, the material of the cover layer 1〇7 is different from the two conductive pad structures 1〇4. In one embodiment, the material of the cover layer 1〇7 comprises a metal material, a ceramic material, a polymer material, or a combination thereof. Next, the carrier substrate 114 may be selectively bonded to the surface 1b of the substrate 100, and a spacer layer may be selectively interposed between the substrate 100 and the substrate 100. Since the cover layer 1G7 has been formed in advance, in the step of bonding the carrier substrate 114, bubbles are not formed, and the reliability of the wafer package can be improved. Then, the substrate 100 is selectively supported by the carrier substrate 114 to thin the surface 100a of the substrate. Next, a portion of the substrate 100 may be removed from the surface 1QGa of the substrate 1GG by, for example, but not limited to, lithography and lithography to form a hole 106 extending toward the surface 100b. Then, an insulating layer 1 〇 8 may be formed on the sidewall of the hole 106. The insulating layer 108 is formed to cover the conductive pads 〇1 〇 4 on the bottom of the hole 106. Therefore, the insulating layer 1 〇 8 on the bottom of the hole 106 can be further removed to expose a portion of the conductive 塾 structure H) 4 . For example, make a conductive pad available. Since the cover layer 1〇7 has been formed in advance, the 'conductive pad structure Π4' can be sufficiently cut during the formation of the holes 1〇6 to ensure that it is largely unaffected

XllO01_9002-A35856TWF/chiaulin 7 201232727 損傷。 接著’可於孔洞106之側壁上的絕緣層i〇8上形成導 電層110。導電層110可電性接觸導電墊結構104。在第2 圖之實施例中’導電層110可直接接觸導電墊l〇4c。在一 實施例中’導電層110可延伸至基底100a上之絕緣層1〇8 之上。 接著，可選擇性於基底1〇〇之表面l〇〇a上形成保護層 116。保護層116可具有露出導電層11〇之開口。接著，可 於保護層116之開口中形成導電凸塊Π8，並接著沿著預 定切割道（未顯示）切割基底1〇〇以形成至少一晶片封裝體。 第3圖顯示根據本發明另一實施例之晶片封裝體的剖 面圖，用以說明晶片封裝體的製程，其中相同或相似之標 號將用以標示相同或相似之元件。 第3圖實施例相似於第2圖實施例，主要差異在於所 形成之孔洞106進一步穿過導電塾i〇4c，並使最上層導電 墊l〇4a露出。在此情形下，後續形成之導電層11〇可與導 電塾104a直接接觸。然應注意的是，本發明實施例不限於 此。在另一實施例中，所形成之孔洞1 〇6可穿過導電塾 104c ’並使一中間導電墊(例如，104b)露出。在此情形下， 後續形成之導電層11〇可與導電墊104b直接接觸。孔洞 106之延伸程度（即’穿基底導電結構之延伸程度）端視所需 應用而定。 本發明實施例透過覆蓋層之設置，可有效提升晶片封 裝體的可靠度。 雖然本發明已以數個較佳實施例揭露如上，然其並非 8 Χ11-001_9002^Α35856ΊΛνΡ/ο1ιίαυ11ηXllO01_9002-A35856TWF/chiaulin 7 201232727 Damage. Next, a conductive layer 110 may be formed on the insulating layer i 8 on the sidewall of the hole 106. The conductive layer 110 can electrically contact the conductive pad structure 104. In the embodiment of Fig. 2, the conductive layer 110 can directly contact the conductive pads 10c. In one embodiment, the conductive layer 110 can extend over the insulating layer 1 〇 8 on the substrate 100a. Next, a protective layer 116 may be selectively formed on the surface 10a of the substrate. The protective layer 116 may have an opening that exposes the conductive layer 11''. Next, a conductive bump 8 can be formed in the opening of the protective layer 116, and then the substrate 1 can be cut along a predetermined scribe line (not shown) to form at least one chip package. Figure 3 is a cross-sectional view of a chip package in accordance with another embodiment of the present invention for illustrating the process of the chip package, wherein the same or similar reference numerals will be used to designate the same or similar elements. The embodiment of Fig. 3 is similar to the embodiment of Fig. 2, the main difference being that the formed holes 106 further pass through the conductive electrodes 4c and expose the uppermost conductive pads 10a. In this case, the subsequently formed conductive layer 11A can be in direct contact with the conductive pad 104a. It should be noted, however, that the embodiments of the present invention are not limited thereto. In another embodiment, the formed holes 1 〇 6 can pass through the conductive turns 104c' and expose an intermediate conductive pad (e.g., 104b). In this case, the subsequently formed conductive layer 11A can be in direct contact with the conductive pad 104b. The extent to which the holes 106 extend (i.e., the extent to which the substrate conductive structure extends) depends on the desired application. In the embodiment of the invention, the reliability of the wafer package can be effectively improved by the arrangement of the cover layer. Although the present invention has been disclosed above in several preferred embodiments, it is not 8 Χ11-001_9002^Α35856ΊΛνΡ/ο1ιίαυ11η

S 201232727 用以限定本發明，任何所屬技術領域中具有通常知識者， 在不脫離本發明之精神和範圍内，當可作任意之更動與潤 飾，因此本發明之保護範圍當視後附之申請專利範圍所界 定者為準。S 201232727 is used to define the present invention, and any one of ordinary skill in the art can make any changes and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention is attached to the application. The scope defined by the patent scope shall prevail.

S 9 Χ11Ό0] 9002^A35856TWF/chiaulin 201232727 【圖式簡單說明】 第1圖顯示本案發明人所知之一晶片封裝體的剖面 圖。 第2圖顯示根據本發明一實施例之晶片封裝體的剖面 圖。 第3圖顯示根據本發明一實施例之晶片封裝體的剖面 圖。 【主要元件符號說明】 10〜基底， 10a、10b〜表面； 12〜介電層； 13〜開口， 14〜導電墊結構； 14a、14b、14c〜導電墊； 15〜凹陷； 16〜孔洞； 17〜氣泡； 100〜基底； 100a、100b〜表面； 102〜介電層； 103〜開口； 104〜導電塾結構， 104a、104b、104c〜導電墊； 105〜凹陷； 10 Χ11,001_9002'Α35856Τ\νΡ/(：Ηΐ3ΐι11η 201232727 106〜孔洞 ; 107〜 〃覆蓋層； 108- 絕緣 層； HO- /導電 層； 112〜間隔 層； 114- 〃基板 j 116- 〃保護 層； 118- y導電 凸塊。S 9 Χ11Ό0] 9002^A35856TWF/chiaulin 201232727 [Simplified Schematic Description] Fig. 1 shows a cross-sectional view of a chip package known to the inventors of the present invention. Figure 2 is a cross-sectional view showing a chip package in accordance with an embodiment of the present invention. Figure 3 is a cross-sectional view showing a chip package in accordance with an embodiment of the present invention. [Main component symbol description] 10~substrate, 10a, 10b~surface; 12~ dielectric layer; 13~open, 14~ conductive pad structure; 14a, 14b, 14c~ conductive pad; 15~ recessed; 16~ hole; ~ bubble; 100~ substrate; 100a, 100b~ surface; 102~ dielectric layer; 103~ opening; 104~ conductive germanium structure, 104a, 104b, 104c~ conductive pad; 105~ recess; 10 Χ11,001_9002'Α35856Τ\νΡ /(:Ηΐ3ΐι11η 201232727 106~ hole; 107~ 〃 cover layer; 108- insulating layer; HO-/conductive layer; 112~ spacer layer; 114- 〃 substrate j 116- 〃 protective layer; 118- y conductive bump.

S Π Χ11Ό01 9002-A35856TWF/chlaulinS Π Χ11Ό01 9002-A35856TWF/chlaulin

Claims (1)

201232727 七、申請專利範圍·· L 一種晶片封裝體，包括： 一基底，具有一第一表面及一第二表面； 一導電墊結構，位於該基底之該第一表面上； 二電層，位於該基底之該第—表面與該導電塾 ^以及中該介電層具有―開"，露出部分的該導電^結 一覆蓋層，位於該介電層之上，且填入該開口。 2」如申請專利範圍第1項所述之晶片封裝體’更包括： 且dr〔，自該基底之該第二表面朝該第-表面延伸， 且路出邛分的該導電墊結構； 一絕緣層，位於該孔洞之一側壁之上；以及 =電層’位於該孔洞之該側壁上的該絕緣層之上， ，、中W導電層電性接觸該導電墊結構。 3如中請專利範圍第2項所述之晶片封裝體， 導電墊結構包括堆疊的複數個導㈣。 、“ 接接觸該最下層導電墊。"^層¥且該導電層直 孔洞5至&㈣3項所f之晶片縣體，其中該 層直接接觸該=之;電墊’且該導電 電塾位於該最；Π塾中之一中間導電塾’其中該中間導 墊之間。μ下a ¥電墊與該些導電墊中之一最上層導電 6.如申請專利範圍第3項所述之晶片封裝體，其中該 XlI，0〇L9002-A35836TWF/chiaulin 12 201232727 =少穿過該些導電墊中之—最下層導電墊 層直接接觸該些導電塾中之-最上層導電墊。 7抵如申請專利範圍第3項所述之晶 ^層之-厚度大於該些導轉中之任—導電塾二厚亥 度。 ’子 =如中請專利範鮮丨項所述之晶片封裝體，其中該 二c括一金屬材料、-陶究材料、-高分子材 料、或則述之組合。 ”二如申請專利範圍第1項所述之晶片封裝體，其中該 θ之㈣不同於該導電墊結構之材質。 兮申請專利範圍第1項所述之晶片封裝體，其中 6亥覆盘層直接接觸該導電墊結構。 該導專利範圍第10項所述之晶片封裝體’其中 私、、，口構具有一凹陷，且該覆蓋層填入該凹陷。 =· -種晶片封襄體的形成方法，包括： 第共一基底’具有-第-表面及-第二表面，其中該 於上设置有一導電墊結構及-介電層，該介電居位 墊結構；以及 且具有—開口，露出部分的該導電 口。於‘電層上形成一覆蓋層’其中該覆蓋層填入該開 方法';==圍第12項所述之晶片封裝體的形成 其中在形成该覆蓋層之後，更包括： 第4=::==移除部分的該基底以形成朝該 洞’該孔洞露出部分的該導電墊結構，· 13 XHO01_9002-A35856TWF/chiauIin S 201232727 於該孔洞之一側壁上形成一絕緣層；以及 於該孔洞之該側壁上之該絕緣層上形成—導電層，盆 中該導電層電性接觸該導電墊結構。 g八 14^申請專利範圍第13項所述之晶片料體的形成 方法’八中該導電塾結構包括堆疊的複數個導電塾。 方/it中請專利範圍第14項所述之晶片封I體的形成 方法，”中該孔洞露出該些導電墊中之一最下層導電塾， 且該導電層直接接觸該最下層導電墊。 曰 n中請專利範圍第14項所述之晶片封裝體的形成 方法，八中形成該孔洞的步驟包括移除部分的該導電塾社 構而使該孔洞至少穿過該些導電塾中之一最下層導電塾 並使該些導電塾中之一中間導電塾露出，其中ς中 墊位於該最下層導電塾與該些導電财之最上層導電塾: 間。 π·如中請專利範圍第14項所述之晶片料體的形成 方法’八中形成該孔洞的步驟包括移除部分的該導電塾么士 構而使該孔洞至少穿過該些導電墊中之—最下 ° 並使該些導電墊中之一最上層導電墊露出。日 n申請專利範圍第14項所述之晶片封裝體的形成 方中其中該覆蓋層之—厚度大於該 -導電墊之-厚度。 之任 方/it申請專利範圍第12項所述之晶片封裝體的形成 方法，，、中该覆盍層直接接觸該導電墊結構。 方法專利範’12項所述之晶片封裝體的形成 /，、中4覆盖層之材質包括—金屬材料、—陶究材料、 XllO01_9002-A35856TWF/chiaulin 201232727 一高分子材料、或前述之組合。 15 Xl]-0〇]_9002-A35856TWF/chiaulin s201232727 VII. Patent Application Range·· L A chip package comprising: a substrate having a first surface and a second surface; a conductive pad structure on the first surface of the substrate; The first surface of the substrate and the conductive layer and the dielectric layer have an "open", and the exposed portion of the conductive layer is overlying the dielectric layer and filling the opening. 2) The chip package as described in claim 1 further comprising: and dr[, the conductive pad structure extending from the second surface of the substrate toward the first surface and passing away; An insulating layer is disposed on a sidewall of the hole; and an electric layer is disposed on the insulating layer on the sidewall of the hole, and the W conductive layer electrically contacts the conductive pad structure. 3. The chip package of claim 2, wherein the conductive pad structure comprises a plurality of stacked conductors (four). , "contacting the lowermost conductive pad. " ^ layer ¥ and the conductive layer straight hole 5 to & (4) 3 of the wafer county, wherein the layer directly contacts the =; the electric pad 'and the conductive The crucible is located at the most; one of the crucibles is intermediate between the intermediate conductive pads Between the intermediate pads, and the uppermost layer of the conductive pads is electrically conductive as described in item 3 of claim 3 The chip package, wherein the XlI, 0〇L9002-A35836TWF/chiaulin 12 201232727 = less through the conductive pads - the lowermost conductive pad directly contacts the uppermost conductive pads of the conductive pads. The thickness of the crystal layer as described in item 3 of the patent application is greater than the thickness of the conductive layer 塾 厚 厚 ' ' ' ' ' ' = = = = = = = = = = = = = = = = = = = = = = = = = The second package includes a metal material, a ceramic material, a polymer material, or a combination thereof. The chip package according to claim 1, wherein the (four) of the θ is different from the conductive The material of the pad structure. The chip package of claim 1, wherein the 6-layer disk layer directly contacts the conductive pad structure. The chip package of the invention of claim 10, wherein the private, and the mouth structure has a recess, and the cover layer fills the recess. a method for forming a wafer package body, comprising: a first substrate having a first surface and a second surface, wherein the conductive pad structure and the dielectric layer are disposed thereon, the dielectric location a pad structure; and having an opening to expose the portion of the conductive port. Forming a capping layer on the 'electric layer', wherein the capping layer is filled with the opening method; == forming of the chip package according to item 12, wherein after forming the capping layer, the method further comprises: 4=: :== removing part of the substrate to form the conductive pad structure toward the hole 'exposed portion of the hole, 13 XHO01_9002-A35856TWF/chiauIin S 201232727 forming an insulating layer on one side wall of the hole; and the hole A conductive layer is formed on the insulating layer on the sidewall, and the conductive layer electrically contacts the conductive pad structure in the basin. G8 14^ The method of forming a wafer body as described in claim 13 of the invention, wherein the conductive crucible structure comprises a plurality of stacked conductive crucibles. The method for forming a wafer package body according to claim 14, wherein the hole exposes one of the conductive pads of the conductive pads, and the conductive layer directly contacts the lowermost conductive pad. The method for forming a chip package according to claim 14, wherein the step of forming the hole includes removing a portion of the conductive germanium structure such that the hole passes through at least one of the conductive turns. The lowermost conductive ytterbium exposes one of the conductive rafts, wherein the middle ridge is located between the lowermost conductive ridge and the uppermost conductive 塾 of the conductive 。: π· The method for forming the wafer body described in the method of forming the hole includes removing a portion of the conductive scorpion structure such that the hole passes through at least a portion of the conductive pads - and One of the uppermost conductive pads of the conductive pad is exposed. In the formation of the chip package described in claim 14, wherein the thickness of the cover layer is greater than the thickness of the conductive pad. Article 12 of the scope of patent application The method for forming a chip package, wherein the cover layer directly contacts the conductive pad structure. The method for forming a chip package according to the method of claim 12, and the material of the middle cover layer comprises: a metal material, - ceramic materials, XllO01_9002-A35856TWF/chiaulin 201232727 a polymer material, or a combination of the foregoing. 15 Xl]-0〇]_9002-A35856TWF/chiaulin s
TW101101674A 2011-01-17 2012-01-17 Chip package and method for forming the same TWI581390B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US201161433379P 2011-01-17 2011-01-17

Publications (2)

Publication Number Publication Date
TW201232727A true TW201232727A (en) 2012-08-01
TWI581390B TWI581390B (en) 2017-05-01

Family

ID=46481544

Family Applications (1)

Application Number Title Priority Date Filing Date
TW101101674A TWI581390B (en) 2011-01-17 2012-01-17 Chip package and method for forming the same

Country Status (4)

Country Link
US (2) US8742564B2 (en)
JP (1) JP6017141B2 (en)
CN (1) CN102593094B (en)
TW (1) TWI581390B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI484607B (en) * 2013-01-11 2015-05-11 Xintec Inc Package structure and method for manufacturing thereof

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9711403B2 (en) * 2011-01-17 2017-07-18 Xintec Inc. Method for forming chip package
US8742564B2 (en) * 2011-01-17 2014-06-03 Bai-Yao Lou Chip package and method for forming the same
JP5958732B2 (en) * 2011-03-11 2016-08-02 ソニー株式会社 Semiconductor device, manufacturing method, and electronic apparatus
JP5754239B2 (en) 2011-05-24 2015-07-29 ソニー株式会社 Semiconductor device
TWI485818B (en) * 2011-06-16 2015-05-21 Xintec Inc Chip package and method for forming the same
US9006896B2 (en) * 2012-05-07 2015-04-14 Xintec Inc. Chip package and method for forming the same
TWI553841B (en) * 2013-01-31 2016-10-11 原相科技股份有限公司 Chip package and manufacturing method thereof
TWI525673B (en) 2013-10-08 2016-03-11 精材科技股份有限公司 Method of fabricating a wafer-level chip package
TWI550794B (en) * 2014-12-17 2016-09-21 精材科技股份有限公司 Chip package and method for forming the same
CN104576564A (en) * 2015-01-26 2015-04-29 华天科技（昆山）电子有限公司 Wafer level chip size packaging structure and manufacturing process thereof
KR101714735B1 (en) * 2015-04-20 2017-03-10 주식회사 아이센스 Sealing Fluid Saving Bag
CN109742064B (en) * 2015-04-27 2021-06-11 精材科技股份有限公司 Chip package and method for manufacturing the same
US10373883B2 (en) * 2017-10-26 2019-08-06 Advanced Semiconductor Engineering, Inc. Semiconductor package device and method of manufacturing the same
JP2020098849A (en) * 2018-12-18 2020-06-25 ソニーセミコンダクタソリューションズ株式会社 Semiconductor device
CN110620055B (en) * 2019-09-23 2021-06-25 九江市海纳电讯技术有限公司 Bonding method of RF (radio frequency) device
CN112735964B (en) * 2020-12-23 2023-12-22 武汉新芯集成电路制造有限公司 Wafer surface defect detection and surface repair method

Family Cites Families (41)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2849346B1 (en) * 2002-12-20 2006-12-08 Thales Sa SURFACE MOUNTING HYPERFREQUENCY HOUSING AND CORRESPONDING MOUNTING WITH A MULTILAYER CIRCUIT.
JP4248928B2 (en) * 2003-05-13 2009-04-02 ローム株式会社 Semiconductor chip manufacturing method, semiconductor device manufacturing method, semiconductor chip, and semiconductor device
JP2005109221A (en) * 2003-09-30 2005-04-21 Toshiba Corp Wafer-level package and its manufacturing method
US7091124B2 (en) * 2003-11-13 2006-08-15 Micron Technology, Inc. Methods for forming vias in microelectronic devices, and methods for packaging microelectronic devices
JP2006210438A (en) * 2005-01-25 2006-08-10 Nec Electronics Corp Semiconductor device and its manufacturing method
JP4311376B2 (en) * 2005-06-08 2009-08-12 セイコーエプソン株式会社 Semiconductor device, semiconductor device manufacturing method, electronic component, circuit board, and electronic apparatus
JP4745007B2 (en) * 2005-09-29 2011-08-10 三洋電機株式会社 Semiconductor device and manufacturing method thereof
JP5117698B2 (en) * 2006-09-27 2013-01-16 ルネサスエレクトロニクス株式会社 Semiconductor device
TWI370515B (en) * 2006-09-29 2012-08-11 Megica Corp Circuit component
US20080284041A1 (en) * 2007-05-18 2008-11-20 Samsung Electronics Co., Ltd. Semiconductor package with through silicon via and related method of fabrication
JP2009147218A (en) * 2007-12-17 2009-07-02 Toshiba Corp Semiconductor device, and method for manufacturing the same
CN101465299B (en) 2007-12-20 2011-06-15 南茂科技股份有限公司 Method for manufacturing grind used in encapsulation structure of chip reconfiguration
JP5259197B2 (en) * 2008-01-09 2013-08-07 ソニー株式会社 Semiconductor device and manufacturing method thereof
US20090189296A1 (en) * 2008-01-30 2009-07-30 Chipmos Technologies Inc. Flip chip quad flat non-leaded package structure and manufacturing method thereof and chip package structure
JP5007250B2 (en) * 2008-02-14 2012-08-22 ルネサスエレクトロニクス株式会社 Manufacturing method of semiconductor device
JP2009283503A (en) * 2008-05-19 2009-12-03 Panasonic Corp Semiconductor device and method for manufacturing the same
US7968460B2 (en) * 2008-06-19 2011-06-28 Micron Technology, Inc. Semiconductor with through-substrate interconnect
JP5356742B2 (en) * 2008-07-10 2013-12-04 ラピスセミコンダクタ株式会社 Semiconductor device, semiconductor device manufacturing method, and semiconductor package manufacturing method
TWI373109B (en) * 2008-08-06 2012-09-21 Unimicron Technology Corp Package structure
US8017515B2 (en) * 2008-12-10 2011-09-13 Stats Chippac, Ltd. Semiconductor device and method of forming compliant polymer layer between UBM and conformal dielectric layer/RDL for stress relief
JP5330863B2 (en) * 2009-03-04 2013-10-30 パナソニック株式会社 Manufacturing method of semiconductor device
JP5172751B2 (en) * 2009-03-19 2013-03-27 株式会社東芝 Manufacturing method of three-dimensional stacked semiconductor integrated circuit
JP5136515B2 (en) * 2009-05-27 2013-02-06 ソニー株式会社 Solid-state imaging device
DE102009035437B4 (en) * 2009-07-31 2012-09-27 Globalfoundries Dresden Module One Llc & Co. Kg A semiconductor device having a stress buffering material formed over a low ε metallization system
TW201106453A (en) * 2009-08-10 2011-02-16 Unimicron Technology Corp Package substrate having embedded semiconductor chip
DE102010038933A1 (en) * 2009-08-18 2011-02-24 Denso Corporation, Kariya-City Semiconductor chip and metal plate semiconductor device and method of manufacturing the same
TW201110285A (en) * 2009-09-08 2011-03-16 Unimicron Technology Corp Package structure having embedded semiconductor element and method of forming the same
TWI405321B (en) * 2009-09-08 2013-08-11 Ind Tech Res Inst 3d multi-wafer stacked semiconductor structure and method for manufacturing the same
JP2011082450A (en) * 2009-10-09 2011-04-21 Elpida Memory Inc Semiconductor device, and information processing system with the same
JP5532394B2 (en) * 2009-10-15 2014-06-25 セイコーエプソン株式会社 Semiconductor device, circuit board, and electronic equipment
TWI412114B (en) * 2009-12-31 2013-10-11 Advanced Semiconductor Eng Semiconductor package and method for making the same
TWI436463B (en) * 2009-12-31 2014-05-01 Advanced Semiconductor Eng Semiconductor package and method for making the same
US8564123B2 (en) * 2010-01-21 2013-10-22 Ching-Yu Ni Chip package and fabrication method thereof
US8294261B2 (en) * 2010-01-29 2012-10-23 Texas Instruments Incorporated Protruding TSV tips for enhanced heat dissipation for IC devices
TWI505428B (en) * 2010-03-11 2015-10-21 Xintec Inc Chip package and method for forming the same
US8692382B2 (en) * 2010-03-11 2014-04-08 Yu-Lin Yen Chip package
US8507940B2 (en) * 2010-04-05 2013-08-13 Taiwan Semiconductor Manufacturing Company, Ltd. Heat dissipation by through silicon plugs
US8338939B2 (en) * 2010-07-12 2012-12-25 Taiwan Semiconductor Manufacturing Company, Ltd. TSV formation processes using TSV-last approach
TWI500155B (en) * 2010-12-08 2015-09-11 Xintec Inc Chip package and method for forming the same
US20120168935A1 (en) * 2011-01-03 2012-07-05 Nanya Technology Corp. Integrated circuit device and method for preparing the same
US8742564B2 (en) * 2011-01-17 2014-06-03 Bai-Yao Lou Chip package and method for forming the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI484607B (en) * 2013-01-11 2015-05-11 Xintec Inc Package structure and method for manufacturing thereof

Also Published As

Publication number Publication date
JP2012151475A (en) 2012-08-09
US20120181672A1 (en) 2012-07-19
JP6017141B2 (en) 2016-10-26
US8742564B2 (en) 2014-06-03
CN102593094B (en) 2015-09-23
TWI581390B (en) 2017-05-01
CN102593094A (en) 2012-07-18
US20140231966A1 (en) 2014-08-21
US9293394B2 (en) 2016-03-22

Similar Documents

Publication Publication Date Title
TW201232727A (en) Chip package and method for forming the same
US9771259B2 (en) Method for fabricating electronic device package
TWI505428B (en) Chip package and method for forming the same
TWI512930B (en) Chip package and method for forming the same
TWI459485B (en) Method for forming chip package
TWI446512B (en) Chip package and method for forming the same
US9153707B2 (en) Chip package and method for forming the same
TWI529887B (en) Chip package and method for forming the same
TWI529905B (en) Chip package and method for forming the same
US9305843B2 (en) Chip package and method for forming the same
TWI493634B (en) Chip package and method for forming the same
TW201131710A (en) Chip package and fabrication method thereof
TWI578411B (en) Method for forming chip package
US9024437B2 (en) Chip package and method for forming the same
US9275958B2 (en) Chip package and method for forming the same
US8786093B2 (en) Chip package and method for forming the same
TW201232726A (en) Interposer and method for forming the same
US20120104445A1 (en) Chip package and method for forming the same
TWI545708B (en) Wafer stack structure and stack method thereof
TWI549202B (en) Chip package and method for forming the same