JP5985495B2 - コンタクトパッドおよびその製造方法 - Google Patents
コンタクトパッドおよびその製造方法 Download PDFInfo
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- JP5985495B2 JP5985495B2 JP2013538805A JP2013538805A JP5985495B2 JP 5985495 B2 JP5985495 B2 JP 5985495B2 JP 2013538805 A JP2013538805 A JP 2013538805A JP 2013538805 A JP2013538805 A JP 2013538805A JP 5985495 B2 JP5985495 B2 JP 5985495B2
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/1026—Compound semiconductors
- H01L2924/1032—III-V
- H01L2924/1033—Gallium nitride [GaN]
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- H—ELECTRICITY
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- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1203—Rectifying Diode
- H01L2924/12032—Schottky diode
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- H—ELECTRICITY
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- H01L2924/1301—Thyristor
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- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
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- Electrodes Of Semiconductors (AREA)
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- Physical Vapour Deposition (AREA)
Description
[0009]本明細書に組み込まれ一部を形成する添付した図面は、開示のいくつかの態様を図示するとともに、記載は、本開示の原理を説明するために役立つ。
Claims (15)
- 第1の表面を備えた半導体構造を用意するステップと、
前記第1の表面上の少なくとも1箇所の選択領域を露出させる開口部を有する除去可能なマスクを前記第1の表面上に形成するステップと、
前記第1の表面の少なくとも1箇所の選択領域上に接着層を設けるステップと、
蒸発プロセスを使用して前記接着層上に窒化チタンのバリア層を設けるステップであって、該蒸発プロセスが
前記半導体構造の周囲に真空を作り出すステップと、
前記接着層が設けられた後で、窒素及び不活性ガスの注入の間に窒化チタンの前記バリア層が接着層を覆って形成されるように、チタンを蒸発させ、前記チタンが蒸発するにつれて、前記真空中へと窒素及び不活性ガスの両方を注入するステップとを含む、バリア層を設けるステップと、
前記バリア層上にオーバーレイ層を設けるステップであって、コンタクトパッドが、前記接着層、前記バリア層、および前記オーバーレイ層を含む、オーバーレイ層を設けるステップと
を含む、方法。 - 前記バリア層が、窒化チタンから構成される、請求項1に記載の方法。
- 前記バリア層の少なくとも一部分の全体にわたって、チタンと窒素の比率が、前記バリア層内に勾配を付けた部分を設けるために実質的に連続して変化する、請求項1に記載の方法。
- 前記オーバーレイ層が、アルミニウムを含む、請求項1に記載の方法。
- 前記オーバーレイ層が、チタンを含む、請求項4に記載の方法。
- 前記オーバーレイ層が、アルミニウムから構成される、請求項1に記載の方法。
- 前記半導体構造が、前記コンタクトパッドを有するショットキーダイオードを形成するために使用され、前記接着層は、金属−半導体接合が前記接着層と前記第1の表面との接合部のところに形成されるようにショットキー層を設ける、請求項1に記載の方法。
- 前記半導体構造が、前記コンタクトパッドを有するショットキーダイオードを形成するために使用され、前記接着層は、金属−半導体接合が前記接着層と前記第1の表面との接合部のところに形成されるようにショットキー層を設ける、請求項1に記載の方法。
- 前記接着層、前記バリア層、および前記オーバーレイ層が形成された後で、前記第1の表面上の前記少なくとも1箇所の選択領域を覆って存在しない前記接着層、前記バリア層、および前記オーバーレイ層の部分が、前記除去可能なマスクを用いて除去され、前記コンタクトパッドが残るように、前記除去可能なマスクを除去するステップと
を含む、請求項1に記載の方法。 - 前記オーバーレイ層がアルミニウムを含み、前記接着層がチタンを含む、請求項9に記載の方法。
- 前記オーバーレイ層がアルミニウムを含み、前記接着層がチタンを含み、前記バリア層が、前記接着層上に直接形成され、前記オーバーレイ層が前記バリア層上に直接形成される、請求項1に記載の方法。
- 前記半導体構造が、炭化ケイ素材料系から形成される、請求項1に記載の方法。
- 前記オーバーレイ層が、アルミニウム、金、および銅からなる群のうちの1つを含み、前記接着層が、アルミニウム、チタン、白金、およびニッケルからなる群のうちの1つを含む、請求項1に記載の方法。
- 前記バリア層が、100と5000オングストローム(10と500nm)厚の間である、請求項1に記載の方法。
- 前記バリア層が、500と1500オングストローム(50と150nm)厚の間である、請求項1に記載の方法。
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US9799733B2 (en) | 2012-06-06 | 2017-10-24 | Rohm Co., Ltd. | Semiconductor device having a junction portion contacting a schottky metal |
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US20150255362A1 (en) * | 2014-03-07 | 2015-09-10 | Infineon Technologies Ag | Semiconductor Device with a Passivation Layer and Method for Producing Thereof |
KR101764468B1 (ko) * | 2014-07-17 | 2017-08-02 | 주식회사 동부하이텍 | 쇼트키 다이오드 및 그 제조 방법 |
DE102015120668B4 (de) * | 2015-11-27 | 2022-08-11 | Infineon Technologies Ag | Halbleiterbauelement und Verfahren zum Herstellen eines Halbleiterbauelementes |
JP6528793B2 (ja) * | 2017-02-22 | 2019-06-12 | サンケン電気株式会社 | 半導体装置 |
WO2019107571A1 (ja) * | 2017-12-01 | 2019-06-06 | 日本電信電話株式会社 | 平面光波路型光デバイス |
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