JP5891157B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP5891157B2 JP5891157B2 JP2012205174A JP2012205174A JP5891157B2 JP 5891157 B2 JP5891157 B2 JP 5891157B2 JP 2012205174 A JP2012205174 A JP 2012205174A JP 2012205174 A JP2012205174 A JP 2012205174A JP 5891157 B2 JP5891157 B2 JP 5891157B2
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
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Description
図1は実施の形態の半導体装置の構造の一例を示す断面図、図2は図1の半導体装置の裏面側の外部端子の配列の一例を示す裏面図、図3は図1の半導体装置で用いられるテープ基板の構造の一例を示す断面図である。さらに、図4は図1の半導体装置のテープ基板の第1領域とランドパッドの関係の一例を示す部分平面図と、A−A断面図と、B−B断面図、図5は図1の半導体装置のテープ基板における第1領域の表面粗さの定義を示す概念図である。
1a 表面
1b 裏面
1c 電極パッド(パッド)
1d 第1辺
1e 第1方向
1f 第2辺
1g 第2方向
2 テープ基板(配線基板)
2a 上面(第1主面)
2b 下面(第2主面)
2c ランドパターン
2d デバイス領域
2e ランドパッド
2f 第1領域
2fa 第1部分
2fb 第2部分
2fc 第3部分
2fd 第4部分
2g 第2領域
2h Auめっき
2i レジスト膜
2j 第1パターン
2k 第2パターン
2m 基材
2n 接着材
2p スプロケットホール
2q チップ搭載領域
2r 溝部
3 多連テープ基板
4 封止体
5 端子部(外部端子)
6 ダイボンド材(接着材)
7 ワイヤ(金属ワイヤ)
8 COT(半導体装置)
9 シリンジ
10 熱処理装置
10a ベーク炉
11 BGA(半導体装置)
12 半田ボール(外部端子)
13 パッケージ基板(配線基板)
20 ブリード
Claims (13)
- (a)複数のランドパターンが形成された第1主面を有する配線基板を準備する工程と、
(b)前記配線基板の前記第1主面上に接着材を介して半導体チップを搭載する工程と、
(c)前記接着材を常温よりも高い温度下で硬化させる工程と、
(d)前記半導体チップの表面上に配置された複数のパッドと前記複数のランドパターンのうちの複数のランドパッドとをそれぞれ複数の金属ワイヤにより電気的に接続する工程と、
(e)前記配線基板の一部、前記半導体チップ、および前記複数の金属ワイヤを封止体により封止する工程と、を有し、
平面視において、前記配線基板の前記ランドパッドと前記半導体チップとの間の第1領域の表面粗さの局部山頂の平均間隔は、前記配線基板の前記ランドパッドと前記第1領域との間の第2領域の表面粗さの局部山頂の平均間隔よりも小さく、
前記第1領域の表面は、Auめっきが形成されている、半導体装置の製造方法。 - 請求項1に記載の半導体装置の製造方法において、
前記半導体チップの前記表面は、実質的に四角形状であって、前記表面の第1辺は第1方向に伸びており、
前記配線基板の前記ランドパッドは、平面視において、前記第1方向に沿って前記半導体チップの前記第1辺と対向するように配置され、
前記第1領域の前記第1方向における長さは、前記ランドパッドの前記第1方向における長さよりも長い、半導体装置の製造方法。 - 請求項2に記載の半導体装置の製造方法において、
前記第1領域は、平面視において、前記ランドパッドの周囲の一部を囲むように配置されている、半導体装置の製造方法。 - 請求項3に記載の半導体装置の製造方法において、
前記第1領域は、平面視において、前記ランドパッドの周囲を全て囲むように配置されている、半導体装置の製造方法。 - 請求項2に記載の半導体装置の製造方法において、
前記第1領域は、平面視において、前記半導体チップの周囲を囲むように配置されている、半導体装置の製造方法。 - 請求項1に記載の半導体装置の製造方法において、
前記第2領域の表面は、絶縁膜が形成されている、半導体装置の製造方法。 - 請求項1に記載の半導体装置の製造方法において、
前記第1領域の表面の高さは、前記第2領域の表面の高さよりも高い、半導体装置の製造方法。 - 請求項1に記載の半導体装置の製造方法において、
前記第1領域の表面の高さは、前記第2領域の表面の高さよりも低い、半導体装置の製造方法。 - 請求項1に記載の半導体装置の製造方法において、
前記接着材は、エポキシ樹脂を主成分とする、半導体装置の製造方法。 - 請求項1に記載の半導体装置の製造方法において、
前記配線基板は、前記第1主面とは反対側であって、複数の外部端子が配置された第2主面を有し、
前記複数の外部端子と前記複数のランドパッドとはそれぞれ電気的に接続されている、半導体装置の製造方法。 - 請求項1に記載の半導体装置の製造方法において、
前記第1領域は、平面視において、前記ランドパッドの周囲を囲むように形成された第1パターンの一部である、半導体装置の製造方法。 - 請求項1に記載の半導体装置の製造方法において、
前記第1領域は、平面視において、前記半導体チップの周囲を囲むように形成された第2パターンの一部である、半導体装置の製造方法。 - 請求項1に記載の半導体装置の製造方法において、
前記接着材は、低分子成分を有している、半導体装置の製造方法。
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JP2012205174A JP5891157B2 (ja) | 2012-09-19 | 2012-09-19 | 半導体装置の製造方法 |
CN201310430539.6A CN103681388B (zh) | 2012-09-19 | 2013-09-18 | 制造半导体器件的方法 |
US14/030,973 US9006036B2 (en) | 2012-09-19 | 2013-09-18 | Method of manufacturing semiconductor device |
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JPH04107931A (ja) * | 1990-08-29 | 1992-04-09 | Fujitsu Ltd | 半導体装置 |
JPH0521633A (ja) * | 1991-07-12 | 1993-01-29 | Matsushita Electric Ind Co Ltd | 基 板 |
JPH0637122A (ja) | 1992-07-15 | 1994-02-10 | Hitachi Ltd | 半導体装置 |
JPH06342817A (ja) * | 1993-06-02 | 1994-12-13 | Seiko Epson Corp | 半導体装置 |
JPH0745641A (ja) | 1993-07-30 | 1995-02-14 | Matsushita Electric Works Ltd | 半導体装置の実装方法 |
JP2001024310A (ja) * | 1999-07-05 | 2001-01-26 | Nippon Circuit Kogyo Kk | プリント基板の製造方法 |
JP2002050642A (ja) | 2000-07-31 | 2002-02-15 | Hitachi Aic Inc | プリント配線板の製造方法 |
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JP4963148B2 (ja) * | 2001-09-18 | 2012-06-27 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
JP4308608B2 (ja) * | 2003-08-28 | 2009-08-05 | 株式会社ルネサステクノロジ | 半導体装置 |
JP4702157B2 (ja) * | 2006-04-17 | 2011-06-15 | パナソニック株式会社 | Ic部品実装方法とダイボンディング装置 |
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