JP5878362B2 - 半導体装置、半導体パッケージ及び半導体装置の製造方法 - Google Patents

半導体装置、半導体パッケージ及び半導体装置の製造方法 Download PDF

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Publication number
JP5878362B2
JP5878362B2 JP2011282076A JP2011282076A JP5878362B2 JP 5878362 B2 JP5878362 B2 JP 5878362B2 JP 2011282076 A JP2011282076 A JP 2011282076A JP 2011282076 A JP2011282076 A JP 2011282076A JP 5878362 B2 JP5878362 B2 JP 5878362B2
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Japan
Prior art keywords
layer
insulating layer
connection terminal
insulating
substrate
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JP2011282076A
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English (en)
Japanese (ja)
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JP2013131720A5 (https=
JP2013131720A (ja
Inventor
翔太 三木
翔太 三木
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Shinko Electric Industries Co Ltd
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Shinko Electric Industries Co Ltd
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Priority to JP2011282076A priority Critical patent/JP5878362B2/ja
Priority to US13/716,719 priority patent/US8987902B2/en
Publication of JP2013131720A publication Critical patent/JP2013131720A/ja
Publication of JP2013131720A5 publication Critical patent/JP2013131720A5/ja
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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0245—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising use of blind vias during the manufacture
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0249—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias wherein the through-semiconductor via protrudes from backsides of the chips, wafers or substrates during the manufacture
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/095—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers of vias therein
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H10W70/654—Top-view layouts
    • H10W70/655—Fan-out layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/944—Dispositions of multiple bond pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP2011282076A 2011-12-22 2011-12-22 半導体装置、半導体パッケージ及び半導体装置の製造方法 Active JP5878362B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2011282076A JP5878362B2 (ja) 2011-12-22 2011-12-22 半導体装置、半導体パッケージ及び半導体装置の製造方法
US13/716,719 US8987902B2 (en) 2011-12-22 2012-12-17 Semiconductor device, semiconductor package, and method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2011282076A JP5878362B2 (ja) 2011-12-22 2011-12-22 半導体装置、半導体パッケージ及び半導体装置の製造方法

Publications (3)

Publication Number Publication Date
JP2013131720A JP2013131720A (ja) 2013-07-04
JP2013131720A5 JP2013131720A5 (https=) 2014-10-02
JP5878362B2 true JP5878362B2 (ja) 2016-03-08

Family

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JP2011282076A Active JP5878362B2 (ja) 2011-12-22 2011-12-22 半導体装置、半導体パッケージ及び半導体装置の製造方法

Country Status (2)

Country Link
US (1) US8987902B2 (https=)
JP (1) JP5878362B2 (https=)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9123780B2 (en) 2012-12-19 2015-09-01 Invensas Corporation Method and structures for heat dissipating interposers
US9299663B2 (en) 2014-05-19 2016-03-29 Micron Technology, Inc. Semiconductor devices and methods for backside photo alignment
JP2016018879A (ja) * 2014-07-08 2016-02-01 株式会社東芝 半導体装置および半導体装置の製造方法
TWI566305B (zh) * 2014-10-29 2017-01-11 巨擘科技股份有限公司 製造三維積體電路的方法
TWI554174B (zh) * 2014-11-04 2016-10-11 上海兆芯集成電路有限公司 線路基板和半導體封裝結構
US10388608B2 (en) * 2015-08-28 2019-08-20 Hitachi Chemical Company, Ltd. Semiconductor device and method for manufacturing same
KR102031404B1 (ko) * 2016-03-31 2019-10-11 주식회사 엘지화학 리버스 오프셋 행오버 중간체 및 이를 형성하는 리버스 오프셋 금속 패턴의 제조방법
JP6418200B2 (ja) 2016-05-31 2018-11-07 日亜化学工業株式会社 発光装置及びその製造方法
JP6649308B2 (ja) * 2017-03-22 2020-02-19 キオクシア株式会社 半導体装置およびその製造方法
KR101971493B1 (ko) * 2017-09-29 2019-04-23 서울과학기술대학교 산학협력단 은코팅 구리 필라 접합 구조체 및 이를 이용한 접합 방법
US11335634B2 (en) * 2019-08-30 2022-05-17 Taiwan Semiconductor Manufacturing Co., Ltd. Chip package structure and method for forming the same
FR3103315B1 (fr) * 2019-11-19 2021-12-03 St Microelectronics Tours Sas Procédé de fabrication de puces électroniques
FR3104316B1 (fr) * 2019-12-04 2021-12-17 St Microelectronics Tours Sas Procédé de fabrication de puces électroniques
FR3104315B1 (fr) * 2019-12-04 2021-12-17 St Microelectronics Tours Sas Procédé de fabrication de puces électroniques
FR3104317A1 (fr) 2019-12-04 2021-06-11 Stmicroelectronics (Tours) Sas Procédé de fabrication de puces électroniques
JP7078863B2 (ja) * 2020-04-01 2022-06-01 日亜化学工業株式会社 発光装置及びその製造方法
KR20220031398A (ko) * 2020-09-04 2022-03-11 삼성전기주식회사 인쇄회로기판
FR3126540A1 (fr) 2021-08-31 2023-03-03 Stmicroelectronics (Tours) Sas Procédé de fabrication de puces électroniques
KR20230145844A (ko) * 2022-04-11 2023-10-18 엘지이노텍 주식회사 회로기판 및 이를 포함하는 반도체 패키지

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4016984B2 (ja) * 2004-12-21 2007-12-05 セイコーエプソン株式会社 半導体装置、半導体装置の製造方法、回路基板、及び電子機器
US7425507B2 (en) * 2005-06-28 2008-09-16 Micron Technology, Inc. Semiconductor substrates including vias of nonuniform cross section, methods of forming and associated structures
JP2007036571A (ja) * 2005-07-26 2007-02-08 Shinko Electric Ind Co Ltd 半導体装置及びその製造方法
JP4533283B2 (ja) * 2005-08-29 2010-09-01 新光電気工業株式会社 半導体装置の製造方法
JP5222459B2 (ja) * 2005-10-18 2013-06-26 新光電気工業株式会社 半導体チップの製造方法、マルチチップパッケージ
JP5193503B2 (ja) * 2007-06-04 2013-05-08 新光電気工業株式会社 貫通電極付き基板及びその製造方法
US7791159B2 (en) * 2007-10-30 2010-09-07 Panasonic Corporation Solid-state imaging device and method for fabricating the same
JP5318634B2 (ja) * 2009-03-30 2013-10-16 ラピスセミコンダクタ株式会社 チップサイズパッケージ状の半導体チップ及び製造方法

Also Published As

Publication number Publication date
US8987902B2 (en) 2015-03-24
US20130161813A1 (en) 2013-06-27
JP2013131720A (ja) 2013-07-04

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