CN108122880A - 半导体装置的制造方法 - Google Patents
半导体装置的制造方法 Download PDFInfo
- Publication number
- CN108122880A CN108122880A CN201711002107.XA CN201711002107A CN108122880A CN 108122880 A CN108122880 A CN 108122880A CN 201711002107 A CN201711002107 A CN 201711002107A CN 108122880 A CN108122880 A CN 108122880A
- Authority
- CN
- China
- Prior art keywords
- layer
- solder
- etching
- conductive
- dielectric
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 35
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
- 229910000679 solder Inorganic materials 0.000 claims abstract description 82
- 238000005530 etching Methods 0.000 claims abstract description 80
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 44
- 239000003795 chemical substances by application Substances 0.000 claims abstract description 26
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 22
- 239000000523 sample Substances 0.000 claims abstract description 20
- 238000000034 method Methods 0.000 claims description 63
- 239000010410 layer Substances 0.000 description 156
- 239000000758 substrate Substances 0.000 description 75
- 239000011162 core material Substances 0.000 description 63
- 239000000463 material Substances 0.000 description 57
- 239000010949 copper Substances 0.000 description 52
- 229910052802 copper Inorganic materials 0.000 description 47
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 46
- 238000005538 encapsulation Methods 0.000 description 39
- 229910052751 metal Inorganic materials 0.000 description 31
- 239000002184 metal Substances 0.000 description 31
- 239000003989 dielectric material Substances 0.000 description 28
- 238000012360 testing method Methods 0.000 description 27
- 239000013078 crystal Substances 0.000 description 23
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 22
- 229910052737 gold Inorganic materials 0.000 description 18
- 239000010931 gold Substances 0.000 description 18
- 229920000642 polymer Polymers 0.000 description 18
- 239000004020 conductor Substances 0.000 description 17
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 17
- 229920002120 photoresistant polymer Polymers 0.000 description 14
- 238000007747 plating Methods 0.000 description 14
- 239000012778 molding material Substances 0.000 description 13
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 12
- 229910052718 tin Inorganic materials 0.000 description 12
- 239000011135 tin Substances 0.000 description 12
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 11
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 11
- 239000012790 adhesive layer Substances 0.000 description 11
- 239000003822 epoxy resin Substances 0.000 description 11
- 230000004907 flux Effects 0.000 description 11
- 229910052759 nickel Inorganic materials 0.000 description 11
- 229920000647 polyepoxide Polymers 0.000 description 11
- 230000008569 process Effects 0.000 description 11
- 230000001681 protective effect Effects 0.000 description 11
- 229910052719 titanium Inorganic materials 0.000 description 11
- 239000010936 titanium Substances 0.000 description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 10
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 10
- 238000005229 chemical vapour deposition Methods 0.000 description 10
- 238000001723 curing Methods 0.000 description 10
- 238000001465 metallisation Methods 0.000 description 8
- 229920002577 polybenzoxazole Polymers 0.000 description 8
- 238000012545 processing Methods 0.000 description 8
- 229920005989 resin Polymers 0.000 description 8
- 239000011347 resin Substances 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 239000004642 Polyimide Substances 0.000 description 6
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 6
- 238000000231 atomic layer deposition Methods 0.000 description 6
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 6
- 238000000576 coating method Methods 0.000 description 6
- 229910052763 palladium Inorganic materials 0.000 description 6
- 238000005240 physical vapour deposition Methods 0.000 description 6
- 229920001721 polyimide Polymers 0.000 description 6
- 229910052709 silver Inorganic materials 0.000 description 6
- 239000004332 silver Substances 0.000 description 6
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 5
- 239000004411 aluminium Substances 0.000 description 5
- 229910052782 aluminium Inorganic materials 0.000 description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 5
- 150000001875 compounds Chemical class 0.000 description 5
- 238000010276 construction Methods 0.000 description 5
- 230000009977 dual effect Effects 0.000 description 5
- 229910052732 germanium Inorganic materials 0.000 description 5
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 5
- 238000000227 grinding Methods 0.000 description 5
- 238000000465 moulding Methods 0.000 description 5
- 238000010992 reflux Methods 0.000 description 5
- 239000000377 silicon dioxide Substances 0.000 description 5
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 4
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 4
- 229910052799 carbon Inorganic materials 0.000 description 4
- 229910052804 chromium Inorganic materials 0.000 description 4
- 239000011651 chromium Substances 0.000 description 4
- 239000011248 coating agent Substances 0.000 description 4
- 239000002131 composite material Substances 0.000 description 4
- 238000000151 deposition Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 239000012212 insulator Substances 0.000 description 4
- 238000003475 lamination Methods 0.000 description 4
- 239000005360 phosphosilicate glass Substances 0.000 description 4
- 238000007639 printing Methods 0.000 description 4
- 229910010271 silicon carbide Inorganic materials 0.000 description 4
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 3
- 229910000881 Cu alloy Inorganic materials 0.000 description 3
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 3
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 230000009471 action Effects 0.000 description 3
- ZTXONRUJVYXVTJ-UHFFFAOYSA-N chromium copper Chemical compound [Cr][Cu][Cr] ZTXONRUJVYXVTJ-UHFFFAOYSA-N 0.000 description 3
- 238000004140 cleaning Methods 0.000 description 3
- 230000008878 coupling Effects 0.000 description 3
- 238000010168 coupling process Methods 0.000 description 3
- 238000005859 coupling reaction Methods 0.000 description 3
- 238000013461 design Methods 0.000 description 3
- 239000011152 fibreglass Substances 0.000 description 3
- 239000007769 metal material Substances 0.000 description 3
- 229910017604 nitric acid Inorganic materials 0.000 description 3
- 150000003839 salts Chemical class 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 238000004528 spin coating Methods 0.000 description 3
- CGZLUZNJEQKHBX-UHFFFAOYSA-N titanium tungsten Chemical compound [Ti][Ti][W] CGZLUZNJEQKHBX-UHFFFAOYSA-N 0.000 description 3
- 238000012546 transfer Methods 0.000 description 3
- JYEUMXHLPRZUAT-UHFFFAOYSA-N 1,2,3-triazine Chemical compound C1=CN=NN=C1 JYEUMXHLPRZUAT-UHFFFAOYSA-N 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 2
- 229910000673 Indium arsenide Inorganic materials 0.000 description 2
- 238000004380 ashing Methods 0.000 description 2
- 239000005388 borosilicate glass Substances 0.000 description 2
- 239000011469 building brick Substances 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 230000006835 compression Effects 0.000 description 2
- 238000007906 compression Methods 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 239000010432 diamond Substances 0.000 description 2
- 238000005553 drilling Methods 0.000 description 2
- 238000001035 drying Methods 0.000 description 2
- 239000002305 electric material Substances 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 230000003628 erosive effect Effects 0.000 description 2
- 239000000945 filler Substances 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 239000003365 glass fiber Substances 0.000 description 2
- 239000003292 glue Substances 0.000 description 2
- 238000013007 heat curing Methods 0.000 description 2
- 238000011065 in-situ storage Methods 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 2
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 2
- 229910000765 intermetallic Inorganic materials 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 239000005001 laminate film Substances 0.000 description 2
- 238000010030 laminating Methods 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 239000011435 rock Substances 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 229910052723 transition metal Inorganic materials 0.000 description 2
- 150000003624 transition metals Chemical class 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- XQUPVDVFXZDTLT-UHFFFAOYSA-N 1-[4-[[4-(2,5-dioxopyrrol-1-yl)phenyl]methyl]phenyl]pyrrole-2,5-dione Chemical compound O=C1C=CC(=O)N1C(C=C1)=CC=C1CC1=CC=C(N2C(C=CC2=O)=O)C=C1 XQUPVDVFXZDTLT-UHFFFAOYSA-N 0.000 description 1
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910005540 GaP Inorganic materials 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 1
- 229910003978 SiClx Inorganic materials 0.000 description 1
- 238000003848 UV Light-Curing Methods 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 238000004026 adhesive bonding Methods 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
- 239000003054 catalyst Substances 0.000 description 1
- 229910010293 ceramic material Inorganic materials 0.000 description 1
- 238000000748 compression moulding Methods 0.000 description 1
- 238000005034 decoration Methods 0.000 description 1
- 230000032798 delamination Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 239000008393 encapsulating agent Substances 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- -1 for example Substances 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 150000003949 imides Chemical class 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 description 1
- 239000003112 inhibitor Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- LQBJWKCYZGMFEV-UHFFFAOYSA-N lead tin Chemical compound [Sn].[Pb] LQBJWKCYZGMFEV-UHFFFAOYSA-N 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 229910052748 manganese Inorganic materials 0.000 description 1
- 238000005272 metallurgy Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000003801 milling Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910003465 moissanite Inorganic materials 0.000 description 1
- 239000007800 oxidant agent Substances 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- OYLRFHLPEAGKJU-UHFFFAOYSA-N phosphane silicic acid Chemical compound P.[Si](O)(O)(O)O OYLRFHLPEAGKJU-UHFFFAOYSA-N 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229920003192 poly(bis maleimide) Polymers 0.000 description 1
- 239000013047 polymeric layer Substances 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 239000007921 spray Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000001029 thermal curing Methods 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- 229910001428 transition metal ion Inorganic materials 0.000 description 1
- 229910052720 vanadium Inorganic materials 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
- 238000009736 wetting Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
- H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
- H01L2224/21—Structure, shape, material or disposition of high density interconnect preforms of an individual HDI interconnect
- H01L2224/214—Connecting portions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45147—Copper (Cu) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/0651—Wire or wire-like electrical connections from device to substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
- H01L2225/06568—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices decreasing in size, e.g. pyramidical stack
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
- H01L2225/1035—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1047—Details of electrical connections between containers
- H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
一种半导体装置的制造方法包括:在管芯上形成导电柱;使用焊料将测试探针耦合到所述导电柱;以及使用多个刻蚀工艺对所述焊料及所述导电柱进行刻蚀,所述多个刻蚀工艺包括第一刻蚀工艺,所述第一刻蚀工艺包括使用氮系刻蚀剂对所述导电柱进行刻蚀。
Description
技术领域
本发明实施例涉及半导体装置的制造方法。
背景技术
半导体装置被用于例如个人计算机、手机、数码相机及其他电子装备等各种各样的电子应用中。半导体装置通常是通过以下方式来制作:在半导体衬底之上依序沉积绝缘层或介电层、导电层、以及半导体材料层;以及利用光刻(lithography)对所述各种材料层进行图案化以在其上形成电路组件及元件。通常会在单个半导体晶片(semiconductorwafer)上制造数十或数百个集成电路。通过沿着切割道(scribe line)锯切集成电路来单体化各别的管芯(die)。接着将所述各别的管芯单独地封装,例如在多芯片模块中封装或以其他类型的封装方式进行封装。
半导体行业通过不断减小最小特征大小来不断地提高各种电子组件(例如,晶体管、二极管、电阻器及电容器等)的集成密度,以使得更多的组件能够被集成到给定区域中。在一些应用中,例如集成电路管芯等这些较小的电子组件也可能需要使用比过去的封装小的面积的较小的封装。
发明内容
本发明实施例包括一种半导体装置的制造方法。所述方法包括:在管芯上形成导电柱;使用焊料将测试探针耦合到所述导电柱;以及使用多个刻蚀工艺对所述焊料及所述导电柱进行刻蚀,所述多个刻蚀工艺包括第一刻蚀工艺,所述第一刻蚀工艺包括使用氮系刻蚀剂对所述导电柱进行刻蚀。
本发明实施例包括一种半导体装置的制造方法。所述方法包括:使用焊料将测试探针耦合到导电柱;在对所述测试探针进行耦合之后,从所述导电柱移除所述测试探针;以及在移除所述测试探针之后,使用刻蚀工艺从所述导电柱移除所述焊料的剩余部分,所述刻蚀工艺包括使用氮系刻蚀剂对所述焊料进行刻蚀。
本发明实施例包括一种半导体装置的制造方法。所述方法包括:在管芯上形成铜柱体;在所述铜柱体上形成焊料球;对所述焊料球进行回流以形成焊料连接部,所述焊料连接部接触所述铜柱体的侧壁并将测试探针耦合到所述铜柱体的顶表面;使用所述测试探针来测试所述管芯;以及使用氮系刻蚀剂对所述铜柱体的所述顶表面及所述侧壁进行刻蚀。
附图说明
结合附图阅读以下详细说明,会最好地理解本发明的各个方面。应注意,根据本行业中的标准惯例,各种特征并非按比例绘制。事实上,为论述清晰起见,可任意增大或减小各种特征的尺寸。
图1至图9是根据一些实施例的在形成及测试管芯的工艺期间的各中间步骤的剖视图。
图10至图15是根据一些实施例的在形成第一装置封装的工艺期间的各中间步骤的剖视图。
图16是根据一些实施例的在形成封装结构的工艺期间的中间步骤的剖视图。
图17至图18是根据其他实施例的在形成第一装置封装的工艺期间的各中间步骤的剖视图。
具体实施方式
以下公开内容提供用于实作本发明的不同特征的许多不同的实施例或实例。以下阐述组件及排列的具体实例以简化本公开内容。当然,这些仅为实例且不旨在进行限制。举例来说,以下说明中将第一特征形成在第二特征“之上”或第二特征“上”可包括其中第一特征及第二特征被形成为直接接触的实施例,且也可包括其中第一特征与第二特征之间可形成有附加特征、进而使得所述第一特征与所述第二特征可能不直接接触的实施例。另外,本公开内容可能在各种实例中重复使用参考编号及/或字母。这种重复使用是出于简洁及清晰的目的,而不是自身表示所论述的各种实施例及/或配置之间的关系。
此外,为易于说明,本文中可能使用例如“之下(beneath)”、“下面(below)”、“下部的(lower)”、“上方(above)”、“上部的(upper)”等空间相对性用语来阐述图中所示的一个元件或特征与另一(其他)元件或特征的关系。所述空间相对性用语旨在除图中所绘示的取向外还囊括装置在使用或操作中的不同取向。设备可具有其他取向(旋转90度或处于其他取向),且本文中所用的空间相对性描述语可同样相应地进行解释。
根据各种实施例提供一种半导体装置及方法。具体来说,在集成电路装置上形成导电特征,且使用焊料将测试结构耦合到导电特征。在测试之后,通过使用氮系刻蚀剂(nitric-based etchant)对焊料及导电特征进行刻蚀,以从所述导电特征移除所述焊料。所述刻蚀可从导电特征移除焊料,且可在后续加工步骤中减少包封体(encapsulant)从导电特征的侧壁及/或顶表面的分层(delamination)。具体来说,氮系刻蚀剂可对导电特征的表面进行清洁,以使得当使用例如低温聚酰亚胺(low temperature polyimide,LTPI)等包封体对导电特征及集成电路装置进行包封时减少或消除分层。对各实施例的一些变型进行论述。所属领域中的普通技术人员将易于理解可作出预期落于其他实施例范围内的其他润饰。
图1至图9是根据一些实施例的在形成及测试管芯100的工艺期间的各中间步骤的剖视图。管芯100可包括逻辑管芯,例如中央处理器(central processing unit,CPU)、图形处理单元(graphics processing unit,GPU)、类似元件或其组合。在一些实施例中,管芯100包括管芯堆叠(图中未示出),所述管芯堆叠可包括逻辑管芯与存储器管芯二者。管芯100可包括输入/输出(input/output,I/O)管芯,例如在第一封装与随后贴合的第二封装之间提供连接的宽的I/O管芯。
在图1中,示出处于加工的中间阶段的管芯100,管芯100包括衬底50、垫52及保护膜54。在图1中所示步骤之前,可根据可应用制造工艺来加工管芯100以在管芯100中形成集成电路,从而形成集成电路管芯。
衬底50可包括块状半导体衬底(bulk semiconductor substrate)、绝缘体上覆半导体(semiconductor-on-insulator,SOI)衬底、多层式衬底(multi-layered substrate)或梯度衬底(gradient substrate)等。衬底50的半导体可包括例如以下等任意半导体材料:元素半导体,如硅、锗等;化合物半导体或合金半导体,包括SiC、GaAs、GaP、InP、InAs、InSb、SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP及/或GaInAsP;类似材料;或者其组合。
衬底50可包括集成电路装置(图中未示出)。所属领域中的普通技术人员应知,可在衬底50中及/或衬底50上形成例如晶体管、二极管、电容器、电阻器、类似装置或其组合等众多各种各样的集成电路装置来符合对管芯100的设计的结构性要求及功能性要求。可使用任意适合的方法来形成集成电路装置。
衬底50也可包括内连线结构(图中未示出)。可将内连线结构形成在集成电路装置之上并设计成连接各种集成电路装置以形成功能性电路系统(functional circuitry)。内连线结构可由交替的介电(例如,低k介电材料)层与导电材料(例如,铜)层形成,并且可通过任意适合的工艺(例如,沉积、镶嵌、双镶嵌(dual damascene)等)来形成所述内连线结构。导电层及介电层可包括金属线及通孔(图中未示出)以将集成电路装置电耦合到垫52。在图中示出衬底50的仅一部分,原因是这便足以充分阐述说明性实施例。
垫52位于衬底50之上。可将垫52形成在衬底50(图中未示出)中的内连线结构之上且将垫52形成为与所述内连线结构电接触,以帮助提供与集成电路装置的外部连接。垫52位于可被称为管芯100的有源侧的部位上。在一些实施例中,通过在介电层(图中未示出)或衬底50中形成凹陷部(图中未示出)来形成垫52。可将所述凹陷部形成以使得垫52能够嵌置在介电层及/或衬底50中。在其他实施例中,由于可在介电层或衬底50上形成垫52,因此可省略凹陷部。垫52可包括由铜、钛、镍、金、锡、类似材料或其组合制成的薄晶种层(图中未示出)。可在所述薄晶种层之上沉积垫52的导电材料。可通过电化学镀覆工艺(electro-chemical plating process)、化学气相沉积(chemical vapor deposition,CVD)、物理气相沉积(physical vapor deposition,PVD)、原子层沉积(atomic layer deposition,ALD)、类似工艺或其组合来形成所述导电材料。在实施例中,垫52的导电材料为铜、钨、铝、银、金、锡、类似材料或其组合。可将垫52形成为具有介于约0.01μm至约1.0μm之间(例如约0.3μm)的厚度。
为清晰及简洁起见,在管芯100上示出一个垫52,且所属领域中的普通技术人员将易于理解可存在多于一个垫52。
在衬底50上且在垫52之上形成保护膜54。保护膜54可由例如氧化硅、氮化硅、低k介电质(例如,掺杂碳的氧化物)、极低k介电质(例如,掺杂多孔碳的二氧化硅)、聚合物(例如,聚酰亚胺)、阻焊剂、聚苯并恶唑(polybenzoxazole,PBO)、苯并环丁烯(benzocyclobutene,BCB)、模制化合物、类似材料或其组合等一种或多种适合的介电材料制成。可通过例如CVD、PVD、ALD、旋涂介电质工艺(spin-on-dielectric process)、类似工艺或其组合等工艺来形成保护膜54,且保护膜54可具有介于约0.1μm至约10μm之间的厚度。可基于形成保护膜54的材料来变化形成的保护膜54的厚度。在一些实施例中,垫52的顶表面与保护膜54的底表面的一部分齐平。
形成穿过保护膜54的开口以暴露出垫52的一部分。可通过例如刻蚀、钻孔(milling)、激光技术、类似工艺或其组合等来形成所述开口。
在图2中,在衬底50、保护膜54及垫52之上形成晶种层56。晶种层56直接接触位于保护膜54的开口中的垫52的顶表面。在一些实施例中,晶种层56为金属层,所述金属层可为单一层或包括由不同材料形成的多个子层的复合层。晶种层56可由铜、钛、镍、金、类似材料或其组合形成。在一些实施例中,晶种层56包括钛层及位于所述钛层之上的铜层。可使用例如PVD等来形成晶种层56。
在图3中,形成光刻胶58并将光刻胶58图案化在晶种层56之上。在一些实施例中,在晶种层56上形成光刻胶58并将光刻胶58图案化并接着在图案化光刻胶58中形成导电特征(以下将在图4中论述)。可通过湿式工艺(例如,旋涂工艺)或干式工艺(例如,通过涂覆干膜(dry fim))来形成光刻胶58。可在光刻胶58中形成开口60以暴露出下伏的晶种层56。
在图4中,在开口60中形成导电特征62。图4中示出导电特征62具有平的顶表面,但应理解,所述顶表面可为其他形状,例如凸的(convex)顶表面或凹的(concave)顶表面。可通过用于形成导电特征62的工艺的参数来控制导电特征62的顶表面的形状/轮廓。在一些实施例中,通过例如电镀(electroplating)、无电镀覆(electroless plating)等镀覆工艺来形成导电特征62。导电特征62可由如铜、铝、镍、金、银、钯、锡、类似材料或其组合等金属形成,且可具有包括多个层的复合结构。在一些实施例中,可基于导电特征的构造而向镀覆溶液添加被称为催化剂(accelerator)、抑制剂(suppressor)及均衡剂(leveler)的化学添加剂。
在图5中,移除光刻胶58,且移除晶种层56的位于导电特征62之外的部分。可通过例如灰化(ashing)、刻蚀工艺、类似工艺或其组合等适合的移除工艺来移除光刻胶58及晶种层56。
在图6中,在加工期间使用具有探针触点(probe contact)的测试结构64来测试管芯100。可在形成管芯100时原位(in-situ)执行所述测试且所述测试可监测管芯100的良率(yield)。使用焊料顶盖(solder cap)66将测试结构64的探针触点耦合到导电特征62。通过使用例如蒸镀(evaporation)、电镀、印刷、焊料转移(solder transfer)、植球(ballplacement)等这些常用方法初始地形成焊料层来在导电特征62的顶表面上形成焊料顶盖66。当已在导电特征62上形成焊料层时,可执行回流(reflow)以对焊料进行回流且形成焊料顶盖66,焊料顶盖66将导电特征62实体地耦合到且电耦合到测试结构64。在回流期间,在焊料顶盖66与导电特征62之间可形成金属间化合物(intermetallic compound,IMC)(图中未示出)。当导电特征62耦合到测试结构64时,测试管芯100。若管芯100未通过测试,可停止进一步的加工。
在图7中,将测试结构64从导电特征62解耦合(decouple)。使用选择性刻蚀工艺(selective etching process)68来移除焊料顶盖66。选择性刻蚀工艺68对于焊料顶盖66的材料来说具有选择性。在实施例中,导电特征62由Cu形成,且选择性刻蚀工艺68是使用氮系刻蚀剂的湿刻蚀工艺(wet etching process)。氮系刻蚀剂可为包含例如V、Cr、Mn或Fe等过渡金属的离子的硝酸。硝酸中的过渡金属离子的浓度可介于约0.1%至约10%之间。过渡金属的离子会对刻蚀化学成分的选择性进行调制,以使选择性刻蚀工艺68移除IMC及焊料顶盖66而不显著地损坏导电特征62的暴露出的表面。在其中导电特征62由Cu形成的实施例中,对暴露出的表面造成的损坏可因导电特征62中的Cu与焊料顶盖66中的锡之间的还原(氧化还原)电位差而减轻。过渡金属充当焊料顶盖66的氧化剂,以使焊料顶盖66中的锡与硝酸形成盐,但导电特征62中的Cu不形成盐或形成比焊料顶盖66中的锡少的盐。使用选择性刻蚀工艺68从Cu柱体移除焊料造成的表面损坏可比传统焊料移除刻蚀工艺少。选择性刻蚀工艺68可为单步骤刻蚀工艺(single-step etching process),所述单步骤刻蚀工艺还将对导电特征62的暴露出的表面进行清洁。在一些实施例中,选择性刻蚀工艺68包括多个刻蚀工艺,所述多个刻蚀工艺中的一个刻蚀工艺包括使用氮系刻蚀剂,且所述多个刻蚀工艺中的其他刻蚀工艺包括进一步改善对导电特征62的表面的清洁的其他清洁步骤。使用氮系刻蚀剂及可选的其他清洁步骤也可提高从导电特征62移除的焊料的量。
当形成焊料顶盖66时,在未来的包封步骤(以下将论述)中对焊料进行回流时可沿导电特征62形成空隙(void),且可使得焊料沿导电特征62的侧壁润湿(wetting)。氮系刻蚀剂可从导电特征62的侧壁移除焊料且减少或消除空隙的数量。
在图8中,将介电材料70形成在管芯100的有源侧上,例如形成在保护膜54及导电特征62上。介电材料70可包封导电特征62。在一些实施例中,介电材料70在侧向上毗邻管芯100。介电材料70可为例如聚苯并恶唑(PBO)、聚酰亚胺、苯并环丁烯(BCB)等聚合物。在其他实施例中,介电材料70由以下材料形成:氮化物,例如氮化硅;氧化物,例如氧化硅、磷硅酸盐玻璃(phosphosilicate glass,PSG)、硼硅酸盐玻璃(borosilicate glass,BSG)、掺杂硼的磷硅酸盐玻璃(boron-doped phosphosilicate glass,BPSG)等;或者类似材料。可通过例如旋转涂布(spin coating)、CVD、积层(laminating)、类似工艺或其组合等任意可接受的沉积工艺来形成介电材料70。在形成之后,介电材料70埋置导电特征62。
在实施例中,介电材料70是LTPI。使用氮系刻蚀剂从导电特征62移除焊料顶盖66并清洁导电特征62可改善LTPI与导电特征62之间的界面。具体来说,使用氮系刻蚀剂对焊料顶盖66执行清洁及移除可减少原本将在焊料剩余在导电特征62上时在介电材料70与导电特征62之间的界面处发生的分层。减少分层可改善介电材料70与导电特征62之间的粘合。
在图9中,可对介电材料70执行例如研磨(grinding)或化学机械平坦化(chemical-mechanical planarization,CMP)等平坦化步骤72。使用平坦化步骤72移除介电材料70的过量部分,这些过量部分位于导电特征62的顶表面之上。在一些实施例中,将导电特征62的顶表面暴露出并将所述顶表面平坦化,且所述顶表面与介电材料70的顶表面齐平。在一些实施例中,省略平坦化步骤72。在这些实施例(以下将参照图17至图18来论述)中,介电材料70的过量部分可剩余在导电特征62的顶表面之上且将在后续平坦化步骤中被移除。如图所示,导电特征62延伸到介电材料70的顶表面且可用作通往例如重布线层(redistribution layer,RDL)(以下将在图13中论述)等下一导电层的通孔且可在下文中被称作导电通孔。此外,将导电特征62嵌置在介电材料70内且将导电特征62与下一导电层(参见图9)隔离。也可将导电特征62称作柱体或微凸块(microbump)。
图10至图15是根据一些实施例的在形成第一装置封装200的工艺期间的各中间步骤的剖视图。在图10中,第一装置封装200包括载体衬底102及位于载体衬底102之上的介电层104。
载体衬底102可为对位于载体衬底102之上的层提供(在制作工艺的中间操作期间)机械支撑的任意适合的衬底。载体衬底102可为包含玻璃、硅(例如,硅晶片)、氧化硅、金属板、陶瓷材料等的晶片。
粘合层(图中未示出)可将载体衬底102粘合到介电层104。可将粘合层设置(例如,积层)在载体衬底102上。粘合层可由例如当暴露于紫外(ultra-violet,UV)光时将失去自身的粘合性质的紫外(UV)胶等胶、当受热时将失去自身的粘合性质的光热转换(light-to-heat conversion,LTHC)材料等形成。粘合层可为液体,经分配并进行固化。粘合层亦可为被积层到载体衬底102上的积层体膜(laminate film)或可为类似形式。粘合层的顶表面可以是平的(leveled)且可具有高的共面程度(degree of coplanarity)。
在粘合层及载体衬底102之上形成介电层104。介电层104可为氮化硅、碳化硅、氧化硅、低k介电质(例如,掺杂碳的氧化物)、极低k介电质(例如,掺杂多孔碳的二氧化硅)、聚合物(例如,环氧树脂、聚酰亚胺、苯并环丁烯、聚苯并恶唑)、类似材料或其组合。尽管如此,介电层104也可使用其他相对软的(常为有机的)介电材料。可通过CVD、PVD、ALD、旋涂介电质工艺、类似工艺或其组合来沉积介电层104。
在一些实施例中,介电层104可为背侧重布线结构(backside redistributionstructure)。背侧重布线结构(介电层104)可由交替的介电(例如,低k介电材料)层与导电材料(例如,铜)层形成,且可通过任意适合的工艺(例如,沉积、镶嵌、双镶嵌等)来形成背侧重布线结构(介电层104)。导电层及介电层可包括金属线及通孔(图中未示出)。
在图10中,可进一步在晶种层(图中未示出)之上形成电连接件108且电连接件108在实质上垂直于介电层104的表面的方向上从晶种层延伸。在其中介电层104是背侧重布线结构的实施例中,将电连接件108实体地耦合到且电耦合到背侧重布线结构(介电层104)。
在一些实施例中,通过镀覆工艺来形成电连接件108。在这些实施例中,电连接件108由铜、铝、镍、金、银、钯、锡、类似材料或其组合等制成,且可具有包括多个层的复合结构。在这些实施例中,可在载体衬底102之上形成光刻胶(图中未示出)。在一些实施例中,在晶种层上形成光刻胶并进行图案化,且接着在图案化光刻胶中形成电连接件108。可通过湿式工艺(例如,旋涂工艺)或干式工艺(例如,通过涂覆干膜)来形成光刻胶。在光刻胶中形成多个开口以暴露出下伏的晶种层。接着执行镀覆步骤以镀覆电连接件108。
在替代性实施例中,电连接件108可为短柱凸块(stud bump),所述短柱凸块是通过以下方式形成:在介电层104之上进行打线接合(wire bonding)并切断接合导线且使接合导线的一部分贴合到相应接合球(bond ball)。举例来说,电连接件108可包括下部部分及上部部分,其中所述下部部分可为在打线接合中形成的接合球(图中未示出),且所述上部部分可为其余接合导线(图中未示出)。电连接件108的上部部分可具有在上部部分的整个顶部、中部及底部上均匀的均匀宽度及均匀形状。电连接件108可由可通过打线接合器(wire bonder)接合的非焊料金属材料形成。在一些实施例中,电连接件108由铜导线、金导线、类似导线或其组合等制成,且可具有包括多个层的复合结构。在打线接合实施例中,可省略晶种层及牺牲层。
在图11中,使用粘合层106将管芯100粘合到介电层104。在粘合到介电层104之前,可根据适用于在管芯100中形成集成电路的制造工艺来加工管芯100(参见图1至图9)。粘合层106可为任意适合的粘合剂,例如管芯贴合膜(die attach film,DAF)等。
在图12中,使用模制材料110来包封管芯100及电连接件108。可例如使用压缩模制(compression molding)将模制材料110模制在管芯100及电连接件108上。在一些实施例中,模制材料110由模制化合物、聚合物、环氧树脂、氧化硅填料材料、类似材料或其组合制成。可执行固化步骤以固化模制材料110,其中所述固化可为热固化(thermal curing)、紫外固化(UV curing)、类似固化方式或其组合。
在一些实施例中,将管芯100、导电通孔(导电特征62)及电连接件108埋置在模制材料110中,且在将模制材料110固化之后,对模制材料110执行例如研磨或CMP等平坦化步骤。使用平坦化步骤移除模制材料110的过量部分,这些过量部分位于导电通孔(导电特征62)的顶表面及电连接件108的顶表面之上。在一些实施例中,将导电通孔(导电特征62)的表面及电连接件108的表面暴露出,且导电通孔(导电特征62)的表面及电连接件108的表面与模制材料110的表面齐平。可将电连接件108称作模制穿孔(through molding via,TMV)、封装穿孔(through package via,TPV)及/或集成扇出型(integrated fan-out,InFO)穿孔(through InFO via,TIV),且将在下文中将电连接件108称作TIV。
在图13中,在管芯100、TIV(电连接件108)及模制材料110之上形成第一聚合物层112。在第一聚合物层112中形成开口,且在所述开口中形成实体地耦合到且电耦合到TIV(电连接件108)及/或导电特征62的凸块下金属(under bump metallurgy,UBM)114。UBM114具有位于第一聚合物层112之上的部分,且接触开口的侧壁。在第一聚合物层112之上及UBM 114之上形成第二聚合物层116。
通过若干种方式形成第一聚合物层112及第二聚合物层116。在一些实施例中,第一聚合物层112及/或第二聚合物层116包含聚苯并恶唑(PBO)、聚酰亚胺、环氧树脂等等。可通过化学气相沉积(CVD)、旋转涂布、积层等等来形成或沉积第一聚合物层112及/或第二聚合物层116。第二聚合物层116可相似于第一聚合物层112或可为不同的聚合物层。
可通过首先穿过第一聚合物层112形成开口以暴露出TIV(电连接件108)的表面及/或导电特征62的表面来形成UBM 114。UBM 114可延伸穿过第一聚合物层112中的这些开口且还沿第一聚合物层112的表面延伸。UBM 114可包括三个导电材料层,例如钛层、铜层及镍层。然而,所属领域中的普通技术人员将知,存在许多适合用于形成UBM 114的适合的材料与层的排列方式,例如铬/铬-铜合金/铜/金的排列方式、钛/钛钨/铜的排列方式或铜/镍/金的排列方式。可用于UBM 114的任意适合的材料或材料层完全旨在包含于当前申请的范围内。
在图13中,进一步在管芯100、TIV(电连接件108)及模制材料110上形成前侧重布线结构(front-side redistribution structure)118。前侧重布线结构118包括多个介电层及金属化图案。举例来说,可将前侧重布线结构118图案化成通过相应的一个或多个介电层而彼此分隔开的多个分立的部分。前侧重布线结构118可为例如重布线层(redistribution layer,RDL),且可包括金属迹线(或金属线)及位于所述金属迹线之下且连接到所述金属迹线的通孔。根据本发明的一些实施例,通过镀覆工艺形成RDL,其中所述RDL中的每一者包括晶种层(图中未示出)及位于所述晶种层之上的经镀覆金属材料。晶种层与经镀覆金属材料可由相同材料或不同材料形成。
示出前侧重布线结构118作为实例。可在前侧重布线结构118中形成比所示出的介电层及金属化图案更多或更少的介电层及金属化图案。所属领域中的普通技术人员将易于理解,将省略或重复进行哪些步骤及工艺来形成更多的或更少的介电层及金属化图案。
在图13中,进一步形成耦合到前侧重布线结构118的UMB 120,且形成耦合到UMB120的导电连接件122。可通过首先穿过最顶部介电层形成一组开口(图中未示出)以暴露出前侧重布线结构118中的金属化图案的表面来形成凸块下金属120。UBM 120可延伸穿过介电层中的这些开口且还沿所述介电层的表面延伸。UBM 120可包括三个导电材料层,例如钛层、铜层及镍层。然而,所属领域中的普通技术人员将知,存在许多适合用于形成UBM 120的适合的材料与层的排列方式,例如铬/铬-铜合金/铜/金的排列方式、钛/钛钨/铜的排列方式或铜/镍/金的排列方式。可用于UBM 120的任意适合的材料或材料层完全旨在包含于当前申请的范围内。
在一些实施例中,可形成耦合到UBM 120的子集的表面安装装置(surface mountdevice,SMD)(图中未示出)。SMD可为无源装置或有源装置。
导电连接件122可为焊料凸块、金属柱体、受控塌陷芯片连接(controlledcollapse chip connection,C4)凸块、微凸块、无电镀镍钯浸金技术(electrolessnickel-electroless palladium-immersion gold technique,ENEPIG)形成的凸块等。导电连接件122可包含例如焊料、铜、铝、金、镍、银、钯、锡、类似材料或其组合等导电材料。在其中导电连接件122为焊料凸块的实施例中,通过使用例如蒸镀、电镀、印刷、焊料转移、植球等常用方法初始地形成焊料层来形成导电连接件122。一旦已在所述结构上形成焊料层,则可执行回流以将所述材料造型成所需凸块形状。在另一实施例中,导电连接件122为通过溅镀(sputtering)、印刷、电镀、无电镀覆、化学气相沉积等而形成的金属柱体(例如铜柱体)。所述金属柱体可不含有焊料且具有实质上垂直的侧壁。在一些实施例中,在金属柱体的顶部上形成金属顶盖层(metal cap layer)(图中未示出)。金属顶盖层可包含镍、锡、锡-铅、金、银、钯、铟、镍-钯-金、镍-金、类似材料或其组合,且可通过镀覆工艺来形成所述金属顶盖层。
在图14中,根据实施例使用粘合层来剥离载体衬底102以暴露出介电层104。举例来说,通过将UV光或激光投影在粘合层上来执行所述剥离。举例来说,当粘合层由LTHC形成时,从光或激光产生的热会使LTHC分解,且因此使载体衬底102从第一装置封装200分离。接着将所述结构翻转并放置在固定到切割架(dicing frame)(图中未示出)的切割胶带(dicing tape)124上。将切割胶带124贴合到第一装置封装200以保护导电连接件122。
在图15中,穿过介电层104的至少一部分形成开口126以暴露出TIV(电连接件108)及/或导电特征的位于背侧重布线结构(介电层104)中的部分。可例如使用激光钻孔(laserdrilling)、刻蚀等来形成开口126。
图16是根据一些实施例的在形成封装结构500的工艺期间的中间步骤的剖视图。封装结构500可为叠层封装(package-on-package,PoP)结构。
在图16中,将第二装置封装300贴合到第一装置封装200。第二装置封装300包括衬底302及耦合到衬底302的一个或多个堆叠管芯308(管芯308A及管芯308B)。衬底302可由例如硅、锗、金刚石等半导体材料制成。在一些实施例中,也可使用例如硅锗、碳化硅、镓砷、砷化铟、磷化铟、碳化硅锗、磷化镓砷、磷化镓铟、这些的组合等化合物材料。另外,衬底302可为SOI衬底。一般来说,SOI衬底包括例如外延硅、锗、硅锗、SOI、绝缘体上硅锗(silicongermanium on insulator,SGOI)或其组合等半导体材料的层。在一个替代性实施例中,衬底302是基于绝缘芯体,例如玻璃纤维加强型树脂芯体(fiberglass reinforced resincore)。一种示例性芯体材料为玻璃纤维树脂(例如,FR4)。芯体材料的另一些选择包括双马来酰亚胺三嗪(bismaleimide-tirazine,BT)树脂,或作为另外一种选择,包括其他印刷电路板(printed circuit board,PCB)材料或膜。衬底302可使用例如味之素增层膜(Ajinomoto build-up film,ABF)等增层膜或其他积层体。
衬底302可包括有源装置或无源装置(图中未示出)。所属领域中的普通技术人员应知,可使用例如晶体管、电容器、电阻器、这些的组合等众多各种各样的装置来符合对第二装置封装300设计的结构性要求及功能性要求。可使用任亦适合的方法来形成所述装置。
衬底302也可包括金属化层(图中未示出)及穿孔306。可在有源装置及无源装置之上形成金属化层并将所述金属化层设计成连接各种装置,以形成功能性电路系统。金属化层可由交替的介电(例如,低k介电材料)层与导电材料(例如,铜)层以及对各导电材料层进行内连的通孔形成,并且可通过任意适合的工艺(例如,沉积、镶嵌、双镶嵌等)来形成所述金属化层。在一些实施例中,衬底302实质上不含有有源装置及无源装置。
衬底302可具有接合垫303及接合垫304,接合垫303位于衬底302的第一侧上以耦合到堆叠管芯308,接合垫304位于衬底302的第二侧上以耦合到导电连接件314,衬底302的第二侧与第一侧相对。在一些实施例中,通过在衬底302的第一侧及第二侧上在介电层(图中未示出)中形成凹陷部(图中未示出)来形成接合垫303及接合垫304。可将凹陷部形成为使得接合垫303及接合垫304能够嵌置于介电层中。在其他实施例中,由于可在介电层上形成接合垫303及接合垫304,因此将省略所述凹陷部。在一些实施例中,接合垫303及接合垫304包括由铜、钛、镍、金、钯、类似材料或其组合制成的薄晶种层(图中未示出)。可在所述薄晶种层之上沉积接合垫303及304的导电材料。可通过电化学镀覆工艺、无电镀覆工艺、CVD、ALD、PVD、类似工艺或其组合来形成导电材料。在实施例中,接合垫303及304的导电材料为铜、钨、铝、银、金、类似材料或其组合。
在实施例中,接合垫303及接合垫304为包括三个导电材料层的UBM,所述三个导电材料层例如为钛层、铜层及镍层。然而,所属领域中的普通技术人员应知,存在许多适合用于形成UBM(接合垫303及接合垫304)的材料与层的排列方式,例如铬/铬-铜合金/铜/金的排列方式、钛/钛钨/铜的排列方式或铜/镍/金的排列方式。可用于UBM 303及接合垫304的任意适合的材料或材料层完全旨在包含于当前申请的范围内。在一些实施例中,穿孔306穿过衬底302而延伸且将至少一个接合垫303耦合到至少一个接合垫304。
在所示实施例中,堆叠管芯308是通过打线接合件(wire bond)310耦合到衬底302。尽管如此,可使用例如导电凸块等其他连接方式将打线接合件(wire bond)310耦合到衬底302。在实施例中,堆叠管芯308为堆叠的存储器管芯。举例来说,堆叠的存储器管芯可包括低功率(low-power,LP)双倍数据速率(double data rate,DDR)存储器模块,例如LPDDR1、LPDDR2、LPDDR3、LPDDR4或类似的存储器模块。
在一些实施例中,可通过模制材料312来包封堆叠管芯308及打线接合件310。可例如使用压缩模制将模制材料312模制在堆叠管芯308及打线接合件310上。在一些实施例中,模制材料312为模制化合物、聚合物、环氧树脂、氧化硅填料材料、类似材料或其组合。可执行固化步骤以固化模制材料312,其中所述固化可为热固化、紫外固化、类似固化方式或其组合。
在一些实施例中,将堆叠管芯308及打线接合件310埋置在模制材料312中,且在将模制材料312固化之后,执行例如研磨等平坦化步骤以移除模制材料312的过量部分,且为第二装置封装300提供实质上平坦的表面。
在形成第二装置封装300之后,通过导电连接件314、接合垫304、背侧重布线结构(介电层104)及/或TIV(电连接件108),将第二装置封装300接合到第一装置封装200。在一些实施例中,可通过打线接合件310、接合垫303及接合垫304、穿孔306、导电连接件314以及TIV(电连接件108)将堆叠管芯308耦合到管芯100。
导电连接件314可相似于上述导电连接件122,且本文中不再对其予以赘述。尽管如此,导电连接件314与导电连接件122无需相同。在一些实施例中,在接合导电连接件314之前,以例如免清洗焊剂(no-clean flux)等焊剂(图中未示出)涂布导电连接件314。可将导电连接件314浸入焊剂中或可将所述焊剂喷射至导电连接件314上。在另一实施例中,可将焊剂涂覆到背侧重布线结构(介电层104)的表面。在开口126中形成导电连接件314。
在一些实施例中,在导电连接件314被回流之前,导电连接件314上可形成有环氧树脂焊剂(epoxy flux)(图中未示出),所述环氧树脂焊剂的至少一些环氧树脂部分会在将第二装置封装300贴合到第一装置封装200之后剩余。此剩余的环氧树脂部分可充当底部填充体(underfill)以减小应力并保护对导电连接件314进行回流而得到的接点(joint)。在一些实施例中,可在第二装置封装300与第一装置封装200之间形成环绕导电连接件314的底部填充体(图中未示出)。可在贴合第二装置封装300之后通过毛细流动工艺来形成底部填充体,或者可在贴合第二装置封装300之前通过适合的沉积方法来形成所述底部填充体。
第二装置封装300与第一装置封装200之间的接合可为焊料接合或直接金属对金属(metal-to-metal)(例如,铜对铜(copper-to-copper)或锡对锡(tin-to-tin))接合。在一个实施例中,通过回流工艺将第二装置封装300接合到第一装置封装200。在此回流工艺期间,导电连接件314接触接合垫304及背侧重布线结构(介电层104)以将第二装置封装300实体地耦合到且电耦合到第一装置封装200。在接合工艺之后,可在背侧重布线结构(介电层104)与导电连接件314的界面处且还在导电连接件314与接合垫304之间的界面(图中未示出)处形成IMC(图中未示出)。
在图16中,进一步通过将第一装置封装200安装到衬底400而将第一装置封装200及第二装置封装300贴合到衬底400。可将衬底400称为封装衬底400。使用导电连接件122将第一装置封装200安装到封装衬底400。
封装衬底400可由例如硅、锗、金刚石等半导体材料制成。作为另外一种选择,也可使用例如硅锗、碳化硅、镓砷、砷化铟、磷化铟、碳化硅锗、磷化镓砷、磷化镓铟、这些的组合等化合物材料。另外,封装衬底400可为SOI衬底。一般来说,SOI衬底包括例如外延硅、锗、硅锗、SOI、SGOI或其组合等半导体材料的层。在一个替代性实施例中,封装衬底400是基于绝缘芯体,例如玻璃纤维加强型树脂芯体。一个示例性芯体材料为玻璃纤维树脂(例如,FR4)。芯体材料的另一些选择包括双马来酰亚胺三嗪BT树脂,或作为另外一种选择,包括其他PCB材料或膜。封装衬底400可使用例如ABF等增层膜或其他积层体。
封装衬底400可包括有源装置或无源装置(图中未示出)。如所属领域中的普通技术人员应知,可使用例如晶体管、电容器、电阻器、这些的组合等众多各种各样的装置来符合对封装结构500的设计的结构性要求及功能性要求。可使用任意适合的方法来形成所述装置。
封装衬底400也可包括金属化层及通孔(图中未示出)以及位于所述金属化层及通孔之上的接合垫402。可将金属化层形成在有源装置及无源装置之上并将所述金属化层设计成连接各种装置,以形成功能性电路系统。金属化层可由交替的介电(例如,低k介电材料)层与导电材料(例如,铜)层以及对各导电材料层进行内连的通孔形成,并且可通过任意适合的工艺(例如,沉积、镶嵌、双镶嵌等)来形成所述金属化层。在一些实施例中,封装衬底400实质上不含有有源装置及无源装置。
在一些实施例中,导电连接件122可进行回流以将第一装置封装200贴合到接合垫402。导电连接件122将衬底400(包括位于衬底400中的金属化层)电耦合到及/或实体地耦合到第一装置封装200。
在导电连接件122被回流之前,导电连接件122上可形成有环氧树脂焊剂(图中未示出),所述环氧树脂焊剂的至少一些环氧树脂部分会在将第一装置封装200贴合到衬底400之后剩余。此剩余的环氧树脂部分可充当底部填充体以减小应力并保护对导电连接件122进行回流而得到的接点。在一些实施例中,可在第一装置封装200与衬底400之间形成环绕导电连接件122的底部填充体(图中未示出)。可在贴合第一装置封装200之后通过毛细流动工艺来形成底部填充体,或者可在贴合第一装置封装200之前通过适合的沉积方法来形成所述底部填充体。
图17至图18是根据其他实施例的在形成第一装置封装200的工艺期间的各中间步骤的剖视图。在图17至图18中所示实施例中,利用以上在图1至图8中阐述的工艺流程来加工管芯100。省略平坦化步骤72(示出于图9中)。这样一来,管芯100在导电特征62之上具有介电材料70。在图17中,将管芯100与过量的介电材料70一起粘合到介电层104。在放置管芯100之后,介电材料70的顶表面及电连接件108的顶表面高于导电特征62的顶表面。在图18中,使用模制材料110来包封管芯100及电连接件108。对模制材料110、管芯100及电连接件108执行例如研磨或CMP等平坦化步骤。平坦化步骤将移除位于导电特征62之上的介电材料70的过量部分。在平坦化步骤之后,电连接件108的顶表面、模制材料110的顶表面、介电材料70的顶表面及导电特征62的顶表面齐平。可接着利用在图13至图16中示出的工艺流程来继续对第一装置封装200的加工。
一些实施例可实现多个优点。随着装置的大小持续缩小,使用氮系刻蚀剂移除焊料顶盖可减少因高温焊料移除操作而造成的翘曲(warpage),且可增大后续研磨操作的工艺窗口大小(process window size)。对导电柱进行清洁可减少将在包封所述导电柱时发生的分层,且可增强所述导电柱与包封体之间的粘合。作为结果,在测试装置之后进行的加工可具有较高的良率。
一个实施例包括一种半导体装置的制造方法。所述方法包括:在管芯上形成导电柱;使用焊料将测试探针耦合到所述导电柱;以及使用多个刻蚀工艺对所述焊料及所述导电柱进行刻蚀,所述多个刻蚀工艺包括第一刻蚀工艺,所述第一刻蚀工艺包括使用氮系刻蚀剂对所述导电柱进行刻蚀。
在一些实施例中,在所述刻蚀之前,所述焊料接触所述导电柱的顶表面及侧壁。
在一些实施例中,对所述焊料及所述导电柱进行刻蚀以将所述导电柱的所述顶表面及所述侧壁移除所述焊料。
在一些实施例中,所述半导体装置的制造方法进一步包括:在将所述测试探针耦合到所述导电柱之后,测试所述管芯。
在一些实施例中,所述刻蚀是在所述测试之后执行。
在一些实施例中,所述半导体装置的制造方法进一步包括:在对所述焊料及所述导电柱进行刻蚀之后,在所述管芯之上形成介电质,所述介电质接触所述导电柱的侧壁。
在一些实施例中,所述半导体装置的制造方法进一步包括:将所述管芯放置在载体衬底上;在所述载体衬底上且邻近所述管芯处形成通孔;以及使用模制化合物来包封所述管芯及所述通孔。
在一些实施例中,所述半导体装置的制造方法进一步包括:在所述管芯及所述通孔之上形成重布线层;以及在所述重布线层上形成外部触点。
一个实施例包括一种方法。所述方法包括:使用焊料将测试探针耦合到导电柱;在对所述测试探针进行耦合之后,从所述导电柱移除所述测试探针;以及在移除所述测试探针之后,使用刻蚀工艺从所述导电柱移除所述焊料的剩余部分,所述刻蚀工艺包括使用氮系刻蚀剂对所述焊料进行刻蚀。
在一些实施例中,使用所述氮系刻蚀剂对所述焊料进行刻蚀包括从所述导电柱的侧壁刻蚀掉所述焊料。
在一些实施例中,使用所述氮系刻蚀剂对所述焊料进行刻蚀包括从所述导电柱的顶表面刻蚀掉所述焊料。
在一些实施例中,所述半导体装置的制造方法进一步包括:在从所述导电柱移除所述焊料的所述剩余部分之后,在所述导电柱的被刻蚀的所述侧壁及所述顶表面上形成介电材料。
在一些实施例中,使用所述氮系刻蚀剂对所述焊料进行刻蚀将清洁所述导电柱。
在一些实施例中,所述导电柱是铜柱体。
一个实施例包括一种方法。所述方法包括:在管芯上形成铜柱体;在所述铜柱体上形成焊料球;对所述焊料球进行回流以形成焊料连接部,所述焊料连接部接触所述铜柱体的侧壁并将测试探针耦合到所述铜柱体的顶表面;使用所述测试探针来测试所述管芯;以及使用氮系刻蚀剂对所述铜柱体的所述顶表面及所述侧壁进行刻蚀。
在一些实施例中,所述对所述铜柱体的所述顶表面及所述侧壁进行刻蚀包括使用多种刻蚀剂对所述铜柱体执行多个刻蚀步骤,所述多种刻蚀剂中的至少一种是氮系刻蚀剂。
在一些实施例中,所述半导体装置的制造方法进一步包括:在所述铜柱体的被刻蚀的所述侧壁及所述顶表面上形成介电材料;以及将所述介电材料平坦化,直至所述铜柱体的所述顶表面与所述介电材料的顶表面齐平。
在一些实施例中,刻蚀所述铜柱体的所述顶表面及所述侧壁将移除所述焊料连接部且将所述测试探针从所述铜柱体解耦合。
在一些实施例中,所述半导体装置的制造方法进一步包括:将所述管芯放置在载体衬底上;在邻近所述管芯处形成通孔;以及在所述载体衬底上包封所述管芯及所述通孔。
在一些实施例中,所述半导体装置的制造方法进一步包括:在所述管芯及所述通孔之上形成重布线层;以及在所述重布线层上形成外部触点。以上概述了若干实施例的特征,以使所属领域中的技术人员可更好地理解本发明的各个方面。所属领域中的技术人员应知,其可容易地使用本发明作为设计或修改其他工艺及结构的基础来施行与本文中所介绍的实施例相同的目的及/或实现与本文中所介绍的实施例相同的优点。所属领域中的技术人员还应认识到,这些等效构造并不背离本发明的精神及范围,而且他们可在不背离本发明的精神及范围的条件下对其作出各种改变、代替及变更。
Claims (1)
1.一种半导体装置的制造方法,其特征在于,包括:
在管芯上形成导电柱;
使用焊料将测试探针耦合到所述导电柱;以及
使用多个刻蚀工艺对所述焊料及所述导电柱进行刻蚀,所述多个刻蚀工艺包括第一刻蚀工艺,所述第一刻蚀工艺包括使用氮系刻蚀剂对所述导电柱进行刻蚀。
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201662427693P | 2016-11-29 | 2016-11-29 | |
US62/427,693 | 2016-11-29 | ||
US15/640,942 | 2017-07-03 | ||
US15/640,942 US10186462B2 (en) | 2016-11-29 | 2017-07-03 | Semiconductor device and method |
Publications (2)
Publication Number | Publication Date |
---|---|
CN108122880A true CN108122880A (zh) | 2018-06-05 |
CN108122880B CN108122880B (zh) | 2022-10-28 |
Family
ID=62190966
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201711002107.XA Active CN108122880B (zh) | 2016-11-29 | 2017-10-24 | 半导体装置的制造方法 |
Country Status (3)
Country | Link |
---|---|
US (2) | US10186462B2 (zh) |
CN (1) | CN108122880B (zh) |
TW (1) | TWI749088B (zh) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN110379719A (zh) * | 2018-04-12 | 2019-10-25 | 台湾积体电路制造股份有限公司 | 封装件及其形成方法 |
CN111128904A (zh) * | 2018-10-30 | 2020-05-08 | 台湾积体电路制造股份有限公司 | 封装结构、管芯及其制造方法 |
CN111276468A (zh) * | 2018-12-05 | 2020-06-12 | 台湾积体电路制造股份有限公司 | 半导体结构及其形成方法 |
CN113078125A (zh) * | 2020-03-12 | 2021-07-06 | 台湾积体电路制造股份有限公司 | 管芯堆叠件的形成方法及管芯堆叠结构 |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10685934B2 (en) * | 2017-07-10 | 2020-06-16 | Advanced Semiconductor Engineering, Inc. | Semiconductor package device and method of manufacturing the same |
US10629559B2 (en) * | 2018-09-19 | 2020-04-21 | Powertech Technology Inc. | Semiconductor package and manufacturing method thereof |
US11121089B2 (en) * | 2018-11-30 | 2021-09-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit package and method |
US11309222B2 (en) * | 2019-08-29 | 2022-04-19 | Advanced Micro Devices, Inc. | Semiconductor chip with solder cap probe test pads |
FR3126258A1 (fr) * | 2021-08-20 | 2023-02-24 | Stmicroelectronics (Crolles 2) Sas | Structure d'interconnexion d’un circuit intégré |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20110084370A1 (en) * | 2009-10-14 | 2011-04-14 | Advanced Semiconductor Engineering, Inc. | Semiconductor package and process for fabricating same |
CN102054790A (zh) * | 2009-10-29 | 2011-05-11 | 台湾积体电路制造股份有限公司 | 半导体元件及其制造方法 |
CN103219281A (zh) * | 2013-05-03 | 2013-07-24 | 华进半导体封装先导技术研发中心有限公司 | 一种tsv背面露头工艺 |
US20150311144A1 (en) * | 2013-03-09 | 2015-10-29 | Adventive Ipbank | Low-Profile Footed Power Package |
CN105448755A (zh) * | 2016-01-15 | 2016-03-30 | 中芯长电半导体(江阴)有限公司 | 一种铜柱凸点的封装方法及封装结构 |
US20160276235A1 (en) * | 2015-03-16 | 2016-09-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure for die probing |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6291891B1 (en) * | 1998-01-13 | 2001-09-18 | Kabushiki Kaisha Toshiba | Semiconductor device manufacturing method and semiconductor device |
US8791579B2 (en) * | 2011-11-17 | 2014-07-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Adjusting sizes of connectors of package components |
CN104662643B (zh) * | 2012-06-13 | 2016-03-30 | 三菱瓦斯化学株式会社 | 清洗用液态组合物、半导体元件的清洗方法、以及半导体元件的制造方法 |
US10446522B2 (en) * | 2015-04-16 | 2019-10-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods of forming multiple conductive features in semiconductor devices in a same formation process |
US9735071B2 (en) * | 2015-08-25 | 2017-08-15 | International Business Machines Corporation | Method of forming a temporary test structure for device fabrication |
US9899342B2 (en) * | 2016-03-15 | 2018-02-20 | Taiwan Semiconductor Manufacturing Co., Ltd. | Integrated fan-out package, redistribution circuit structure, and method of fabricating the same |
US9871009B2 (en) * | 2016-06-15 | 2018-01-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and method |
US9852985B1 (en) * | 2016-06-27 | 2017-12-26 | Taiwan Semiconductor Manufacturing Co., Ltd. | Conductive terminal on integrated circuit |
-
2017
- 2017-07-03 US US15/640,942 patent/US10186462B2/en active Active
- 2017-10-24 TW TW106136437A patent/TWI749088B/zh active
- 2017-10-24 CN CN201711002107.XA patent/CN108122880B/zh active Active
-
2019
- 2019-01-21 US US16/253,109 patent/US10867874B2/en active Active
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20110084370A1 (en) * | 2009-10-14 | 2011-04-14 | Advanced Semiconductor Engineering, Inc. | Semiconductor package and process for fabricating same |
CN102054790A (zh) * | 2009-10-29 | 2011-05-11 | 台湾积体电路制造股份有限公司 | 半导体元件及其制造方法 |
US20150311144A1 (en) * | 2013-03-09 | 2015-10-29 | Adventive Ipbank | Low-Profile Footed Power Package |
CN103219281A (zh) * | 2013-05-03 | 2013-07-24 | 华进半导体封装先导技术研发中心有限公司 | 一种tsv背面露头工艺 |
US20160276235A1 (en) * | 2015-03-16 | 2016-09-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure for die probing |
CN105448755A (zh) * | 2016-01-15 | 2016-03-30 | 中芯长电半导体(江阴)有限公司 | 一种铜柱凸点的封装方法及封装结构 |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN110379719A (zh) * | 2018-04-12 | 2019-10-25 | 台湾积体电路制造股份有限公司 | 封装件及其形成方法 |
CN110379719B (zh) * | 2018-04-12 | 2021-04-02 | 台湾积体电路制造股份有限公司 | 封装件及其形成方法 |
US10971442B2 (en) | 2018-04-12 | 2021-04-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device having via sidewall adhesion with encapsulant |
US11527466B2 (en) | 2018-04-12 | 2022-12-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device having via sidewall adhesion with encapsulant |
CN111128904A (zh) * | 2018-10-30 | 2020-05-08 | 台湾积体电路制造股份有限公司 | 封装结构、管芯及其制造方法 |
CN111276468A (zh) * | 2018-12-05 | 2020-06-12 | 台湾积体电路制造股份有限公司 | 半导体结构及其形成方法 |
US11894309B2 (en) | 2018-12-05 | 2024-02-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | System on integrated chips (SoIC) and semiconductor structures with integrated SoIC |
CN113078125A (zh) * | 2020-03-12 | 2021-07-06 | 台湾积体电路制造股份有限公司 | 管芯堆叠件的形成方法及管芯堆叠结构 |
Also Published As
Publication number | Publication date |
---|---|
CN108122880B (zh) | 2022-10-28 |
US20180151453A1 (en) | 2018-05-31 |
US20190214317A1 (en) | 2019-07-11 |
US10867874B2 (en) | 2020-12-15 |
TW201820464A (zh) | 2018-06-01 |
TWI749088B (zh) | 2021-12-11 |
US10186462B2 (en) | 2019-01-22 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN108122880A (zh) | 半导体装置的制造方法 | |
US11189603B2 (en) | Semiconductor packages and methods of forming same | |
US10720409B2 (en) | Semiconductor packages with thermal-electrical-mechanical chips and methods of forming the same | |
CN107808870B (zh) | 半导体封装件中的再分布层及其形成方法 | |
CN107342277B (zh) | 封装件及其形成方法 | |
TWI708291B (zh) | 半導體封裝及其製造方法 | |
CN105374693B (zh) | 半导体封装件及其形成方法 | |
CN108010854B (zh) | 封装件及其形成方法 | |
CN109786268B (zh) | 半导体封装件中的金属化图案及其形成方法 | |
CN109585404A (zh) | 半导体封装及其形成方法 | |
CN1976014B (zh) | 半导体器件及其制造方法 | |
CN109786350B (zh) | 半导体封装件和方法 | |
CN107871718A (zh) | 半导体封装件及其形成方法 | |
CN108122857A (zh) | 封装结构 | |
CN109216296A (zh) | 半导体封装件和方法 | |
CN107665887A (zh) | 封装结构及其形成方法 | |
CN108987380A (zh) | 半导体封装件中的导电通孔及其形成方法 | |
CN107689333A (zh) | 半导体封装件及其形成方法 | |
CN109786360B (zh) | 半导体封装件和方法 | |
CN110970312B (zh) | 封装件及其形成方法 | |
CN106057760A (zh) | 半导体器件及其形成方法 | |
US11164855B2 (en) | Package structure with a heat dissipating element and method of manufacturing the same | |
US20210351111A1 (en) | Semiconductor device and manufacturing method thereof | |
CN111261608B (zh) | 半导体器件及其形成方法 | |
US20170301651A1 (en) | Wafer level system in package (sip) using a reconstituted wafer and method of making |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |