JP5808522B2 - シリコンを含有するエピタキシャル層の形成 - Google Patents

シリコンを含有するエピタキシャル層の形成 Download PDF

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Publication number
JP5808522B2
JP5808522B2 JP2009541510A JP2009541510A JP5808522B2 JP 5808522 B2 JP5808522 B2 JP 5808522B2 JP 2009541510 A JP2009541510 A JP 2009541510A JP 2009541510 A JP2009541510 A JP 2009541510A JP 5808522 B2 JP5808522 B2 JP 5808522B2
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JP
Japan
Prior art keywords
silicon
source
substrate
deposition
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
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JP2009541510A
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English (en)
Japanese (ja)
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JP2010512669A (ja
JP2010512669A5 (enExample
Inventor
ツィユアン イェ，
ツィユアン イェ，
アンドリュー ラム，
アンドリュー ラム，
イーワン キム，
イーワン キム，
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Applied Materials Inc
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Applied Materials Inc
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Publication of JP2010512669A5 publication Critical patent/JP2010512669A5/ja
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Publication of JP5808522B2 publication Critical patent/JP5808522B2/ja
Expired - Fee Related legal-status Critical Current
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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02529—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/0257—Doping during depositing
    • H01L21/02573—Conductivity type
    • H01L21/02576—N-type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/0257—Doping during depositing
    • H01L21/02573—Conductivity type
    • H01L21/02579—P-type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/027—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs
    • H10D30/0275—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs forming single crystalline semiconductor source or drain regions resulting in recessed gates, e.g. forming raised source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
    • H10D30/608—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs  having non-planar bodies, e.g. having recessed gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H10D30/797—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions being in source or drain regions, e.g. SiGe source or drain

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Chemical Vapour Deposition (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Recrystallisation Techniques (AREA)
JP2009541510A 2006-12-12 2007-12-11 シリコンを含有するエピタキシャル層の形成 Expired - Fee Related JP5808522B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/609,590 2006-12-12
US11/609,590 US20080138955A1 (en) 2006-12-12 2006-12-12 Formation of epitaxial layer containing silicon
PCT/US2007/087050 WO2008073926A2 (en) 2006-12-12 2007-12-11 Formation of epitaxial layers containing silicon

Publications (3)

Publication Number Publication Date
JP2010512669A JP2010512669A (ja) 2010-04-22
JP2010512669A5 JP2010512669A5 (enExample) 2010-12-02
JP5808522B2 true JP5808522B2 (ja) 2015-11-10

Family

ID=39498580

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009541510A Expired - Fee Related JP5808522B2 (ja) 2006-12-12 2007-12-11 シリコンを含有するエピタキシャル層の形成

Country Status (6)

Country Link
US (1) US20080138955A1 (enExample)
JP (1) JP5808522B2 (enExample)
KR (1) KR101432150B1 (enExample)
CN (2) CN104599945B (enExample)
TW (1) TWI383435B (enExample)
WO (1) WO2008073926A2 (enExample)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101470659B1 (ko) * 2006-09-07 2014-12-08 액테리온 파마슈티칼 리미티드 면역조절제로서 피리딘-4-일 유도체
US8288554B2 (en) * 2006-09-08 2012-10-16 Actelion Pharmaceuticals Ltd. Pyridin-3-yl derivatives as immunomodulating agents
US7833883B2 (en) * 2007-03-28 2010-11-16 Intel Corporation Precursor gas mixture for depositing an epitaxial carbon-doped silicon film
US7994015B2 (en) * 2009-04-21 2011-08-09 Applied Materials, Inc. NMOS transistor devices and methods for fabricating same
US8999798B2 (en) * 2009-12-17 2015-04-07 Applied Materials, Inc. Methods for forming NMOS EPI layers
DE102010055564A1 (de) * 2010-12-23 2012-06-28 Johann-Wolfgang-Goethe Universität Frankfurt am Main Verfahren und Vorrichtung zur Abscheidung von Silizium auf einem Substrat
WO2012102755A1 (en) * 2011-01-28 2012-08-02 Applied Materials, Inc. Carbon addition for low resistivity in situ doped silicon epitaxy
TWI521600B (zh) * 2011-06-03 2016-02-11 應用材料股份有限公司 在矽基材上形成高生長速率低電阻率的鍺膜之方法〈一〉
KR101371435B1 (ko) 2012-01-04 2014-03-12 주식회사 유진테크 처리유닛을 포함하는 기판 처리 장치
KR101677560B1 (ko) 2014-03-18 2016-11-18 주식회사 유진테크 공정공간 높이별 가열온도를 조절할 수 있는 히터를 구비한 기판 처리 장치
RU2618279C1 (ru) * 2016-06-23 2017-05-03 Акционерное общество "Эпиэл" Способ изготовления эпитаксиального слоя кремния на диэлектрической подложке
US11018002B2 (en) * 2017-07-19 2021-05-25 Asm Ip Holding B.V. Method for selectively depositing a Group IV semiconductor and related semiconductor device structures
US11374112B2 (en) * 2017-07-19 2022-06-28 Asm Ip Holding B.V. Method for depositing a group IV semiconductor and related semiconductor device structures
US11404270B2 (en) * 2018-11-30 2022-08-02 Texas Instruments Incorporated Microelectronic device substrate formed by additive process
US10861715B2 (en) 2018-12-28 2020-12-08 Texas Instruments Incorporated 3D printed semiconductor package
US10910465B2 (en) 2018-12-28 2021-02-02 Texas Instruments Incorporated 3D printed semiconductor package
KR102189557B1 (ko) * 2019-03-05 2020-12-11 에스케이머티리얼즈 주식회사 박막 트랜지스터 및 이의 제조방법
EP3832696A1 (en) * 2019-12-06 2021-06-09 Imec VZW Formation of a sige(:b):ga layer
TW202208659A (zh) * 2020-06-16 2022-03-01 荷蘭商Ａｓｍ Ｉｐ私人控股有限公司 沉積含硼之矽鍺層的方法
JP7703376B2 (ja) * 2020-06-24 2025-07-07 エーエスエム・アイピー・ホールディング・ベー・フェー シリコンを備える層を形成するための方法
CN115491655A (zh) * 2022-10-05 2022-12-20 江苏筑磊电子科技有限公司 一种半导体技术中用于低温清洁和沉积的微波等离子辅助方法

Family Cites Families (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07118452B2 (ja) * 1986-03-08 1995-12-18 日新電機株式会社 シリコンエピタキシヤル成長方法
CA2011563C (en) * 1989-03-08 1994-05-10 Kiyoshi Nakata Power conversion system
US5108792A (en) * 1990-03-09 1992-04-28 Applied Materials, Inc. Double-dome reactor for semiconductor processing
US5322813A (en) * 1992-08-31 1994-06-21 International Business Machines Corporation Method of making supersaturated rare earth doped semiconductor layers by chemical vapor deposition
KR100224707B1 (ko) * 1995-12-23 1999-10-15 윤종용 반도체 장치 커패시터의 제조방법
KR100200705B1 (ko) * 1996-06-08 1999-06-15 윤종용 반도체 디바이스 제조장치, 제조장치의 공정 조건 조절방법 및 이를 이용한 커패시터 제조방법
US6083321A (en) * 1997-07-11 2000-07-04 Applied Materials, Inc. Fluid delivery system and method
WO1999045167A1 (en) * 1998-03-06 1999-09-10 Asm America, Inc. Method of depositing silicon with high step coverage
DE60033656T2 (de) * 2000-03-03 2007-06-21 Matsushita Electric Industrial Co., Ltd., Kadoma Halbleiteranordnung
WO2002080244A2 (en) * 2001-02-12 2002-10-10 Asm America, Inc. Improved process for deposition of semiconductor films
US6916398B2 (en) * 2001-10-26 2005-07-12 Applied Materials, Inc. Gas delivery apparatus and method for atomic layer deposition
US6897131B2 (en) * 2002-09-20 2005-05-24 Applied Materials, Inc. Advances in spike anneal processes for ultra shallow junctions
US6803297B2 (en) * 2002-09-20 2004-10-12 Applied Materials, Inc. Optimal spike anneal ambient
US7540920B2 (en) * 2002-10-18 2009-06-02 Applied Materials, Inc. Silicon-containing layer deposition with silicon compounds
CN100471991C (zh) * 2002-10-18 2009-03-25 应用材料有限公司 采用硅化合物进行的含硅层沉积
US6998153B2 (en) * 2003-01-27 2006-02-14 Applied Materials, Inc. Suppression of NiSi2 formation in a nickel salicide process using a pre-silicide nitrogen plasma
TWI336102B (en) * 2003-03-13 2011-01-11 Asm Inc Epitaxial semiconductor deposition methods and structures
US7132338B2 (en) * 2003-10-10 2006-11-07 Applied Materials, Inc. Methods to fabricate MOSFET devices using selective deposition process
US7166528B2 (en) * 2003-10-10 2007-01-23 Applied Materials, Inc. Methods of selective deposition of heavily doped epitaxial SiGe
US7560352B2 (en) * 2004-12-01 2009-07-14 Applied Materials, Inc. Selective deposition
US7312128B2 (en) * 2004-12-01 2007-12-25 Applied Materials, Inc. Selective epitaxy process with alternating gas supply
US7682940B2 (en) * 2004-12-01 2010-03-23 Applied Materials, Inc. Use of Cl2 and/or HCl during silicon epitaxial film formation
US7816236B2 (en) * 2005-02-04 2010-10-19 Asm America Inc. Selective deposition of silicon-containing films
JP2006294953A (ja) * 2005-04-13 2006-10-26 Elpida Memory Inc 半導体装置の製造方法及び製造装置
US7648853B2 (en) * 2006-07-11 2010-01-19 Asm America, Inc. Dual channel heterostructure

Also Published As

Publication number Publication date
JP2010512669A (ja) 2010-04-22
KR20090088431A (ko) 2009-08-19
TWI383435B (zh) 2013-01-21
CN104599945A (zh) 2015-05-06
TW200834667A (en) 2008-08-16
CN101548363A (zh) 2009-09-30
CN104599945B (zh) 2017-11-28
US20080138955A1 (en) 2008-06-12
KR101432150B1 (ko) 2014-08-20
WO2008073926A3 (en) 2009-01-15
WO2008073926A2 (en) 2008-06-19

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