JP5779068B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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Description
本発明の実施の形態による不揮発性メモリセルを有する半導体装置の製造方法の一例を図1〜図27を用いて工程順に説明する。図1〜図15および図18〜図27は本実施の形態による半導体装置の製造工程中における周辺回路領域(nMIS領域およびpMIS領域)、スクライブ領域(周辺回路用マーク領域(第2領域)およびメモリ用マーク領域(第1領域))、メモリセル領域(本体セル領域およびダミーセル領域)、および容量素子領域の要部断面図である。周辺回路領域にはnMISおよびpMISのゲート長方向の断面図を示し、メモリセル領域には選択用nMISおよびメモリ用nMISから構成される不揮発性メモリセルのゲート長方向の断面図を示している。図16は本実施の形態による半導体装置の概略平面図であり、周辺回路領域のゲート電極、スクライブ領域のマークパターン、およびメモリセル領域の選択ゲート電極を形成した後に、これらを平面視したとき概略平面図、図17は本願発明が適用される前の半導体装置の概略平面図であり、周辺回路領域のゲート電極、スクライブ領域のマークパターン、およびメモリセル領域の選択ゲート電極を形成した後に、これらを平面視したときの概略平面図である。
2ad,2as 半導体領域
2b n+型の半導体領域
3 シリサイド層
4 ゲート絶縁膜(第1ゲート絶縁膜)
5 半導体領域
6b,6t 絶縁膜
8 半導体領域
9 層間絶縁膜
9a 窒化シリコン膜
9b 酸化シリコン膜
10 導電膜(第1導電膜)
10E 下部電極(第1導電膜)
10na n型の導電膜(第1導電膜)
10n n型の導電膜(第1導電膜)
10p p型の導電膜(第1導電膜)
11 サイドウォール(第2導電膜)
11E 上部電極(第2導電膜)
12 下層レジスト膜
13 レジスト中間層
14 上層レジスト膜
15 サイドウォール
16 フォトレジストパターン
17 フォトレジストパターン
18 n−型の半導体領域
19 p−型の半導体領域
20 フォトレジストパターン
21 p+型の半導体領域
22 フォトレジストパターン
23 n+型の半導体領域
24 酸化シリコン膜
25 窒化シリコン膜
ACT 活性領域
CA,CB,CNT コンタクトホール
CG 選択ゲート電極
CSL 電荷蓄積層
Dc チャネル形成用の半導体領域
Drm ドレイン領域
Gn,Gp ゲート電極
M1 第1層配線
MG メモリゲート電極
MP1 周辺回路用マークパターン
MP2,MP3 メモリ用マークパターン
NISO 埋め込みウェル
NW nウェル
PA,PB,PLG プラグ
PW pウェル
RP1,RP2,RP3,RP4,RP5 フォトレジストパターン
SD ソース・ドレイン領域
Srm ソース領域
STI 素子分離部
SW サイドウォール
Claims (4)
- 複数のメモリセルが形成されたメモリマットを備えるメモリセル領域と、周辺回路領域と、スクライブ領域とを有する半導体装置の製造方法であって、
(a)前記メモリセル領域の半導体基板の主面に第1ゲート絶縁膜を形成する工程と、
(b)前記メモリセル領域の前記第1ゲート絶縁膜上に第1導電膜および絶縁膜を順次形成する工程と、
(c)前記絶縁膜および前記第1導電膜を順次加工することによって、前記メモリセル領域に、前記第1導電膜からなる選択ゲート電極および前記絶縁膜の積層膜から構成される複数の第1パターンを第1方向に沿って形成する工程と、
(d)前記(c)工程の後、前記第1方向と直交する第2方向で、前記メモリマットの最も外側に位置する前記第1パターンの上部を構成する前記絶縁膜を除去して、前記メモリマットの前記第2方向の最も外側に、前記選択ゲート電極から構成される第2パターンを形成する工程と、
(e)前記(d)工程の後、前記半導体基板の主面上に、前記メモリセル領域の前記第1パターンおよび前記第2パターンを覆う第2ゲート絶縁膜を形成する工程と、
(f)前記第2ゲート絶縁膜上に第2導電膜を形成する工程と、
(g)前記第2導電膜に対して異方性エッチングを施すことにより、前記第1パターンの両側面および前記第2パターンの両側面に前記第2導電膜を残存させる工程と、
(h)前記第2導電膜の一部を除去して前記第1パターンの一方の側面および前記第2パターンの一方の側面に、前記第2導電膜からなるメモリゲート電極を形成する工程と、
を含み、さらに、
前記(b)工程では、前記スクライブ領域の第1領域に前記第1導電膜および前記絶縁膜を順次形成し、
前記(c)工程では、前記スクライブ領域の前記第1領域の前記絶縁膜および前記第1導電膜を順次加工することによって、前記スクライブ領域の前記第1領域に、前記第1導電膜および前記絶縁膜の積層膜から構成される第3パターンを形成し、
前記(d)工程では、前記第3パターンの上部を構成する前記絶縁膜を除去して、前記第1導電膜から構成され、前記複数のメモリセルを形成する際のフォトリソグラフィにおける合わせマークとして用いられる第4パターンを形成することを特徴とする半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
前記第2パターンの前記半導体基板の主面からの高さと前記第4パターンの前記半導体基板の主面からの高さとが同じであることを特徴とする半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、さらに、
前記(b)工程では、前記周辺回路領域、および前記スクライブ領域の第2領域に前記第1導電膜および前記絶縁膜を順次形成し、
前記(d)工程では、前記周辺回路領域、および前記スクライブ領域の前記第2領域の前記絶縁膜を除去し、
前記(h)工程の後、前記周辺回路領域、および前記スクライブ領域の前記第2領域の前記第1導電膜をそれぞれ加工して、前記周辺回路領域に電界効果トランジスタのゲート電極を形成し、前記スクライブ領域の前記第2領域に前記電界効果トランジスタを形成する際のフォトリソグラフィにおける合わせマークとして用いられる第5パターンを形成することを特徴とする半導体装置の製造方法。 - 請求項3記載の半導体装置の製造方法において、
前記第4パターンの前記半導体基板の主面からの高さと前記第5パターンの前記半導体基板の主面からの高さとは同じであることを特徴とする半導体装置の製造方法。
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JP2011219364A JP5779068B2 (ja) | 2011-10-03 | 2011-10-03 | 半導体装置の製造方法 |
US13/612,630 US8951860B2 (en) | 2011-10-03 | 2012-09-12 | Manufacturing method of semiconductor device |
TW101134916A TW201320245A (zh) | 2011-10-03 | 2012-09-24 | 半導體裝置的製造方法 |
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US8399310B2 (en) | 2010-10-29 | 2013-03-19 | Freescale Semiconductor, Inc. | Non-volatile memory and logic circuit process integration |
US8906764B2 (en) | 2012-01-04 | 2014-12-09 | Freescale Semiconductor, Inc. | Non-volatile memory (NVM) and logic integration |
US8951863B2 (en) | 2012-04-06 | 2015-02-10 | Freescale Semiconductor, Inc. | Non-volatile memory (NVM) and logic integration |
US9087913B2 (en) | 2012-04-09 | 2015-07-21 | Freescale Semiconductor, Inc. | Integration technique using thermal oxide select gate dielectric for select gate and apartial replacement gate for logic |
US9111865B2 (en) | 2012-10-26 | 2015-08-18 | Freescale Semiconductor, Inc. | Method of making a logic transistor and a non-volatile memory (NVM) cell |
US9006093B2 (en) | 2013-06-27 | 2015-04-14 | Freescale Semiconductor, Inc. | Non-volatile memory (NVM) and high voltage transistor integration |
US8877585B1 (en) * | 2013-08-16 | 2014-11-04 | Freescale Semiconductor, Inc. | Non-volatile memory (NVM) cell, high voltage transistor, and high-K and metal gate transistor integration |
US9129996B2 (en) | 2013-07-31 | 2015-09-08 | Freescale Semiconductor, Inc. | Non-volatile memory (NVM) cell and high-K and metal gate transistor integration |
US8871598B1 (en) | 2013-07-31 | 2014-10-28 | Freescale Semiconductor, Inc. | Non-volatile memory (NVM) and high-k and metal gate integration using gate-first methodology |
US9082837B2 (en) | 2013-08-08 | 2015-07-14 | Freescale Semiconductor, Inc. | Nonvolatile memory bitcell with inlaid high k metal select gate |
US9082650B2 (en) | 2013-08-21 | 2015-07-14 | Freescale Semiconductor, Inc. | Integrated split gate non-volatile memory cell and logic structure |
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US8901632B1 (en) | 2013-09-30 | 2014-12-02 | Freescale Semiconductor, Inc. | Non-volatile memory (NVM) and high-K and metal gate integration using gate-last methodology |
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US9343314B2 (en) | 2014-05-30 | 2016-05-17 | Freescale Semiconductor, Inc. | Split gate nanocrystal memory integration |
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US9257445B2 (en) | 2014-05-30 | 2016-02-09 | Freescale Semiconductor, Inc. | Method of making a split gate non-volatile memory (NVM) cell and a logic transistor |
JP6310802B2 (ja) * | 2014-07-28 | 2018-04-11 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
US9397176B2 (en) * | 2014-07-30 | 2016-07-19 | Freescale Semiconductor, Inc. | Method of forming split gate memory with improved reliability |
JP2016051740A (ja) * | 2014-08-28 | 2016-04-11 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
JP6501588B2 (ja) * | 2015-03-30 | 2019-04-17 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
US9748240B2 (en) * | 2015-06-22 | 2017-08-29 | Toshiba Memory Corporation | Semiconductor device including a boundary of conductivity in a substrate |
KR102411071B1 (ko) * | 2017-05-29 | 2022-06-21 | 삼성전자주식회사 | 반도체 장치 |
US10872898B2 (en) * | 2017-07-19 | 2020-12-22 | Cypress Semiconductor Corporation | Embedded non-volatile memory device and fabrication method of the same |
KR102524612B1 (ko) * | 2017-09-19 | 2023-04-24 | 삼성전자주식회사 | 정보 저장 소자 및 그 제조방법 |
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JP2819972B2 (ja) | 1992-11-10 | 1998-11-05 | 日本電気株式会社 | 半導体装置の製造方法 |
JPH11121327A (ja) * | 1997-10-09 | 1999-04-30 | Nec Corp | 半導体装置及びその製造方法 |
JP2000022103A (ja) * | 1998-06-29 | 2000-01-21 | Sanyo Electric Co Ltd | 半導体装置とその製造方法 |
JP3726760B2 (ja) * | 2002-02-20 | 2005-12-14 | セイコーエプソン株式会社 | 半導体装置の製造方法 |
JP4758625B2 (ja) * | 2004-08-09 | 2011-08-31 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP4947931B2 (ja) * | 2004-08-12 | 2012-06-06 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP2009054707A (ja) * | 2007-08-24 | 2009-03-12 | Renesas Technology Corp | 半導体記憶装置およびその製造方法 |
JP5425437B2 (ja) * | 2008-09-30 | 2014-02-26 | ルネサスエレクトロニクス株式会社 | 不揮発性半導体記憶装置 |
WO2010082328A1 (ja) * | 2009-01-15 | 2010-07-22 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
JP5554973B2 (ja) * | 2009-12-01 | 2014-07-23 | ルネサスエレクトロニクス株式会社 | 半導体集積回路装置の製造方法 |
JP2010219541A (ja) * | 2010-04-20 | 2010-09-30 | Renesas Electronics Corp | 半導体装置およびその製造方法 |
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