JP5716749B2 - 半導体装置 - Google Patents
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- JP5716749B2 JP5716749B2 JP2012534055A JP2012534055A JP5716749B2 JP 5716749 B2 JP5716749 B2 JP 5716749B2 JP 2012534055 A JP2012534055 A JP 2012534055A JP 2012534055 A JP2012534055 A JP 2012534055A JP 5716749 B2 JP5716749 B2 JP 5716749B2
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- 239000004065 semiconductor Substances 0.000 title claims description 89
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- 239000012535 impurity Substances 0.000 claims description 35
- 230000002093 peripheral effect Effects 0.000 claims description 17
- 239000002344 surface layer Substances 0.000 claims description 11
- 239000000758 substrate Substances 0.000 claims description 3
- 230000015556 catabolic process Effects 0.000 description 34
- 238000010586 diagram Methods 0.000 description 20
- 230000001965 increasing effect Effects 0.000 description 14
- 230000006378 damage Effects 0.000 description 4
- 230000005684 electric field Effects 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 4
- 230000017525 heat dissipation Effects 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000002485 combustion reaction Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
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- 238000012986 modification Methods 0.000 description 1
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- 230000003071 parasitic effect Effects 0.000 description 1
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- H01L29/083—Anode or cathode regions of thyristors or gated bipolar-mode devices
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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Description
は、第1導電型の第1の半導体層と、前記第1の半導体層の表面に設けられた第2導電型の第2の半導体層と、前記第2の半導体層の表面に設けられ、かつ該第2の半導体層より低い不純物濃度を有する第2導電型の第3の半導体層と、前記第3の半導体層の表面層に選択的に設けられた第1導電型の第1の半導体領域と、前記第1の半導体領域の表面層に選択的に設けられた第2導電型の第2の半導体領域と、前記第3の半導体層と前記第2の半導体領域に挟まれた前記第1の半導体領域の表面に、絶縁膜を介して設けられた第1の電極と、前記第1の半導体領域および前記第2の半導体領域に接する第2の電極と、前記第1の半導体層の、前記第3の半導体層が設けられた表面に対して反対側の表面に設けられた第3の電極と、前記第2の半導体層より高い不純物濃度を有し、かつ、前記第2の半導体層を貫通して前記第1の半導体層および前記第3の半導体層に接して前記第2の半導体層と交互に繰り返し設けられる、当該第2の半導体層と同一の厚さの第2導電型の第1の低抵抗層と、を備え、前記第1の低抵抗層の不純物濃度は、7×10 16 cm -3 以上で7×10 17 cm -3 以下であり、基板の外周端部には、前記第1の低抵抗層を配置せず、前記第2の半導体層を配置することを特徴とする。
図1は、実施の形態1にかかる半導体装置の要部を示す断面図である。図1に示す半導体装置は、縦型のIGBT(絶縁ゲート型バイポーラトランジスタ)である。図1に示すIGBTは紙面右側にメインIGBTが形成され、n-ドリフト層(第3の半導体層)1の表面層に、pベース領域(第1の半導体領域)2が選択的に設けられている。pベース領域2の表面層には、n+エミッタ領域(第2の半導体領域)3が選択的に設けられている。
図2は、実施の形態2にかかる半導体装置の要部を示す断面図である。n+バッファ層より高い濃度を有するn++半導体層(以下、n++バッファ層とする)を、n+バッファ層と交互に設けてもよい。
図3は、実施の形態3にかかる半導体装置の要部を示す断面図である。n+バッファ層を設けずに、かつp++コレクタ層にn++半導体層(以下、n++コレクタ層とする)を設けてもよい。
図5は、チップサイズとフィールドディケイサージによる印加電圧との関係を示す特性図である。まず、実施の形態1に従い、チップサイズを種々変更して複数のIGBTを作製した(以下、実施例とする)。各実施例では、n+バッファ層9の不純物濃度および厚さを、それぞれ9.2×1016cm-3および18μmとした。比較として、従来のIGBTを作製した(図14参照。以下、従来例とする)。従来例では、n+バッファ層の不純物濃度および厚さを5.4×1016cm-3および30μmとした。それ以外の構成は実施例と同様である。そして、これらのIGBTに対して、上述したように、フィールドディケイ試験を行った(図9〜図11参照)。試験条件は、上述した試験条件と同様である。
図6は、バッファ層の不純物濃度と逆方向耐圧の関係について示す特性図である。実施の形態1に従い、IGBTを2つ作製した(以下、第1,2の実施例とする)。第1の実施例では、n+バッファ層の不純物濃度を7.1×1016cm-3とした。第2の実施例では、n+バッファ層の不純物濃度を9.2×1016cm-3とした。また、第1,2実施例ともに、n+バッファ層の厚さを18μmとした。比較として、実施例1と同様に従来例を作製した。そして、第1,2実施例および従来例に対して、実施例1と同様に、フィールドディケイ試験を行った。
図7は、バッファ層の不純物濃度とフィールドディケイサージによる印加電圧の関係について示す特性図である。実施例2と同様に、第1,2の実施例および従来例を作製した。そして、第1,2実施例および従来例に対して、実施例1と同様に、フィールドディケイ試験を行った。
図8は、バッファ層の不純物濃度とESB耐量の関係について示す特性図である。まず、実施の形態1に従い、n+バッファ層の厚さの異なる複数のIGBTを作製した(第3の実施例とする)。第3の実施例のそれ以外の構成は、第1の実施例と同様である。そして、第3の実施例に対して、実施例1と同様に、フィールドディケイ試験を行った。
2 pベース領域
3 n+エミッタ領域
4 ゲート絶縁膜
5 ゲート電極
6 層間絶縁膜
7 エミッタ電極
8 酸化膜
9 n+バッファ層
10 pコレクタ層
11 コレクタ電極
t1 n+バッファ層の厚さ
Claims (1)
- 第1導電型の第1の半導体層と、
前記第1の半導体層の表面に設けられた第2導電型の第2の半導体層と、
前記第2の半導体層の表面に設けられ、かつ該第2の半導体層より低い不純物濃度を有する第2導電型の第3の半導体層と、
前記第3の半導体層の表面層に選択的に設けられた第1導電型の第1の半導体領域と、
前記第1の半導体領域の表面層に選択的に設けられた第2導電型の第2の半導体領域と、
前記第3の半導体層と前記第2の半導体領域に挟まれた前記第1の半導体領域の表面に、絶縁膜を介して設けられた第1の電極と、
前記第1の半導体領域および前記第2の半導体領域に接する第2の電極と、
前記第1の半導体層の、前記第3の半導体層が設けられた表面に対して反対側の表面に設けられた第3の電極と、
前記第2の半導体層より高い不純物濃度を有し、かつ、前記第2の半導体層を貫通して前記第1の半導体層および前記第3の半導体層に接して前記第2の半導体層と交互に繰り返し設けられる、当該第2の半導体層と同一の厚さの第2導電型の第1の低抵抗層と、
を備え、
前記第1の低抵抗層の不純物濃度は、7×10 16 cm -3 以上で7×10 17 cm -3 以下であり、
基板の外周端部には、前記第1の低抵抗層を配置せず、前記第2の半導体層を配置することを特徴とする半導体装置。
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JP2012534055A JP5716749B2 (ja) | 2010-09-17 | 2011-09-15 | 半導体装置 |
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PCT/JP2011/071154 WO2012036247A1 (ja) | 2010-09-17 | 2011-09-15 | 半導体装置 |
JP2012534055A JP5716749B2 (ja) | 2010-09-17 | 2011-09-15 | 半導体装置 |
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Families Citing this family (4)
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JP2015028969A (ja) * | 2013-07-30 | 2015-02-12 | 本田技研工業株式会社 | 半導体装置 |
CN105940496B (zh) | 2014-01-29 | 2019-06-18 | 三菱电机株式会社 | 电力用半导体装置 |
JP6707930B2 (ja) * | 2016-03-18 | 2020-06-10 | 富士電機株式会社 | スイッチ装置および点火装置 |
JP7024277B2 (ja) | 2017-09-20 | 2022-02-24 | 株式会社デンソー | 半導体装置 |
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JPH05114606A (ja) * | 1991-10-24 | 1993-05-07 | Fuji Electric Co Ltd | 絶縁ゲート型バイポーラトランジスタ |
JPH05152574A (ja) * | 1991-11-29 | 1993-06-18 | Fuji Electric Co Ltd | 半導体装置 |
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JP4797445B2 (ja) | 2005-05-24 | 2011-10-19 | 株式会社デンソー | 絶縁ゲート型バイポーラトランジスタ |
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JP5157201B2 (ja) * | 2006-03-22 | 2013-03-06 | 株式会社デンソー | 半導体装置 |
JP5298521B2 (ja) | 2007-10-15 | 2013-09-25 | 富士電機株式会社 | 半導体装置 |
JP5332175B2 (ja) * | 2007-10-24 | 2013-11-06 | 富士電機株式会社 | 制御回路を備える半導体装置 |
US9385196B2 (en) * | 2012-09-12 | 2016-07-05 | Texas Instruments Incorporated | Fast switching IGBT with embedded emitter shorting contacts and method for making same |
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2011
- 2011-09-15 JP JP2012534055A patent/JP5716749B2/ja active Active
- 2011-09-15 WO PCT/JP2011/071154 patent/WO2012036247A1/ja active Application Filing
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2013
- 2013-02-13 US US13/766,424 patent/US9035351B2/en active Active
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2014
- 2014-06-16 JP JP2014123863A patent/JP5943037B2/ja active Active
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JPH01282872A (ja) * | 1988-05-09 | 1989-11-14 | Matsushita Electron Corp | 半導体装置 |
JPH04320377A (ja) * | 1991-04-19 | 1992-11-11 | Fuji Electric Co Ltd | 絶縁ゲート型バイポーラトランジスタ |
JPH05114606A (ja) * | 1991-10-24 | 1993-05-07 | Fuji Electric Co Ltd | 絶縁ゲート型バイポーラトランジスタ |
JPH05152574A (ja) * | 1991-11-29 | 1993-06-18 | Fuji Electric Co Ltd | 半導体装置 |
JPH06318706A (ja) * | 1993-03-08 | 1994-11-15 | Fuji Electric Co Ltd | 半導体装置 |
JPH07211895A (ja) * | 1994-01-12 | 1995-08-11 | Sanken Electric Co Ltd | 伝導度変調型電界効果トランジスタ |
JPH08288503A (ja) * | 1995-04-11 | 1996-11-01 | Rohm Co Ltd | プレーナ型高耐圧縦型素子を有する半導体装置およびその製造方法 |
JPH1197715A (ja) * | 1997-09-19 | 1999-04-09 | Toshiba Corp | 半導体装置 |
JP2009130096A (ja) * | 2007-11-22 | 2009-06-11 | Fuji Electric Device Technology Co Ltd | 制御回路を備える半導体装置 |
JP2009283818A (ja) * | 2008-05-26 | 2009-12-03 | Sanken Electric Co Ltd | 半導体装置およびその製造方法 |
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US20130153955A1 (en) | 2013-06-20 |
JP2014197699A (ja) | 2014-10-16 |
US9035351B2 (en) | 2015-05-19 |
WO2012036247A1 (ja) | 2012-03-22 |
JP5943037B2 (ja) | 2016-06-29 |
JPWO2012036247A1 (ja) | 2014-02-03 |
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