JP5695294B2 - コンプライアント端子の取付け具を有する超小型電子素子および該超小型電子素子を作製する方法 - Google Patents
コンプライアント端子の取付け具を有する超小型電子素子および該超小型電子素子を作製する方法 Download PDFInfo
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- JP5695294B2 JP5695294B2 JP2008548666A JP2008548666A JP5695294B2 JP 5695294 B2 JP5695294 B2 JP 5695294B2 JP 2008548666 A JP2008548666 A JP 2008548666A JP 2008548666 A JP2008548666 A JP 2008548666A JP 5695294 B2 JP5695294 B2 JP 5695294B2
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
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- H—ELECTRICITY
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- H01L2924/01—Chemical elements
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- H01L2924/013—Alloys
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- H—ELECTRICITY
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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Description
本出願は、2005年12月27日に出願された米国特許出願第11/318,846号の継続出願であり、その内容は、参照することによって、ここに含まれるものとする。
半導体チップは、一般的に、ウエハと呼ばれる大きな平坦体の半導体材料を処理し、単一チップに組み込まれることになる電子回路をそれぞれ備える多数の領域を形成し、次いで、ウエハを鋸レーンに沿って切断し、個々のチップに分断することによって、形成される。各チップは、典型的には、略平面的な前面および後面、およびこれらの面の境界において前面と後面との間に延在する小さい縁を有する平坦な矩形体である。各チップは、典型的には、前面に露出した接点を有し、これらの接点は、チップ内の回路に電気的に接続されている。
Claims (31)
- (a)間隙を介してバンプを複数含む誘電体構造を、前記誘電体構造の第1の表面がモールドの作用面によって形作られるように、そして、前記第1の表面が、各々のバンプ上のパッド領域とパッド領域から突出するポストを含むように、形成するステップと、
(b)前記誘電体構造を1つまたは複数のチップ領域を備えるウエハ素子の表面に転移させるステップであって、前記誘電体構造の前記第1の表面が前記ウエハ素子から離れる方を向くと共に前記誘電体構造の第2の表面が前記ウエハ素子の方を向くようする、転移させるステップと、
(c)各々の端子が、バンプ上のパッド領域を覆う導電性パッドと前記パッドから突出する導電性ポストを含むように、前記誘電体構造の前記第1の表面上に端子を設けるステップと、
(d)前記端子を前記ウエハ素子の接点に電気的に接続するステップと、
を含む、チップアセンブリを作製する方法。 - 前記形成ステップは、前記バンプの前記パッド領域から突出している誘電性ポストとともに前記バンプを設けることを含み、端子を設ける前記ステップは、前記誘電性ポスト上に前記導電性ポストを形成することを含むことを特徴とする請求項1に記載の方法。
- 前記誘電体構造は、前記バンプ間の間隙を含むことを特徴とする請求項1または請求項2に記載の方法。
- 前記バンプの少なくともいくつかは、前記誘電体構造の他の部分から離れた遊離バンプであり、前記方法は、前記形成ステップと前記転移ステップとの間に、前記遊離バンプを前記誘電体構造の前記他の部分に対して適所に維持するステップをさらに含むことを特徴とする請求項3に記載の方法。
- 前記誘電体構造は、前記遊離バンプのみから構成されることを特徴とする請求項4に記載の方法。
- 前記形成ステップは、前記誘電体構造内に前記第1の表面から離れて空洞を形成するように行われ、端子を設ける前記ステップは、前記端子の少なくともいくつかを前記空洞と一直線に並んで配置させるように行われることを特徴とする請求項1に記載の方法。
- 前記空洞の少なくともいくつかと連通する、前記チップアセンブリの外側に開口する通気孔を設けるステップをさらに含むことを特徴とする請求項6に記載の方法。
- 端子を設ける前記ステップは、金属層を前記モールドの前記作用面上に前記形成ステップ中に前記金属層が前記誘電体構造の前記第1の表面と前記モールドとの間に配置されるように設け、前記転移ステップ中に前記金属層を前記誘電体構造と共に転移させることを含むことを特徴とする請求項1に記載の方法。
- 端子を設ける前記ステップは、前記転移ステップの後、金属層を前記誘電体構造の前記第1の表面上に堆積させることを含むことを特徴とする請求項1に記載の方法。
- 金属層を堆積させる前記ステップは、前記金属層の部分を前記ウエハの前面および前記前面に露出した前記ウエハ素子の接点上に堆積させ、前記金属層を前記金属層が複数の個別の金属要素を含むようにパターニングさせることを含み、前記金属要素の各々は、前記誘電体構造上の端子および前記端子を前記ウエハ素子の接点に接続する配線を含むことを特徴とする請求項9に記載の方法。
- 前記金属層を堆積させる前記ステップは、実質的に連続する層を形成することを含み、前記パターニングステップは、前記個別の金属要素を形成するように、前記連続層を分割することを含むことを特徴とする請求項10に記載の方法。
- 前記金属層を堆積する前記ステップは、互いに分離した前記金属要素を形成するように、金属を選択的に堆積させることを含むことを特徴とする請求項10に記載の方法。
- 前記転移ステップは、前記形成ステップの後、前記モールドを前記モールドの前記誘電体構造が前記ウエハ素子の前記前面を覆うように配置し、前記誘電体構造の前記第2の表面を前記ウエハ素子の前記前面に接合させ、次いで、前記モールドを取り外すことを含むことを特徴とする請求項1に記載の方法。
- 前記モールドおよび前記ウエハ素子は、実質的に等しい熱膨張係数を有することを特徴とする請求項13に記載の方法。
- 前記形成ステップは、未硬化の流動性のある誘電体材料を前記作用面に堆積させ、次いで、前記誘電体材料を硬化させることを含むことを特徴とする請求項1に記載の方法。
- 前記作用面は、複数の凹部および前記凹部間のランド領域を備え、前記形成ステップは、前記硬化ステップが完了する前に、誘電体材料を前記ランド領域から取り除くことをさらに含むことを特徴とする請求項15に記載の方法。
- 前記硬化ステップは、前記未硬化の誘電体材料の一部が未硬化のまま維持されるように、前記未硬化の誘電体材料を放射エネルギーに選択的に露出させることを含み、前記形成ステップは、前記誘電体材料の前記未硬化の部分を取り除くことをさらに含むことを特徴とする請求項15に記載の方法。
- 前記形成ステップは、前記層を貫通する通気開口を形成することを含むことを特徴とする請求項1に記載の方法。
- 前記ウエハ素子は、複数のチップ領域を含み、前記方法は、複数のユニットを形成するために、前記転移ステップの後、前記ウエハおよび前記誘電体構造を分断するステップをさらに含み、前記複数のユニットの各々は、1つまたは複数の前記チップ領域および前記誘電体構造の一部を含むことを特徴とする請求項1に記載の方法。
- 本体および前記本体に支持された端子を備える超小型電子素子であって、前記端子の各々は、導電性パッドと、前記パッド上の導電性ポストとを備え、前記ポストは前記パッドよりも小さい直径を有し、前記ポストは前記本体から離れて上方に突出し、前記本体上に層をさらに備え、前記層は、前記パッドと一直線に並ぶ開口を有し、前記パッドは、前記開口を通して露出され、前記ポストは、前記層の上方に突出することを特徴とする超小型電子素子。
- 前記層は、半田マスク層であることを特徴とする請求項20に記載の超小型電子素子。
- 前記本体は、前面を有するチップと、前記チップの前記前面を覆う誘電体構造とを備え、前記端子は、前記誘電体構造に支持されることを特徴とする請求項20に記載の超小型電子素子。
- 前記誘電体構造は誘電体ポストを含み、前記導電性ポストは前記誘電体ポストを覆う導電性材料を含むことを特徴とする請求項22に記載の超小型電子素子。
- 前記誘電体構造は、前記チップから離れて上方に突出する複数のバンプを含み、前記端子の前記パッドは、前記端子の前記ポストが前記バンプから突出するように、前記バンプ上に配置されることを特徴とする請求項22に記載の超小型電子素子。
- 前記端子の前記パッドから前記チップに向かって前記バンプに沿って下方に延在する導電性帯片と、前記帯片を少なくとも部分的に覆う半田マスク層とをさらに備え、前記半田マスク層は、前記端子の前記パッドと一直線に並ぶ開口を有することを特徴とする請求項24に記載の超小型電子素子。
- 前記バンプの各々は、前記チップから離れた上端を有し、前記端子の前記パッドは、前記バンプの前記上端に配置され、前記半田マスクは、前記バンプの上端まで実質的に延在することを特徴とする請求項25に記載の超小型電子素子。
- 本体および前記本体に支持された端子を備える超小型電子素子を検査する方法であって、前記端子の各々は、導電性パッドと、前記パッド上の導電性ポストとを備え、前記ポストは前記パッドよりも小さい直径を有し、前記ポストは前記本体から離れて上方に突出し、当該方法は、前記超小型電子素子を検査備品に、前記端子の前記ポストが前記検査備品の接触パッドと当接するように、係合させることを含むことを特徴とする方法。
- 前記係合ステップは、前記超小型電子素子と検査備品とを互いに向かって付勢することを含むことを特徴とする請求項27に記載の方法。
- 前記超小型電子素子を前記検査備品から取り外し、前記端子を基板の接触パッドに、導電接合材料の塊が前記端子の前記パッドと前記基板の前記接触パッドとの間に延在するように、接合させるステップをさらに含むことを特徴とする請求項27に記載の方法。
- 前記接合ステップは、前記ポストが前記接合材料の塊内に配置されるように行われることを特徴とする請求項29に記載の方法。
- 前記本体は半導体チップおよび前記チップから離れて上方に突出する複数のバンプを含み、前記端子の前記パッドは、前記端子の前記ポストが前記バンプから突出するように、前記バンプ上に配置されることを特徴とする請求項27に記載の方法。
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US11/318,846 US7534652B2 (en) | 2005-12-27 | 2005-12-27 | Microelectronic elements with compliant terminal mountings and methods for making the same |
PCT/US2006/049202 WO2007076099A2 (en) | 2005-12-27 | 2006-12-26 | Microelectronic elements with compliant terminal mountings and methods for making the same |
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- 2006-12-26 JP JP2008548666A patent/JP5695294B2/ja active Active
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JP2009521818A (ja) | 2009-06-04 |
CN101346812B (zh) | 2012-05-09 |
WO2007076099A3 (en) | 2007-08-23 |
US20070145550A1 (en) | 2007-06-28 |
CN101346812A (zh) | 2009-01-14 |
US7534652B2 (en) | 2009-05-19 |
KR101411482B1 (ko) | 2014-06-24 |
WO2007076099A2 (en) | 2007-07-05 |
KR20080091163A (ko) | 2008-10-09 |
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