JP5687844B2 - ハイブリッド半導体基板の製造プロセス - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 170
- 239000000758 substrate Substances 0.000 title claims abstract description 142
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 60
- 239000012535 impurity Substances 0.000 claims abstract description 73
- 238000000034 method Methods 0.000 claims abstract description 55
- 239000012212 insulator Substances 0.000 claims abstract description 10
- 125000006850 spacer group Chemical group 0.000 claims description 19
- 239000000463 material Substances 0.000 claims description 11
- 150000004767 nitrides Chemical class 0.000 claims description 11
- 238000002955 isolation Methods 0.000 claims description 4
- 238000002513 implantation Methods 0.000 description 16
- 238000005530 etching Methods 0.000 description 11
- 238000005229 chemical vapour deposition Methods 0.000 description 8
- 238000005468 ion implantation Methods 0.000 description 7
- 239000002019 doping agent Substances 0.000 description 6
- 229910052814 silicon oxide Inorganic materials 0.000 description 5
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 208000012868 Overgrowth Diseases 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000002800 charge carrier Substances 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000000280 densification Methods 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 238000007667 floating Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical class [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
- H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/185—Joining of semiconductor bodies for junction formation
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823412—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
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- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
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- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
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- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
- H01L27/1207—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
Description
Claims (17)
- ハイブリッド半導体基板を製造する方法において、
(a)ベース基板(3)の上の絶縁層(5)と前記絶縁層(5)の上のSeOI層(7)とを備えるセミコンダクタ−オン−インシュレータ(SeOI)領域(13)と、バルク半導体領域(11)とを具備するハイブリッド半導体基板を提供するステップであって、前記SeOI領域(13)と前記バルク半導体領域(11)は同じベース基板(3)を共用するステップと、
(b)前記SeOI領域(13)の上にマスク層(9)を提供するステップと、
(c)前記SeOI領域(13)と前記バルク半導体領域(11)を同時にドーピングすることにより、第1の不純物レベル(17a、17b)を形成するステップであって、該ドーピングは、前記SeOI領域(13)の前記第1の不純物レベル(17a)が前記マスク層(9)内のみに含まれるように実行される、ステップと
を含むことを特徴とする方法。 - ハイブリッド半導体基板を製造する請求項1に記載の方法において、
(d)前記SeOI領域(13)と前記バルク半導体領域(11)を同時にドーピングすることにより、第2の不純物レベル(19a、19b)を形成するステップであって、該ドーピングは、前記SeOI領域(13)の前記第2の不純物レベル(19a)が、前記絶縁層(5)の下の前記ベース基板(3)内にあるように実行される、ステップをさらに含むことを特徴とする方法。 - ハイブリッド半導体基板を製造する請求項2に記載の方法において、
(e)前記SeOI領域(13)と前記バルク半導体領域(11)を同時にドーピングすることにより、第3の不純物レベル(21a、21b)を形成するステップであって、該ドーピングは、前記SeOI領域(13)の前記第3の不純物レベル(21a)が、前記第2の不純物レベル(19a)の下の前記ベース基板(3)内の、前記絶縁層(5)からさらに離れた位置にあるように実行される、ステップをさらに含むことを特徴とする方法。 - ハイブリッド半導体基板を製造する請求項1ないし3のいずれかに記載の方法であって、
(g)セミコンダクタ−オン−インシュレータ(SeOI)基板(1a)を提供するステップと、
前記SeOI基板(1a)上に前記マスク層(9)を形成するステップと、
前記マスク層(9)、前記SeOI層(7)および前記絶縁層(5)の所定の領域を除去して、前記バルク半導体領域(11)を得るステップと
をさらに含むことを特徴とする方法。 - ハイブリッド半導体基板を製造する請求項1ないし4のいずれかに記載の方法であって、
(h)ステップc)、d)およびe)のうちの少なくとも1つのステップの最中に、第2のマスク(15)によってマスクされた領域に不純物レベルが形成されることを防ぐために、前記ハイブリッド半導体基板の上に、所定のパターンを有する前記第2のマスク(15)を提供するステップを含むことを特徴とする方法。 - ハイブリッド半導体基板を製造する請求項1ないし5のいずれかに記載の方法であって、
(i)ステップc)の後に、前記SeOI領域(13)から前記マスク層(9)を除去するステップを含むことを特徴とする方法。 - ハイブリッド半導体基板を製造する請求項1ないし6のいずれかに記載の方法であって、前記マスク層(9)および/または前記絶縁層(5)は、酸化物からなることを特徴とする方法。
- ハイブリッド半導体基板を製造する請求項1ないし7のいずれかに記載の方法であって、
(j)前記バルク半導体領域(11)に隣接する前記SeOI領域(13)のエッジ領域に、スペーサ(29)を、前記スペーサ(29)が少なくとも前記ベース基板(3)の表面から前記SeOI層(7)まで延びるように提供するステップをさらに含むことを特徴とする方法。 - ハイブリッド半導体基板を製造する請求項8に記載の方法であって、前記スペーサ(29)を、とりわけステップ(j)の後に除去するステップをさらに含むことを特徴とする方法。
- ハイブリッド半導体基板を製造する請求項8または9に記載の方法であって、前記スペーサ(29)は、マスク層(9)とは異なる材料からなり、とりわけ窒化物であることを特徴とする方法。
- ハイブリッド半導体基板を製造する請求項1ないし10のいずれかに記載の方法であって、前記マスク層(9)の厚さは少なくとも20nm、とりわけ20nm以上、30nm以下であることを特徴とする方法。
- ハイブリッド半導体基板を製造する請求項1ないし11のいずれかに記載の方法であって、
前記SeOI層(7)の厚さは最大20nm、とりわけ10nm以上、20nm以下であり、かつ/または
前記絶縁層(5)の厚さは最大20nm、とりわけ10nm以上、20nm以下であることを特徴とする方法。 - ハイブリッド半導体基板を製造する請求項1ないし12のいずれかに記載の方法であって、浅いトレンチ分離(STI)(23)を提供して、前記SeOI領域(13)と前記バルク半導体領域(11)とを分離するステップをさらに含むことを特徴とする方法。
- ベース基板(3)と、前記ベース基板(3)の上の絶縁層(5)と、前記絶縁層(5)の上のSeOI層(7)と、前記SeOI層(7)の上のマスク層(9)とを備えるセミコンダクタ−オン−インシュレータ(SeOI)領域(13)と、
前記SeOI領域(13)に隣接して提供されたバルク半導体領域(11)と、
前記SeOI領域(13)および前記バルク半導体領域(11)の第1の不純物領域(17a、17b)と
を具備し、
前記SeOI領域(13)の前記第1の不純物領域(17a)は前記マスク層(9)内のみに含まれることを特徴とするハイブリッド半導体基板。 - 前記SeOI領域(13)と前記バルク半導体領域(11)は同じベース基板(3)を共用することを特徴とする請求項14に記載のハイブリッド半導体基板。
- 前記SeOI領域(13)および前記バルク半導体領域(11)の第2の不純物領域(19a、19b)をさらに具備し、前記SeOI領域(13)の前記第2の不純物領域(19a)は、前記絶縁層(5)の下の前記ベース基板(3)内にあることを特徴とする請求項15に記載のハイブリッド半導体基板。
- 前記SeOI領域(13)および前記バルク半導体領域(11)の第3の不純物領域(21a、21b)をさらに具備し、前記SeOI領域(13)の前記第3の不純物領域(21a)は、前記第2の不純物領域(19a)の下の前記ベース基板(3)内の、前記絶縁層(5)からさらに離れた位置にあることを特徴とする請求項16に記載のハイブリッド半導体基板。
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EP09290372A EP2254148B1 (en) | 2009-05-18 | 2009-05-18 | Fabrication process of a hybrid semiconductor substrate |
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FR2991502B1 (fr) * | 2012-05-29 | 2014-07-11 | Commissariat Energie Atomique | Procede de fabrication d'un circuit integre ayant des tranchees d'isolation avec des profondeurs distinctes |
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WO2014020387A1 (en) | 2012-07-31 | 2014-02-06 | Soitec | Methods of forming semiconductor structures including mems devices and integrated circuits on opposing sides of substrates, and related structures and devices |
TWI588955B (zh) | 2012-09-24 | 2017-06-21 | 索泰克公司 | 使用多重底材形成iii-v族半導體結構之方法及應用此等方法所製作之半導體元件 |
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KR101639261B1 (ko) * | 2015-05-21 | 2016-07-13 | 서울시립대학교 산학협력단 | 하이브리드 반도체 소자 및 하이브리드 반도체 모듈 |
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-
2009
- 2009-05-18 EP EP09290372A patent/EP2254148B1/en active Active
- 2009-05-18 AT AT09290372T patent/ATE535937T1/de active
-
2010
- 2010-03-11 SG SG201001706-9A patent/SG166719A1/en unknown
- 2010-03-15 KR KR1020100022903A patent/KR101687603B1/ko not_active Application Discontinuation
- 2010-03-18 US US12/726,800 patent/US8058158B2/en active Active
- 2010-03-25 TW TW099108956A patent/TWI492276B/zh active
- 2010-04-21 JP JP2010097815A patent/JP5687844B2/ja active Active
- 2010-05-12 CN CN201010178285.XA patent/CN101894741B/zh active Active
Also Published As
Publication number | Publication date |
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ATE535937T1 (de) | 2011-12-15 |
CN101894741B (zh) | 2014-10-08 |
US20100289113A1 (en) | 2010-11-18 |
KR101687603B1 (ko) | 2016-12-20 |
CN101894741A (zh) | 2010-11-24 |
US8058158B2 (en) | 2011-11-15 |
KR20100124202A (ko) | 2010-11-26 |
TWI492276B (zh) | 2015-07-11 |
TW201110201A (en) | 2011-03-16 |
EP2254148B1 (en) | 2011-11-30 |
EP2254148A1 (en) | 2010-11-24 |
JP2010267959A (ja) | 2010-11-25 |
SG166719A1 (en) | 2010-12-29 |
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