CN109037047B - 电子芯片中的半导体区域的制造 - Google Patents

电子芯片中的半导体区域的制造 Download PDF

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CN109037047B
CN109037047B CN201810570553.9A CN201810570553A CN109037047B CN 109037047 B CN109037047 B CN 109037047B CN 201810570553 A CN201810570553 A CN 201810570553A CN 109037047 B CN109037047 B CN 109037047B
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silicon nitride
nitride layer
semiconductor substrate
doped
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CN109037047A (zh
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F·朱利恩
F·谢拉
N·布兰克
E·布罗特
P·劳克斯
G·泰雷
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STMicroelectronics Rousset SAS
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Abstract

本公开涉及电子芯片中的半导体区域的制造。例如，一种方法可用于制造由隔离沟槽隔开的第一和第二半导体区域。半导体衬底被氮化硅覆盖。通过离子注入掺杂位于第一区域上方的氮化硅。沟槽被蚀刻穿过氮化硅，并且以各向同性方式部分地蚀刻掺杂氮化硅。用绝缘体填充沟槽到达位于第一区域的层级上方的层级。去除氮化硅，使得仅第一区域的边缘被绝缘体环覆盖。

Description

电子芯片中的半导体区域的制造
相关申请的交叉参考
本申请要求2017年6月12日提交的法国申请第1755226号的优先权，其内容结合于此作为参考。
技术领域
本专利申请涉及一种用于在电子芯片中制造半导体区域的方法。
背景技术
在包括场效应晶体管的电子芯片中会产生各种问题。
具体地，这种晶体管中的一个问题在于：一般地，晶体管越小，泄露电流的相对值越大。这就导致了高能耗。
另一问题在于：当多个晶体管被设计为相同时，这些晶体管实际上通常显示出不同的电特性，具体为不同的阈值电压。当操作温度降低时，这些电特性之间的差异通常趋于恶化。这在实际获取想要的电特性的过程中导致各种困难。这些困难尤其在芯片被提供用于模拟操作(例如，在测量设备中)和/或冷操作(例如，在负环境温度下)的情况下产生。这通常导致特定芯片在制造后检查期间被拒绝。
此外，电子芯片可以包括被控制栅极环绕的浮置栅极晶体管类型的存储点。除了关于晶体管的上述问题之外，由于相对较高的电压被要求施加用于编程存储点的事实，这种存储点显示出劣化晶体管的栅极绝缘体的问题。
如果期望针对不同类型(N沟道和P沟道)的晶体管和/或存储点同时实施的话，则用于解决上述各种问题的各种已知方法要求多种制造步骤。
发明内容
本专利申请涉及一种用于在电子芯片中制造半导体区域(例如，用于形成N沟道和P沟道晶体管和/或存储点的半导体区域)的方法。实施例可以减轻上述缺陷中的所有或一些。
一个实施例提供了一种用于制造通过隔离沟槽隔开的第一和第二半导体区域的方法。半导体衬底用氮化硅覆盖。位于第一区域上方的氮化硅通过离子注入来掺杂。以各向同性的方式，沟槽蚀刻穿过氮化硅，并且掺杂的氮化硅被部分蚀刻。沟槽用绝缘体填充到位于第一区域的层级上方的层级。去除氮化硅，使得第一区域的边缘仅用绝缘体环覆盖。
根据一个实施例，该方法进一步包括清洁在去除氮化硅后得到的结构的步骤。这种清洁会使得在第二区域周围的绝缘体的表面上形成凹陷(pit)。
根据一个实施例，氮化硅具有80和200nm之间的厚度，并且利用大于60keV的能量来执行离子注入。
根据一个实施例，在包括氩和磷的组中选择注入的离子。
根据一个实施例，部分蚀刻去除2和15nm之间的氮化硅的厚度，并且沟槽被填充到第一区域的层级上方1和10nm之间的层级。
根据一个实施例，通过包括磷酸的溶液来执行部分蚀刻。
根据一个实施例，衬底是SOI结构的上部半导体层。
根据一个实施例，衬底是块状(bulk)衬底。
该方法可以同时地制造N沟道晶体管和P沟道晶体管。在形成氮化硅之前，在第一区域中执行P型掺杂步骤，并且在第二区域中执行N型掺杂。在去除氮化硅之后，P沟道晶体管形成在第二区域中和上，并且N沟道晶体管形成在第一区域中和上。
一个实施例提供了一种包括通过填充有绝缘体的沟槽隔开的第一和第二半导体区域的器件。第一区域的边缘仅用绝缘体环覆盖。
根据一个实施例，绝缘体的表面在第二区域周围形成凹陷。
一个实施例提供了一种电子芯片，其包括诸如上面所述的器件。N沟道晶体管定位在第一区域中和上，并且P沟道晶体管定位在第二区域中和上。
附图说明
将在以下参照附图给出的具体实施例的非限制性描述中详细地描述这些特征和优点及其他，其中：
图1A至图1E是示出用于制造P沟道晶体管的方法的步骤的部分和示意性截面图；
图1F是图1E的结构从上往下看的平面图；
图2A至图2H是示出用于制造N沟道晶体管和P沟道晶体管的方法的实施例的步骤的部分和示意性截面图；以及
图2I是图2H的结构从上往下看的平面图。
具体实施方式
各个附图没有按比例绘制，并且此外，在各个附图中，相同的元件通过相同的参考标号表示。为了清楚，仅示出并详细描述对于所述实施例的理解有用的那些元件。具体地，没有示出晶体管的各种元件(诸如间隔件)。
在以下描述中，当参考诸如术语“左”、“右”、“上方”、“上部”、“下部”等的位置限定时，参考所考虑附图中表示的元件的定向，实际上理解所描述的器件可以不同地定向。
图1A至图1E是示出用于制造P沟道晶体管的方法的步骤的部分和示意性截面图。
在图1A的步骤中，半导体衬底10例如包括N型掺杂阱12N。在阱12N的上部中，已经形成N型掺杂区域16N，并且根据晶体管的期望电特性来选择其掺杂等级。通过变形，阱12N和区域16N将在该方法的稍后步骤中形成。衬底用厚度通常在2和20nm之间的精细的氧化硅层14覆盖。此后，在结构上沉积氮化硅层20，然后沟槽22蚀刻穿过氮化硅(在图中仅看到一半沟槽)。沟槽穿入衬底中，并且界定区域16N的一部分。
在图1B的步骤中，用绝缘体(例如，氧化硅)填充沟槽到达氮化硅20的上部层级。
在图1C的步骤中，相对于氮化硅20，例如相对于位于区域16N的层级上方的层级，沟槽22的绝缘体被选择性地蚀刻。
在步骤1D的步骤中，通过相对于沟槽22的绝缘体选择性地蚀刻来去除氮化硅。然后，层14保护区域16N。此后，该结构被清洁，以消除仍然存在于区域16N上的层14的氧化物。例如在基于氢氟酸的溶液中执行这种清洁。这种清洁使得在区域16N周围的沟槽的绝缘体表面上形成凹陷28。
在图1E的步骤中，在区域16N中和上形成P沟道MOS晶体管。具体地，形成栅极绝缘层30和栅极32。
图1F是图1E的结构从上往下看的示图。没有表示绝缘层30。从上往下看，栅极32遍布区域16N的宽度延伸。在区域16N中的栅极的每一侧上形成漏极和源极区域34。
调整上述方法的参数(具体地，图2C的步骤中沟槽22的绝缘体的蚀刻以及图2D的步骤中的清洁)，以优化晶体管的电特性，例如使其泄露电流最小。这种调整例如通过试验来执行。确实，由于各种边缘效应，电特性(诸如阈值电压和泄露电流)在晶体管的边缘和中心处是不同的。调整方法的参数使得可以得到减少这些边缘效应的凹陷形状。
上面已经描述了使得可以得到最佳电特性的P沟道晶体管的方法。然而，该方法不适合于得到最佳电特性的N沟道晶体管。确实，当区域16不再是N型区域16N而是P型区域16P时，在为该方法提供的各种退火步骤的过程中，P型掺杂原子(尤其当处理硼时)区域迁移到沟槽22的绝缘体(例如，氧化硅)中。这样做的结果是，与沟槽22接触的区域16P的外围部分的掺杂等级低于区域16P的中心处的掺杂等级，并且这是不规则的方式。因此，当实施图1A至图1E的方法以得到被设计为相同的各种N沟道晶体管时，减小掺杂的外围部分是导致晶体管的电特性之间的差异的原因。
图2A至图2H是示出用于在图中左侧制造N沟道晶体管以及在右侧制造P沟道晶体管的方法的实施例的步骤的部分和示意性截面图。该方法使得可以优化P沟道晶体管和N沟道晶体管的电特性，并且减少被设计为相同的晶体管之间的差异。
在图2A的步骤中，提供衬底10。衬底10这里以块状半导体衬底(例如，硅)为例。衬底部分的左部代表P型掺杂阱12P。衬底部分的右部代表N型掺杂阱12N。通过变形，衬底可以是覆盖支持件上的绝缘层的半导体层，也就是说，SOI(“绝缘体上硅”)结构的上部半导体层。
优选地，分别在左侧和右侧在衬底中实施P型掺杂层16P’和N型掺杂层16N’。例如，层16P’和层16N’的掺杂等级大于1017原子/cm3。在衬底是覆盖SOI衬底的绝缘层的单晶硅的薄层的变形中，层16P’和层16N’可以延伸遍及薄单晶硅层的厚度。
通过变形，阱12P、阱12N、区域16P和/或区域16N可以在该方法的稍后步骤中被掺杂，来代替从图2A的步骤开始掺杂。
优选地，衬底覆盖有厚度例如在2和20nm之间的氧化硅层14。
此后，氮化硅层20被沉积在衬底上。氮化硅层20优选具有80和200nm之间的厚度。
在图2B的步骤中，P沟道晶体管的位置被覆盖有掩模层，例如光敏树脂层40。在N沟道晶体管的位置处去除该层。
然后，在N沟道晶体管的位置处进行氮化硅中的注入(箭头42)。例如，注入的原子是氩和/或磷原子。还可以使用其他类型的原子。选择注入能量以能够到达所有的氮化物层20，并且更具体地，到达其下部。在层具有80与200nm之间的厚度的情况下，注入能量例如在10与100keV之间，优选在60和90keV之间。注入到氮化硅中的原子的数量足以使得注入的氮化物可相对于非注入氮化物选择性地蚀刻。氮化物的攻击率根据所注入原子的类型以及还根据注入引发的氮化物的晶体栅格的修改而改变。
在图2C的步骤中，去除掩模层40。此后，蚀刻沟槽22，完全穿过氮化硅20以及层16P’和16N’。沟槽22在层16P’中界定半导体区域16P以及在层16N’中界定半导体区域16N。沟槽22环绕区域16P和16N。得到掺杂氮化硅20’的整体地覆盖区域16P的部分以及非掺杂氮化硅20的整体地覆盖区域16N的部分。相邻沟槽之间的距离对应于未来晶体管的宽度W(对应于晶体管的漏极-源极方向的长度)，并且例如在10nm和几十μm之间。
在图2D的步骤中，进行氮化硅的各向同性蚀刻。通过示例，通过磷酸溶液来执行蚀刻。掺杂氮化硅20’比非掺杂氮化硅20更快地被蚀刻，通常快10至100倍。选择蚀刻的参数(例如，溶液的组成和浓度、蚀刻的持续时间和温度)，以根据晶体管的尺寸去除掺杂氮化硅20’的例如2和几十nm之间的厚度，优选地，2与15nm之间的厚度。
在图2E的步骤中，在沟槽22中填充绝缘体23(例如，氧化硅)到达氮化硅20、20’的上部层级。
在图2F的步骤中，例如通过基于氢氟酸的溶液，隔离沟槽的绝缘体被选择性地蚀刻到位于区域16P的层级上方的层级。由此，绝缘体环50保留在区域16P的外围上方，环绕氮化物焊盘20’。选择蚀刻的参数，使得保留在区域16P的边缘上的绝缘体环50的厚度例如在1和几十nm之间，优选在1和10nm之间。
在图2G的步骤中，例如通过基于磷酸的溶液，去除氮化硅。此后，例如在基于氢氟酸的溶液中清洁该结构。在N区域18周围得到凹陷28，并且在区域16P的边缘上保留绝缘体环50。
在图2H的步骤中，制造分别位于区域16P和16N中和上的N沟道和P沟道晶体管。具体地，形成栅极绝层30和栅极32。通过示例，通过热氧化和/或通过沉积形成栅极绝缘体。栅极绝缘体可以包括具有高介电常数的材料，例如氧化铪。
图2I是图2H的结构从上往下看的示意图，其中没有表示栅极绝缘体。栅极32横跨区域16P和16N在漏极和源极区域34之间延伸。在晶体管被并排形成的情况下，栅极对于两个晶体管来说可以是公共的。
如前所述，当区域16不再是N型区域16N而是P型区域16P时，在为该方法提供的各种退火的过程中，P型的掺杂原子(尤其涉及硼时)趋于在沟槽22的绝缘体(例如，氧化硅)中迁移。这样的结果是，与沟槽22接触的区域16P的外围部分的掺杂等级低于区域16P的中心处的掺杂等级，并且是以不规则的方式。在图2H中，通过参考标号54来表示这些更轻掺杂的外围区域。它们被绝缘体环50覆盖。因此，栅极下方的绝缘体的厚度在沟槽区域的边缘处更大，并且栅极30仅在具有区域16P的均匀掺杂的中心部分上方有效。由此，以简单的方式得到优化的N沟道晶体管，具体为减少了步骤的数量。
可以调整该方法的参数(具体地，图2D的步骤的掺杂氮化硅20’的蚀刻、图2F的步骤的沟槽22的绝缘体的蚀刻以及图2G的步骤的清洁)，以在一个相同的时间得到P沟道晶体管和N沟道晶体管的优化电特性，具体得到被设计为相同的晶体管之间的减少的差异。
根据一个优点，以具体为减少步骤的数量的方式并且以简化的方式得到优化特性的N沟道和P沟道晶体管。此外，保留与部分42被自动对准的事实相关的图1A至图1F的方法的可靠性的优势。
根据另一优点，即使对于较小的晶体管，也可以同时得到显示出尤其低的泄露电流的N沟道和P沟道晶体管。这具体得到低能量消耗，尤其对于包括这种晶体管的芯片。
根据另一优点，除了P沟道晶体管之外，当使用该方法来制造被设计为相同的多个N沟道晶体管时，得到电特性近似相同的N沟道晶体管(包括在冷操作的条件下)。因此，关于在测量设备中使用的晶体管的制造，该方法显示出特别的兴趣。此外，这使得得到尤其高的制造效率。
已经描述了具体实施例。本领域技术人员应明了各种变形和修改。具体地，该方法可以适用于同时制造例如栅极绝缘体厚度不同和/或栅极绝缘体材料不同的晶体管。为此，在图2H的步骤中形成的栅极绝缘体层30可以具有在各种晶体管的位置处不同的厚度和/或在各种晶体管的位置处由不同的材料制成。由此，可以得到阈值电压彼此不同和/或使用电压彼此不同的晶体管。此外，晶体管可以为相同的沟道类型，尽管已经描述了P沟道和N沟道晶体管的制造。
此外，尽管上述实施例涉及晶体管的制造，但所述方法可以适用于其他部件的制造，例如存储点的制造。因此，在图2H的步骤中，晶体管的栅极用没有表示的绝缘层覆盖，该绝缘层例如包括位于两个氧化硅层之间的氮化硅层，并且栅极(未示出)形成在该绝缘层上。由此，该栅极组成用于存储点的控制栅极，栅极32组成存储点的浮置栅极。通过变形，还可以同时形成晶体管和另一部件(诸如存储点)。两个部件可以为相同的沟道类型或不同的沟道类型。

Claims (17)

1.一种用于制造半导体器件的方法，所述方法包括：
在半导体衬底之上形成氮化硅层；
掺杂位于所述半导体衬底的第一区域上方的所述氮化硅层，从而形成所述氮化硅层的掺杂部分，通过离子注入执行所述掺杂，其中所述氮化硅层的位于第二区域之上的部分保持不掺杂；
穿过所述氮化硅层蚀刻沟槽，所述沟槽被布置在所述第一区域和所述第二区域上方，所述沟槽被蚀刻进入所述半导体衬底中，使得所述第一区域与所述第二区域隔离；
部分地各向同性蚀刻掺杂的所述氮化硅层；
用绝缘体将所述沟槽填充到比所述半导体衬底的所述第一区域和所述第二区域的上表面的层级高的层级；以及
从所述半导体衬底的所述第一区域之上去除所述氮化硅层的剩余部分，在去除所述氮化硅层之后，所述半导体衬底的所述第一区域的边缘被绝缘体环覆盖。
2.根据权利要求1所述的方法，其中所述氮化硅层具有80与200nm之间的厚度，并且其中利用大于60keV的能量执行所述离子注入。
3.根据权利要求1所述的方法，其中掺杂所述氮化硅层包括：利用氩或磷来掺杂所述氮化硅层。
4.根据权利要求1所述的方法，其中部分地各向同性蚀刻掺杂的所述氮化硅层包括：去除氮化硅的2与15nm之间的厚度，并且所述沟槽被填充到所述半导体衬底的所述第一区域和所述第二区域的上表面的层级上方的、1与10nm之间的层级。
5.根据权利要求1所述的方法，其中部分地各向同性蚀刻掺杂的所述氮化硅层包括：使用包括磷酸的溶液进行蚀刻。
6.根据权利要求1所述的方法，其中所述半导体衬底是SOI结构的上部半导体层。
7.根据权利要求1所述的方法，其中所述半导体衬底是块状半导体衬底。
8.一种用于制造半导体器件的方法，所述方法包括：
在包括p掺杂第一区域和n掺杂第二区域的半导体衬底之上形成氮化硅层；
通过离子注入在所述第一区域之上掺杂所述氮化硅层，所述第二区域之上的所述氮化硅层不被掺杂；
蚀刻穿过所述氮化硅层、位于所述第一区域和所述第二区域上方并且进入所述半导体衬底的沟槽，使得所述第一区域与所述第二区域隔离；
部分地各向同性蚀刻所述第一区域之上的掺杂的所述氮化硅层；
用绝缘体将所述沟槽填充到比所述半导体衬底的上表面的层级高的层级；以及
从所述半导体衬底的所述第一区域之上去除掺杂的所述氮化硅层的剩余部分，在去除所述第一区域之上的掺杂的所述氮化硅层的剩余部分之后，所述半导体衬底的所述第一区域的边缘被绝缘体环覆盖。
9.根据权利要求8所述的方法，其中在去除所述氮化硅层的剩余部分之后，在所述第二区域周围的绝缘体的表面上形成凹陷。
10.根据权利要求8所述的方法，还包括：在所述第一区域处形成n沟道晶体管，以及在所述第二区域处形成p沟道晶体管。
11.根据权利要求8所述的方法，其中
所述氮化硅层在被形成时具有80与200nm之间的厚度；
利用大于60keV的能量执行所述离子注入；
其中部分地各向同性蚀刻掺杂的所述氮化硅层包括：去除氮化硅的2与15nm之间的厚度；以及
在所述半导体衬底的上表面的层级上方，所述沟槽被填充到1与10nm之间的层级。
12.根据权利要求8所述的方法，其中掺杂所述氮化硅层包括：利用氩或磷掺杂所述氮化硅层。
13.根据权利要求8所述的方法，其中部分地各向同性蚀刻掺杂的所述氮化硅层包括：使用包括磷酸的溶液进行蚀刻。
14.一种半导体器件，包括：
半导体衬底，具有被沟槽环绕的第一区域和第二区域；以及
绝缘材料，填充所述沟槽；
其中所述第一区域的上表面的边缘被填充所述沟槽的所述绝缘材料的一部分覆盖；并且
其中填充所述沟槽的所述绝缘材料在与所述第二区域的边缘相邻的位置处被填充到低于所述第二区域的边缘的层级；
介电层，覆盖所述第一区域、所述第二区域和所述绝缘材料，并且覆盖所述绝缘材料的所述一部分，所述一部分覆盖所述第一区域的所述上表面的边缘，其中所述介电层包括覆盖所述第一区域的第一栅极介电区域和覆盖所述第二区域的第二栅极介电区域；
第一栅极区域，覆盖所述第一区域并且通过所述第一栅极介电区域与所述第一区域绝缘，所述第一栅极区域通过所述绝缘材料与所述第一区域的边缘隔开；以及
第二栅极区域，覆盖所述第二区域并且通过所述第二栅极介电区域与所述第二区域绝缘，所述第二栅极区域包括在所述第二区域的上表面的层级下方延伸的部分。
15.根据权利要求14所述的器件，其中所述第一区域是p掺杂区域，并且所述第二区域是n掺杂区域。
16.根据权利要求14所述的器件，其中所述第一区域是p掺杂区域，并且所述第一栅极区域是n沟道晶体管的栅极；以及
其中所述第二区域是n掺杂区域，并且所述第二栅极区域是p沟道晶体管的栅极。
17.根据权利要求14所述的器件，其中所述半导体衬底是SOI结构的上部半导体层。
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