JP5638760B2 - 半導体装置 - Google Patents
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Description
(実施の形態1)
図1を参照して、半導体装置(たとえば半導体チップ)50は、その表面に、スタンダードセル領域51と、そのスタンダードセル領域51の周囲に配置されたI/O(Input/Output)セル領域52と、外部との入出力に用いられるパッド(図示せず)とを主に有する。
図9を参照して、本実施の形態においては、実施の形態1における電源配線VDおよび接地配線VSのそれぞれ代わりに、電源配線VDwおよび接地配線VSwを有する。電源配線VDwおよび接地配線VSの各々は、幅Wwを有する。幅Wwは、pMIS配線M1pおよびnMIS配線M1nの各々の幅Wsよりも大きい。
図10を参照して、本実施の形態の半導体装置は、スタンダードセルCiv、Cnd、Cnr、Cflを有する。スタンダードセルCiv、Cnd、Cnr、Cflは、複数の段に分かれて配列されており、各段において図中の方向Xに沿って配列されている。
図16を参照して、本実施の形態の半導体装置SDは半導体基板SBを有し、半導体基板SB上に、I/O領域101と、CPU・ロジック領域102と、メモリ領域103と、PLL(Phase-Locked Loop)領域104と、アナログ領域105とを有する。
図23および図24を参照して、本比較例においては、Butting Diffusion構造が設けられていない。このため、n型導電領域Lnおよびp型拡散領域Dpの間の電気的接続と、p型導電領域Lpおよびn型拡散領域Dnとの間の電気的接続とは、メタル配線MTおよびコンタクトCTにより行なわれている。すなわち本実施の形態に比してコンタクトCTがより多く設けられている。この結果ゲート電極GTzの配置に制約が生じるので、複数のゲート電極GTzの配置を第1ピッチP1に統一することができない。すなわち第1ピッチP1よりも大きい第2ピッチP2や、第2ピッチP2よりも大きい第3ピッチP3が第1ピッチP1と混在している。このため本比較例においては高集積化が困難となっている。
図30および図31を参照して、本実施の形態の半導体装置は、ゲート電極GTが形成された層LD2(図30)を有する。この層LD2の部分Xa〜Xfの各々におけるゲート電極GTの配置について、比較例と対比しつつ、以下に詳しく説明する。
図44および図45を参照して、本実施の形態の半導体装置は、ゲート電極GTが形成された層LD3を有する。この層LD3は、セルYa〜Yeの各々に対応する部分を有する。セルYa〜Yeのそれぞれは、半導体装置のうち、インバータ、NAND、NOR、トライステートバッファ、およびフリップフロップとして機能する部分を区画している。セルYa〜Yeの各々は、第1の方向(図44および図45における横方向)に沿って第1ピッチP1の整数倍の幅を有する。たとえばセルYaおよびYbのそれぞれは、第1ピッチP1の2倍および3倍の幅UaおよびUbを有する。
図47〜図49を参照して、本実施の形態の半導体装置は、論理回路として使用されるセルと、論理回路として使用されないダミーセル(フィラーセル)FGとを有する。論理回路として使用されるセルと、論理回路として使用されないダミーセルFGとの各々のゲート電極GTは、第1の方向(図47〜図49における横方向)に第1ピッチで配置されている。
図51および図52を参照して、本実施の形態の半導体装置は、論理回路として使用されるセルと、論理回路として使用されないダミーセル(フィラーセル)FMとを有する。論理回路として使用されるセルと、論理回路として使用されないダミーセルFGとのそれぞれは、メタル配線MTとして、メタル配線MTdと、メタル配線MTfとを有する。メタル配線MTは、第1の方向(図51の横方向)に延び、かつ第2の方向(図51の縦方向)に第2ピッチで配置されている。よってメタル配線MTfの各々は、第1の方向(図51の横方向)に延び、かつダミーセルFMにおいて第2の方向に第2ピッチで配置されている。
図54を参照して、本実施の形態の半導体装置は、容量セルFCaを有する。容量セルFCaは、半導体装置において、電源電位Vccおよび接地電位Vss間に配置されたデカップリング・コンデンサとして機能する部分を区画している。ゲート電極GTは、p型拡散領域Dpおよびn型拡散領域Dnと対向することにより静電容量をなしている。すなわちゲート電極GTは、デカップリング・コンデンサの電極の一部をなしている。
Claims (1)
- 第1の方向に沿って配列された複数のスタンダードセルを有する半導体装置であって、
前記複数のスタンダードセルの各々は、第1の方向に沿って延びかつ互いに正対する第1および第2の外縁を有し、
前記第1の方向に沿って前記複数のスタンダードセルの各々を通りn型ウエルおよびp型ウエルの境となる境界と前記第1の外縁との間に形成されたpMIS領域と、前記境界と前記第2の外縁との間に形成されたnMIS領域とを有する半導体基板と、
前記第1の方向に直交する第2の方向に沿って延びる複数のゲート配線を有し、かつ前記半導体基板上に設けられた第1の層と、
前記第1の層上に設けられた第2の層とを備え、
前記pMIS領域は、n型ウエルと、前記n型ウエル上に形成されたp型拡散領域とを含み、
前記p型拡散領域は、前記pMIS領域におけるソース/ドレイン領域と、前記pMIS領域におけるソース/ドレイン領域の一方の領域に連なり前記第1の外縁と重なって延びる第1接続領域とを有し、
前記nMIS領域は、p型ウエルと、前記p型ウエル上に形成されたn型拡散領域とを含み、
前記n型拡散領域は、前記nMIS領域におけるソース/ドレイン領域と、前記nMIS領域におけるソース/ドレイン領域の一方の領域に連なり前記第2の外縁と重なって延びる第2接続領域とを有し、
前記第2の層は、
前記第1の外縁上に重なるように配置されるとともに前記第1の外縁に沿って延び、かつ前記pMIS領域に電気的に接続された第1の電源配線と、
前記第2の外縁上に重なるように配置されるととに前記第2の外縁に沿って延び、かつ前記nMIS領域に電気的に接続された第2の電源配線と、
前記第1および第2の電源配線の間の前記pMIS領域上において、前記第1の方向に沿って延びかつ前記第2の方向に沿って一のピッチで配置された複数の第1の仮想ラインのそれぞれの上に配置された複数のpMIS配線と、
前記第1および第2の電源配線の間の前記nMIS領域上において、前記第1の方向に沿って延びかつ前記第2の方向に沿って前記一のピッチで配置された複数の第2の仮想ラインのそれぞれの上に配置された複数のnMIS配線とを含み、
前記複数の第1の仮想ラインのうち前記境界に最も近いものと、前記複数の第2の仮想ラインのうち前記境界に最も近いものとの間隔は、前記一のピッチよりも大きく、
前記複数の第1の仮想ラインのうち前記第1の外縁に最も近いものと、前記第1の外縁との間隔は、前記一のピッチより大きく、
前記複数の第1の仮想ラインのうち前記第2の外縁に最も近いものと、前記第2の外縁との間隔は、前記一のピッチより大きく、
前記第1の電源配線は、コンタクトを介して前記第1接続領域と接続され、
前記第2の電源配線は、コンタクトを介して前記第2接続領域と接続されている、半導体装置。
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
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JP2009026135A JP5638760B2 (ja) | 2008-08-19 | 2009-02-06 | 半導体装置 |
TW098126391A TWI446198B (zh) | 2008-08-19 | 2009-08-05 | 半導體裝置 |
US12/536,319 US8237203B2 (en) | 2008-08-19 | 2009-08-05 | Semiconductor device |
CN2009101654632A CN101656253B (zh) | 2008-08-19 | 2009-08-18 | 半导体器件 |
US13/538,602 US8710552B2 (en) | 2008-08-19 | 2012-06-29 | Semiconductor device |
US14/185,801 US9035392B2 (en) | 2008-08-19 | 2014-02-20 | Semiconductor device |
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JP2008210332 | 2008-08-19 | ||
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JP2009026135A JP5638760B2 (ja) | 2008-08-19 | 2009-02-06 | 半導体装置 |
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JP2014215529A Division JP5944464B2 (ja) | 2008-08-19 | 2014-10-22 | 半導体装置 |
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JP2010074125A5 JP2010074125A5 (ja) | 2012-03-08 |
JP5638760B2 true JP5638760B2 (ja) | 2014-12-10 |
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---|---|---|---|---|
JP5292005B2 (ja) * | 2008-07-14 | 2013-09-18 | ルネサスエレクトロニクス株式会社 | 半導体集積回路 |
JP5944464B2 (ja) * | 2008-08-19 | 2016-07-05 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP5537078B2 (ja) * | 2009-07-23 | 2014-07-02 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP5331195B2 (ja) * | 2009-10-19 | 2013-10-30 | パナソニック株式会社 | 半導体装置 |
JP5364015B2 (ja) | 2010-03-05 | 2013-12-11 | パナソニック株式会社 | 半導体装置 |
JP5581795B2 (ja) * | 2010-05-07 | 2014-09-03 | ルネサスエレクトロニクス株式会社 | スタンダードセル、スタンダードセルを備えた半導体装置、およびスタンダードセルの配置配線方法 |
JP2011242541A (ja) * | 2010-05-17 | 2011-12-01 | Panasonic Corp | 半導体集積回路装置、および標準セルの端子構造 |
JP2012255704A (ja) * | 2011-06-08 | 2012-12-27 | Elpida Memory Inc | 半導体装置 |
US8533641B2 (en) * | 2011-10-07 | 2013-09-10 | Baysand Inc. | Gate array architecture with multiple programmable regions |
CN104303263B (zh) * | 2012-01-13 | 2016-12-14 | 特拉创新公司 | 具有线形翅片场效应结构的电路 |
JP6010308B2 (ja) * | 2012-02-27 | 2016-10-19 | ローム株式会社 | 半導体集積回路および電子機器 |
KR101913316B1 (ko) * | 2012-06-04 | 2018-10-31 | 삼성전자주식회사 | 디커플링 커패시터 및 더미 트랜지스터를 갖는 반도체 소자 |
CN104517963B (zh) * | 2013-09-27 | 2018-09-18 | 恩智浦美国有限公司 | 状态保持电源选通单元 |
KR102122458B1 (ko) | 2013-11-19 | 2020-06-12 | 삼성전자주식회사 | 반도체 소자의 패턴을 디자인하는 방법 |
JP6449082B2 (ja) | 2014-08-18 | 2019-01-09 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
CN107112280B (zh) * | 2014-10-24 | 2020-08-04 | 株式会社索思未来 | 半导体集成电路装置 |
US9646960B2 (en) | 2015-02-26 | 2017-05-09 | Samsung Electronics Co., Ltd. | System-on-chip devices and methods of designing a layout therefor |
US9710404B2 (en) | 2015-03-23 | 2017-07-18 | Intel Corporation | Dynamic configuration and peripheral access in a processor |
US9825024B2 (en) | 2015-09-30 | 2017-11-21 | Samsung Electronics Co., Ltd. | Semiconductor device |
US9935100B2 (en) * | 2015-11-09 | 2018-04-03 | Qualcomm Incorporated | Power rail inbound middle of line (MOL) routing |
US9871046B2 (en) | 2016-02-24 | 2018-01-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | SRAM circuits with aligned gate electrodes |
CN107578986B (zh) * | 2016-07-04 | 2019-11-01 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构及其形成方法和光刻偏移的测量方法 |
JP6974743B2 (ja) | 2016-08-01 | 2021-12-01 | 株式会社ソシオネクスト | 半導体集積回路装置 |
US11251124B2 (en) | 2016-11-29 | 2022-02-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Power grid structures and method of forming the same |
US10740531B2 (en) | 2016-11-29 | 2020-08-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit, system for and method of forming an integrated circuit |
US10671547B2 (en) | 2016-12-19 | 2020-06-02 | Intel Corporation | Lightweight trusted tasks |
JP6776192B2 (ja) * | 2017-06-28 | 2020-10-28 | ルネサスエレクトロニクス株式会社 | 半導体装置及びその製造方法 |
US10692808B2 (en) | 2017-09-18 | 2020-06-23 | Qualcomm Incorporated | High performance cell design in a technology with high density metal routing |
KR102362016B1 (ko) | 2017-09-19 | 2022-02-10 | 삼성전자주식회사 | 마스터 슬레이브 플립 플롭 |
US10559558B2 (en) * | 2017-09-29 | 2020-02-11 | Taiwan Semiconductor Manufacturing Co., Ltd. | Pin modification for standard cells |
DE102018122541A1 (de) | 2017-09-29 | 2019-04-04 | Taiwan Semiconductor Manufacturing Co., Ltd. | Stiftmodifizierung für standardzellen |
JP6965721B2 (ja) * | 2017-12-18 | 2021-11-10 | 富士通株式会社 | 回路素子及び回路素子の使用方法 |
WO2019138546A1 (ja) * | 2018-01-12 | 2019-07-18 | 株式会社ソシオネクスト | 半導体集積回路装置 |
CN110349947A (zh) | 2018-04-02 | 2019-10-18 | 台湾积体电路制造股份有限公司 | 半导体装置、其设计方法及包括其的系统 |
JP7365159B2 (ja) * | 2019-08-06 | 2023-10-19 | ローム株式会社 | 半導体集積回路 |
US10796061B1 (en) | 2019-08-29 | 2020-10-06 | Advanced Micro Devices, Inc. | Standard cell and power grid architectures with EUV lithography |
KR20210029966A (ko) | 2019-09-09 | 2021-03-17 | 삼성전자주식회사 | 집적된 표준 셀 구조를 포함하는 집적 회로 |
CN111244064A (zh) * | 2020-01-19 | 2020-06-05 | 比特大陆科技有限公司 | 半导体芯片、半导体装置和数据处理设备 |
US11342326B2 (en) * | 2020-04-28 | 2022-05-24 | Taiwan Semiconductor Manufacturing Co., Ltd. | Self-aligned etch in semiconductor devices |
US11606084B2 (en) * | 2020-05-26 | 2023-03-14 | Taiwan Semiconductor Manufacturing Company Ltd. | Oscillation circuit, semiconductor device for oscillation circuit and method for manufacturing the same |
KR20220124767A (ko) | 2021-02-05 | 2022-09-14 | 창신 메모리 테크놀로지즈 아이엔씨 | 표준 셀 레이아웃 템플릿 및 반도체 구조물 |
US11798809B2 (en) * | 2021-06-17 | 2023-10-24 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and method of manufacturing |
KR20230037103A (ko) * | 2021-09-08 | 2023-03-16 | 삼성전자주식회사 | 반도체 소자 및 그의 제조 방법 |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02280353A (ja) * | 1989-04-20 | 1990-11-16 | Nec Corp | 半導体集積回路 |
JPH0685062A (ja) * | 1992-09-04 | 1994-03-25 | Fujitsu Ltd | セルベースレイアウト設計方法 |
JP3281234B2 (ja) * | 1995-11-08 | 2002-05-13 | 富士通株式会社 | 半導体集積回路装置及びその製造方法 |
JP2991147B2 (ja) * | 1997-01-30 | 1999-12-20 | 日本電気株式会社 | スタンダードセルのレイアウト方式 |
JP3758876B2 (ja) | 1999-02-02 | 2006-03-22 | Necマイクロシステム株式会社 | 半導体装置のレイアウト方法 |
JP2000277620A (ja) | 1999-03-29 | 2000-10-06 | Nec Ic Microcomput Syst Ltd | 標準セル及びそれを用いた電源配線レイアウト方法 |
JP2003203993A (ja) * | 2002-01-10 | 2003-07-18 | Mitsubishi Electric Corp | 半導体記憶装置及びその製造方法 |
US7053424B2 (en) * | 2002-10-31 | 2006-05-30 | Yamaha Corporation | Semiconductor integrated circuit device and its manufacture using automatic layout |
KR100532464B1 (ko) | 2003-08-28 | 2005-12-01 | 삼성전자주식회사 | 액티브를 이용한 반도체 셀의 전원선 레이아웃 |
JP2005236107A (ja) * | 2004-02-20 | 2005-09-02 | Toshiba Corp | 上層メタル電源スタンダードセル、面積圧縮装置および回路最適化装置 |
JP4827422B2 (ja) * | 2005-03-10 | 2011-11-30 | ルネサスエレクトロニクス株式会社 | 半導体集積回路装置の設計方法と装置並びにプログラム |
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TW201017453A (en) | 2010-05-01 |
US20140239406A1 (en) | 2014-08-28 |
US20120261723A1 (en) | 2012-10-18 |
US9035392B2 (en) | 2015-05-19 |
CN101656253A (zh) | 2010-02-24 |
US20100044755A1 (en) | 2010-02-25 |
US8710552B2 (en) | 2014-04-29 |
TWI446198B (zh) | 2014-07-21 |
JP2010074125A (ja) | 2010-04-02 |
US8237203B2 (en) | 2012-08-07 |
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