JP5636203B2 - 半導体基板、半導体装置及び半導体基板の製造方法 - Google Patents

半導体基板、半導体装置及び半導体基板の製造方法 Download PDF

Info

Publication number
JP5636203B2
JP5636203B2 JP2010071059A JP2010071059A JP5636203B2 JP 5636203 B2 JP5636203 B2 JP 5636203B2 JP 2010071059 A JP2010071059 A JP 2010071059A JP 2010071059 A JP2010071059 A JP 2010071059A JP 5636203 B2 JP5636203 B2 JP 5636203B2
Authority
JP
Japan
Prior art keywords
epitaxial layer
semiconductor substrate
forming step
flow rate
dopant
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2010071059A
Other languages
English (en)
Japanese (ja)
Other versions
JP2010251737A (ja
JP2010251737A5 (enExample
Inventor
彰二 野上
彰二 野上
仁 五東
仁 五東
柴田 巧
巧 柴田
山本 剛
剛 山本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumco Corp
Denso Corp
Original Assignee
Sumco Corp
Denso Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumco Corp, Denso Corp filed Critical Sumco Corp
Priority to JP2010071059A priority Critical patent/JP5636203B2/ja
Publication of JP2010251737A publication Critical patent/JP2010251737A/ja
Publication of JP2010251737A5 publication Critical patent/JP2010251737A5/ja
Application granted granted Critical
Publication of JP5636203B2 publication Critical patent/JP5636203B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
    • H10D30/0297—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs using recessing of the gate electrodes, e.g. to form trench gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/01—Manufacture or treatment
    • H10D62/051—Forming charge compensation regions, e.g. superjunctions
    • H10D62/058—Forming charge compensation regions, e.g. superjunctions by using trenches, e.g. implanting into sidewalls of trenches or refilling trenches
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/109—Reduced surface field [RESURF] PN junction structures
    • H10D62/111—Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/24—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using chemical vapour deposition [CVD]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/29—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
    • H10P14/2901—Materials
    • H10P14/2902—Materials being Group IVA materials
    • H10P14/2905—Silicon, silicon germanium or germanium
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/32—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by intermediate layers between substrates and deposited layers
    • H10P14/3242—Structure
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
    • H10P14/3404—Deposited materials, e.g. layers characterised by the chemical composition being Group IVA materials
    • H10P14/3411—Silicon, silicon germanium or germanium
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3438—Doping during depositing
    • H10P14/3441—Conductivity type
    • H10P14/3442—N-type
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3438—Doping during depositing
    • H10P14/3441—Conductivity type
    • H10P14/3444—P-type
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/393—Body regions of DMOS transistors or IGBTs 

Landscapes

  • Recrystallisation Techniques (AREA)
JP2010071059A 2009-03-26 2010-03-25 半導体基板、半導体装置及び半導体基板の製造方法 Active JP5636203B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2010071059A JP5636203B2 (ja) 2009-03-26 2010-03-25 半導体基板、半導体装置及び半導体基板の製造方法

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2009076472 2009-03-26
JP2009076472 2009-03-26
JP2010071059A JP5636203B2 (ja) 2009-03-26 2010-03-25 半導体基板、半導体装置及び半導体基板の製造方法

Publications (3)

Publication Number Publication Date
JP2010251737A JP2010251737A (ja) 2010-11-04
JP2010251737A5 JP2010251737A5 (enExample) 2013-05-09
JP5636203B2 true JP5636203B2 (ja) 2014-12-03

Family

ID=42780588

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2010071059A Active JP5636203B2 (ja) 2009-03-26 2010-03-25 半導体基板、半導体装置及び半導体基板の製造方法

Country Status (5)

Country Link
US (1) US8501598B2 (enExample)
EP (1) EP2413348B1 (enExample)
JP (1) JP5636203B2 (enExample)
CN (1) CN102362336B (enExample)
WO (1) WO2010109892A1 (enExample)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5706674B2 (ja) * 2010-11-24 2015-04-22 セイコーインスツル株式会社 定電流回路及び基準電圧回路
JP5812029B2 (ja) 2012-06-13 2015-11-11 株式会社デンソー 炭化珪素半導体装置およびその製造方法
JP2013258327A (ja) * 2012-06-13 2013-12-26 Toshiba Corp 半導体装置及びその製造方法
JP2015162492A (ja) * 2014-02-26 2015-09-07 豊田合成株式会社 半導体装置の製造方法
JP6150075B2 (ja) * 2014-05-01 2017-06-21 信越半導体株式会社 エピタキシャルウェーハの製造方法
US10541338B2 (en) 2015-12-15 2020-01-21 General Electric Company Edge termination designs for silicon carbide super-junction power devices
CN106876463A (zh) * 2016-12-28 2017-06-20 全球能源互联网研究院 一种超结碳化硅器件及其制备方法
JP6857351B2 (ja) * 2017-02-28 2021-04-14 国立研究開発法人産業技術総合研究所 炭化珪素半導体装置および炭化珪素半導体装置の製造方法
JP7089329B2 (ja) * 2018-11-13 2022-06-22 株式会社豊田中央研究所 半導体装置とその製造方法
JP7077252B2 (ja) * 2019-02-27 2022-05-30 株式会社東芝 半導体装置の製造方法

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4773716B2 (ja) 2004-03-31 2011-09-14 株式会社デンソー 半導体基板の製造方法
CN100565801C (zh) * 2004-03-31 2009-12-02 株式会社电装 半导体器件的制造方法
JP3961503B2 (ja) * 2004-04-05 2007-08-22 株式会社Sumco 半導体ウェーハの製造方法
JP4939760B2 (ja) * 2005-03-01 2012-05-30 株式会社東芝 半導体装置
DE102006062821B4 (de) * 2005-09-29 2014-07-03 Denso Corporation Verfahren zur Fertigung einer Halbleitervorrichtung
JP5150048B2 (ja) * 2005-09-29 2013-02-20 株式会社デンソー 半導体基板の製造方法
JP5015440B2 (ja) * 2005-09-29 2012-08-29 株式会社デンソー 半導体基板の製造方法
WO2007116420A1 (en) * 2006-04-11 2007-10-18 Stmicroelectronics S.R.L. Process for manufacturing a semiconductor power device and respective device
JP5217257B2 (ja) 2007-06-06 2013-06-19 株式会社デンソー 半導体装置およびその製造方法

Also Published As

Publication number Publication date
EP2413348A1 (en) 2012-02-01
EP2413348B1 (en) 2020-11-18
EP2413348A4 (en) 2014-02-26
WO2010109892A1 (ja) 2010-09-30
JP2010251737A (ja) 2010-11-04
US8501598B2 (en) 2013-08-06
CN102362336A (zh) 2012-02-22
CN102362336B (zh) 2014-03-12
US20120032312A1 (en) 2012-02-09

Similar Documents

Publication Publication Date Title
JP2010251737A (ja) 半導体基板、半導体装置及び半導体基板の製造方法
US11646205B2 (en) Methods of selectively forming n-type doped material on a surface, systems for selectively forming n-type doped material, and structures formed using same
KR102806450B1 (ko) 희생 캡핑 층을 이용한 선택적 증착 방법
KR102645400B1 (ko) Iv족 반도체의 선택적 증착 방법 및 이와 관련된 반도체 소자 구조
KR102648942B1 (ko) 실리콘 함유 에피택셜층을 형성하기 위한 방법 및 관련 반도체 소자 구조체
US8685845B2 (en) Epitaxial growth of silicon doped with carbon and phosphorus using hydrogen carrier gas
JP5217257B2 (ja) 半導体装置およびその製造方法
KR102073170B1 (ko) 에피택셜 도핑된 게르마늄 주석 합금 형성 방법
TW202129063A (zh) 用於選擇性沉積經摻雜半導體材料之方法
US10205002B2 (en) Method of epitaxial growth shape control for CMOS applications
US10115826B2 (en) Semiconductor structure and the manufacturing method thereof
KR20130135087A (ko) 에피택셜 트렌치 필의 도펀트 프로파일 제어를 위한 방법 및 구조체
TWI677906B (zh) 選擇性磊晶的方法
CN102254796B (zh) 形成交替排列的p型和n型半导体薄层的方法
KR20170070281A (ko) 저온에서 얇은 에피택셜 필름들을 성장시키는 방법
US9035377B2 (en) Semiconductor device
KR20090035430A (ko) 실리콘 카본 에피택셜 층의 선택적 형성
CN101401202A (zh) 选择性沉积
CN104576389A (zh) 鳍式场效应管及其制作方法
JP2009535859A (ja) 炭素を混合したsi膜を使用した極浅接合形成の方法
JP4865290B2 (ja) 半導体基板の製造方法
CN101330100A (zh) 半导体衬底及其制造方法
JP2007103747A (ja) 半導体基板の製造方法
JP2006352092A (ja) 半導体基板及びその製造方法
US20260035835A1 (en) Methods for selectively depositing a boron doped silicon germanium layer on a surface of a substrate

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20130325

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20130325

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20140228

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20140401

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20140529

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20141007

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20141020

R150 Certificate of patent or registration of utility model

Ref document number: 5636203

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250