JP5617418B2 - 半導体基板の積層方法、半導体基板の積層装置およびデバイスの製造方法 - Google Patents

半導体基板の積層方法、半導体基板の積層装置およびデバイスの製造方法 Download PDF

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JP5617418B2
JP5617418B2 JP2010176468A JP2010176468A JP5617418B2 JP 5617418 B2 JP5617418 B2 JP 5617418B2 JP 2010176468 A JP2010176468 A JP 2010176468A JP 2010176468 A JP2010176468 A JP 2010176468A JP 5617418 B2 JP5617418 B2 JP 5617418B2
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semiconductor substrate
substrate
substrates
semiconductor
stacking
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JP2012038860A (ja
JP2012038860A5 (enExample
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菅谷　功
功 菅谷
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Nikon Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
JP2010176468A 2010-08-05 2010-08-05 半導体基板の積層方法、半導体基板の積層装置およびデバイスの製造方法 Active JP5617418B2 (ja)

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JP2010176468A JP5617418B2 (ja) 2010-08-05 2010-08-05 半導体基板の積層方法、半導体基板の積層装置およびデバイスの製造方法

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JP2010176468A JP5617418B2 (ja) 2010-08-05 2010-08-05 半導体基板の積層方法、半導体基板の積層装置およびデバイスの製造方法

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JP2012038860A JP2012038860A (ja) 2012-02-23
JP2012038860A5 JP2012038860A5 (enExample) 2013-10-10
JP5617418B2 true JP5617418B2 (ja) 2014-11-05

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Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5850412B2 (ja) * 2012-10-02 2016-02-03 株式会社デンソー 半導体装置の製造システム及び半導体装置の製造方法
JP6264831B2 (ja) * 2012-11-06 2018-01-24 株式会社ニコン アライメント装置、位置合わせ方法、及び、積層半導体装置の製造方法
JP6600838B2 (ja) * 2016-03-08 2019-11-06 ボンドテック株式会社 アライメント装置およびアライメント方法
WO2018012300A1 (ja) * 2016-07-12 2018-01-18 株式会社ニコン 積層基板製造方法、積層基板製造装置、積層基板製造システム、および基板処理装置
WO2019087707A1 (ja) * 2017-11-02 2019-05-09 株式会社ニコン 積層基板の製造方法、製造装置、およびプログラム
TWI850225B (zh) 2018-04-12 2024-08-01 日商尼康股份有限公司 位置對準方法及位置對準裝置
US11335607B2 (en) * 2020-07-09 2022-05-17 Tokyo Electron Limited Apparatus and methods for wafer to wafer bonding

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* Cited by examiner, † Cited by third party
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JP4543935B2 (ja) * 2005-01-17 2010-09-15 パナソニック株式会社 電子部品実装装置及び実装方法
JP5343847B2 (ja) * 2007-06-12 2013-11-13 株式会社ニコン ウェハ貼り合せ装置、ウェハ貼り合せ方法
WO2010023935A1 (ja) * 2008-08-29 2010-03-04 株式会社ニコン 基板位置合わせ装置、基板位置合わせ方法および積層型半導体の製造方法

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