JP5581106B2 - 半導体装置の作製方法 - Google Patents

半導体装置の作製方法 Download PDF

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Publication number
JP5581106B2
JP5581106B2 JP2010099455A JP2010099455A JP5581106B2 JP 5581106 B2 JP5581106 B2 JP 5581106B2 JP 2010099455 A JP2010099455 A JP 2010099455A JP 2010099455 A JP2010099455 A JP 2010099455A JP 5581106 B2 JP5581106 B2 JP 5581106B2
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Japan
Prior art keywords
layer
wiring
substrate
film
semiconductor element
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Expired - Fee Related
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JP2010099455A
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English (en)
Japanese (ja)
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JP2010278425A5 (https=
JP2010278425A (ja
Inventor
真弓 三上
小波 泉
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Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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Priority to JP2010099455A priority Critical patent/JP5581106B2/ja
Publication of JP2010278425A publication Critical patent/JP2010278425A/ja
Publication of JP2010278425A5 publication Critical patent/JP2010278425A5/ja
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0214—Manufacture or treatment of multiple TFTs using temporary substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/297—Configurations of stacked chips characterised by the through-semiconductor vias [TSVs] in the stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips

Landscapes

  • Thin Film Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP2010099455A 2009-04-27 2010-04-23 半導体装置の作製方法 Expired - Fee Related JP5581106B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2010099455A JP5581106B2 (ja) 2009-04-27 2010-04-23 半導体装置の作製方法

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2009108129 2009-04-27
JP2009108129 2009-04-27
JP2010099455A JP5581106B2 (ja) 2009-04-27 2010-04-23 半導体装置の作製方法

Related Child Applications (1)

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JP2014142057A Division JP5917618B2 (ja) 2009-04-27 2014-07-10 半導体装置の作製方法

Publications (3)

Publication Number Publication Date
JP2010278425A JP2010278425A (ja) 2010-12-09
JP2010278425A5 JP2010278425A5 (https=) 2013-03-14
JP5581106B2 true JP5581106B2 (ja) 2014-08-27

Family

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Family Applications (2)

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JP2010099455A Expired - Fee Related JP5581106B2 (ja) 2009-04-27 2010-04-23 半導体装置の作製方法
JP2014142057A Active JP5917618B2 (ja) 2009-04-27 2014-07-10 半導体装置の作製方法

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Country Status (2)

Country Link
US (1) US8435870B2 (https=)
JP (2) JP5581106B2 (https=)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
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FR2996682B1 (fr) 2012-10-10 2014-11-28 Commissariat Energie Atomique Procede ameliore d'interconnexion pour micro-imageur
US9252047B2 (en) 2014-01-23 2016-02-02 Taiwan Semiconductor Manufacturing Co., Ltd Interconnect arrangement with stress-reducing structure and method of fabricating the same
US9443872B2 (en) 2014-03-07 2016-09-13 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
JP6917700B2 (ja) 2015-12-02 2021-08-11 株式会社半導体エネルギー研究所 半導体装置
US10586817B2 (en) * 2016-03-24 2020-03-10 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, manufacturing method thereof, and separation apparatus
US10181424B2 (en) * 2016-04-12 2019-01-15 Semiconductor Energy Laboratory Co., Ltd. Peeling method and manufacturing method of flexible device
CN109075079B (zh) * 2016-04-22 2022-04-15 株式会社半导体能源研究所 剥离方法及柔性装置的制造方法

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JPH0463944A (ja) 1990-06-30 1992-02-28 Nippondenso Co Ltd 燃料噴射制御装置
US5757456A (en) * 1995-03-10 1998-05-26 Semiconductor Energy Laboratory Co., Ltd. Display device and method of fabricating involving peeling circuits from one substrate and mounting on other
JP3579492B2 (ja) 1995-03-16 2004-10-20 株式会社半導体エネルギー研究所 表示装置の作製方法
EP0802564A3 (en) * 1996-04-19 1999-02-24 Nec Corporation Semiconductor device having high resistive element including high melting point metal
JP4063944B2 (ja) 1998-03-13 2008-03-19 独立行政法人科学技術振興機構 ３次元半導体集積回路装置の製造方法
JP2003336016A (ja) 2002-05-20 2003-11-28 Nippon Telegr & Teleph Corp <Ntt> 異方導電性両面テープとそれを用いた電子部品の実装方法
JP4554152B2 (ja) * 2002-12-19 2010-09-29 株式会社半導体エネルギー研究所 半導体チップの作製方法
EP1434264A3 (en) * 2002-12-27 2017-01-18 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method using the transfer technique
JP4408042B2 (ja) 2002-12-27 2010-02-03 株式会社半導体エネルギー研究所 半導体装置及びその作製方法
JP2004247373A (ja) * 2003-02-12 2004-09-02 Semiconductor Energy Lab Co Ltd 半導体装置
JP3990347B2 (ja) * 2003-12-04 2007-10-10 ローム株式会社 半導体チップおよびその製造方法、ならびに半導体装置
JP4749102B2 (ja) 2004-09-24 2011-08-17 株式会社半導体エネルギー研究所 半導体装置の作製方法
US7422935B2 (en) * 2004-09-24 2008-09-09 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device, and semiconductor device and electronic device
WO2006038305A1 (ja) * 2004-10-01 2006-04-13 Tadahiro Ohmi 半導体装置およびその製造方法
JP5072210B2 (ja) * 2004-10-05 2012-11-14 株式会社半導体エネルギー研究所 半導体装置の作製方法
JP2006245544A (ja) * 2005-01-28 2006-09-14 Semiconductor Energy Lab Co Ltd パターン付基板及びその形成方法、並びに半導体装置及びその作製方法
CN101233394B (zh) * 2005-07-27 2014-02-26 株式会社半导体能源研究所 半导体装置
JP2007059889A (ja) 2005-07-27 2007-03-08 Semiconductor Energy Lab Co Ltd 半導体装置
JP5127178B2 (ja) * 2005-07-29 2013-01-23 株式会社半導体エネルギー研究所 半導体装置の作製方法
JP2007280368A (ja) 2006-03-15 2007-10-25 Semiconductor Energy Lab Co Ltd 半導体装置及び当該半導体装置を具備するｉｄラベル、ｉｄタグ、ｉｄカード
EP2002383B1 (en) * 2006-03-15 2012-04-25 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
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JP5227536B2 (ja) * 2006-04-28 2013-07-03 株式会社半導体エネルギー研究所 半導体集積回路の作製方法
JP2007317969A (ja) 2006-05-26 2007-12-06 Rohm Co Ltd 半導体装置及び半導体装置の製造方法
JP2008217776A (ja) 2007-02-09 2008-09-18 Semiconductor Energy Lab Co Ltd 半導体装置
US7759629B2 (en) * 2007-03-20 2010-07-20 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing a semiconductor device
US8513678B2 (en) * 2007-05-18 2013-08-20 Semiconductor Energy Laboratory Co., Ltd. Light-emitting device
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US8422837B2 (en) * 2008-02-28 2013-04-16 Nec Corporation Semiconductor device
JP5216716B2 (ja) * 2008-08-20 2013-06-19 株式会社半導体エネルギー研究所 発光装置及びその作製方法
US8198666B2 (en) * 2009-02-20 2012-06-12 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device including a nonvolatile memory element having first, second and third insulating films
JP5677016B2 (ja) * 2010-10-15 2015-02-25 キヤノン株式会社 電気機械変換装置及びその作製方法
JP2012216812A (ja) * 2011-03-31 2012-11-08 Elpida Memory Inc 半導体装置及びその製造方法
US8481353B2 (en) * 2011-04-14 2013-07-09 Opto Tech Corporation Method of separating nitride films from the growth substrates by selective photo-enhanced wet oxidation

Also Published As

Publication number Publication date
JP2014222766A (ja) 2014-11-27
JP5917618B2 (ja) 2016-05-18
JP2010278425A (ja) 2010-12-09
US20100273319A1 (en) 2010-10-28
US8435870B2 (en) 2013-05-07

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